src/gallium/drivers/radeon/R600InstrInfo.cpp

   1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Implementation of TargetInstrInfo.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "R600InstrInfo.h"
  15 #include "AMDGPUTargetMachine.h"
  16 #include "AMDILSubtarget.h"
  17 #include "R600RegisterInfo.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19
  20 #define GET_INSTRINFO_CTOR
  21 #include "AMDGPUGenDFAPacketizer.inc"
  22
  23 using namespace llvm;
  24
  25 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
  26   : AMDGPUInstrInfo(tm),
  27     RI(tm, *this),
  28     TM(tm)
  29   { }
  30
  31 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const
  32 {
  33   return RI;
  34 }
  35
  36 bool R600InstrInfo::isTrig(const MachineInstr &MI) const
  37 {
  38   return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
  39 }
  40
  41 bool R600InstrInfo::isVector(const MachineInstr &MI) const
  42 {
  43   return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
  44 }
  45
  46 void
  47 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  48                            MachineBasicBlock::iterator MI, DebugLoc DL,
  49                            unsigned DestReg, unsigned SrcReg,
  50                            bool KillSrc) const
  51 {
  52
  53   unsigned subRegMap[4] = {AMDGPU::sel_x, AMDGPU::sel_y,
  54                            AMDGPU::sel_z, AMDGPU::sel_w};
  55
  56   if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
  57       && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
  58     for (unsigned i = 0; i < 4; i++) {
  59       BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
  60               .addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define)
  61               .addReg(RI.getSubReg(SrcReg, subRegMap[i]))
  62               .addReg(DestReg, RegState::Define | RegState::Implicit);
  63     }
  64   } else {
  65
  66     /* We can't copy vec4 registers */
  67     assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
  68            && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
  69
  70     BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
  71       .addReg(SrcReg, getKillRegState(KillSrc));
  72   }
  73 }
  74
  75 MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
  76                                              unsigned DstReg, int64_t Imm) const
  77 {
  78   MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
  79   MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
  80   MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
  81   MachineInstrBuilder(MI).addImm(Imm);
  82
  83   return MI;
  84 }
  85
  86 unsigned R600InstrInfo::getIEQOpcode() const
  87 {
  88   return AMDGPU::SETE_INT;
  89 }
  90
  91 bool R600InstrInfo::isMov(unsigned Opcode) const
  92 {
  93   switch(Opcode) {
  94   default: return false;
  95   case AMDGPU::MOV:
  96   case AMDGPU::MOV_IMM_F32:
  97   case AMDGPU::MOV_IMM_I32:
  98     return true;
  99   }
 100 }
 101
 102 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
 103     const ScheduleDAG *DAG) const
 104 {
 105   const InstrItineraryData *II = TM->getInstrItineraryData();
 106   return TM->getSubtarget<AMDILSubtarget>().createDFAPacketizer(II);
 107 }