src/gallium/drivers/radeon/R600InstrInfo.cpp

   1 //===-- R600InstrInfo.cpp - TODO: Add brief description -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // TODO: Add full description
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "R600InstrInfo.h"
  15 #include "AMDGPUTargetMachine.h"
  16 #include "R600RegisterInfo.h"
  17
  18 using namespace llvm;
  19
  20 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
  21   : AMDGPUInstrInfo(tm),
  22     RI(tm, *this),
  23     TM(tm)
  24   { }
  25
  26 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const
  27 {
  28   return RI;
  29 }
  30
  31 bool R600InstrInfo::isTrig(const MachineInstr &MI) const
  32 {
  33   return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
  34 }
  35
  36 void
  37 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  38                            MachineBasicBlock::iterator MI, DebugLoc DL,
  39                            unsigned DestReg, unsigned SrcReg,
  40                            bool KillSrc) const
  41 {
  42   if (!TargetRegisterInfo::isVirtualRegister(SrcReg)
  43       && AMDIL::GPRI32RegClass.contains(SrcReg)) {
  44     SrcReg = AMDIL::T0_X;
  45   }
  46   BuildMI(MBB, MI, DL, get(AMDIL::MOV), DestReg)
  47     .addReg(SrcReg, getKillRegState(KillSrc));
  48 }
  49
  50 unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
  51 {
  52   switch (opcode) {
  53     default: return AMDGPUInstrInfo::getISAOpcode(opcode);
  54     case AMDIL::CUSTOM_ADD_i32:
  55       return AMDIL::ADD_INT;
  56     case AMDIL::CUSTOM_XOR_i32:
  57       return AMDIL::XOR_INT;
  58     case AMDIL::MOVE_f32:
  59     case AMDIL::MOVE_i32:
  60       return AMDIL::MOV;
  61     case AMDIL::SHR_i32:
  62       return getLSHRop();
  63   }
  64 }
  65
  66 unsigned R600InstrInfo::getLSHRop() const
  67 {
  68   unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
  69   if (gen < AMDILDeviceInfo::HD5XXX) {
  70     return AMDIL::LSHR_r600;
  71   } else {
  72     return AMDIL::LSHR_eg;
  73   }
  74 }
  75
  76 unsigned R600InstrInfo::getMULHI_UINT() const
  77 {
  78   unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
  79
  80   if (gen < AMDILDeviceInfo::HD5XXX) {
  81     return AMDIL::MULHI_UINT_r600;
  82   } else {
  83     return AMDIL::MULHI_UINT_eg;
  84   }
  85 }
  86
  87 unsigned R600InstrInfo::getMULLO_UINT() const
  88 {
  89   unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
  90
  91   if (gen < AMDILDeviceInfo::HD5XXX) {
  92     return AMDIL::MULLO_UINT_r600;
  93   } else {
  94     return AMDIL::MULLO_UINT_eg;
  95   }
  96 }
  97
  98 unsigned R600InstrInfo::getRECIP_UINT() const
  99 {
 100   const AMDILDevice * dev = TM.getSubtarget<AMDILSubtarget>().device();
 101
 102   if (dev->getGeneration() < AMDILDeviceInfo::HD5XXX) {
 103     return AMDIL::RECIP_UINT_r600;
 104   } else if (dev->getDeviceFlag() != OCL_DEVICE_CAYMAN) {
 105     return AMDIL::RECIP_UINT_eg;
 106   } else {
 107     return AMDIL::RECIP_UINT_cm;
 108   }
 109 }