src/gallium/drivers/radeon/R600InstrInfo.h

   1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Interface definition for R600InstrInfo
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef R600INSTRUCTIONINFO_H_
  15 #define R600INSTRUCTIONINFO_H_
  16
  17 #include "AMDIL.h"
  18 #include "AMDILInstrInfo.h"
  19 #include "R600RegisterInfo.h"
  20
  21 #include <map>
  22
  23 namespace llvm {
  24
  25   class AMDGPUTargetMachine;
  26   class DFAPacketizer;
  27   class ScheduleDAG;
  28   class MachineFunction;
  29   class MachineInstr;
  30   class MachineInstrBuilder;
  31
  32   class R600InstrInfo : public AMDGPUInstrInfo {
  33   private:
  34   const R600RegisterInfo RI;
  35   AMDGPUTargetMachine &TM;
  36
  37   public:
  38   explicit R600InstrInfo(AMDGPUTargetMachine &tm);
  39
  40   const R600RegisterInfo &getRegisterInfo() const;
  41   virtual void copyPhysReg(MachineBasicBlock &MBB,
  42                            MachineBasicBlock::iterator MI, DebugLoc DL,
  43                            unsigned DestReg, unsigned SrcReg,
  44                            bool KillSrc) const;
  45
  46   bool isTrig(const MachineInstr &MI) const;
  47
  48   /// isVector - Vector instructions are instructions that must fill all
  49   /// instruction slots within an instruction group.
  50   bool isVector(const MachineInstr &MI) const;
  51
  52   virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
  53                                         int64_t Imm) const;
  54
  55   virtual unsigned getIEQOpcode() const;
  56   virtual bool isMov(unsigned Opcode) const;
  57
  58   DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
  59                                            const ScheduleDAG *DAG) const;
  60 };
  61
  62 } // End llvm namespace
  63
  64 namespace R600_InstFlag {
  65         enum TIF {
  66                 TRANS_ONLY = (1 << 0),
  67                 TEX = (1 << 1),
  68                 REDUCTION = (1 << 2),
  69                 FC = (1 << 3),
  70                 TRIG = (1 << 4),
  71                 OP3 = (1 << 5),
  72                 VECTOR = (1 << 6)
  73         };
  74 }
  75
  76 #endif // R600INSTRINFO_H_