radeon/llvm: Fix MULLO* instructions on Cayman
[mesa.git] / src / gallium / drivers / radeon / R600InstrInfo.h
1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Interface definition for R600InstrInfo
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef R600INSTRUCTIONINFO_H_
15 #define R600INSTRUCTIONINFO_H_
16
17 #include "AMDIL.h"
18 #include "AMDILInstrInfo.h"
19 #include "R600RegisterInfo.h"
20
21 #include <map>
22
23 namespace llvm {
24
25 class AMDGPUTargetMachine;
26 class MachineFunction;
27 class MachineInstr;
28 class MachineInstrBuilder;
29
30 class R600InstrInfo : public AMDGPUInstrInfo {
31 private:
32 const R600RegisterInfo RI;
33 AMDGPUTargetMachine &TM;
34
35 public:
36 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
37
38 const R600RegisterInfo &getRegisterInfo() const;
39 virtual void copyPhysReg(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MI, DebugLoc DL,
41 unsigned DestReg, unsigned SrcReg,
42 bool KillSrc) const;
43
44 bool isTrig(const MachineInstr &MI) const;
45
46 /// isVector - Vector instructions are instructions that must fill all
47 /// instruction slots within an instruction group.
48 bool isVector(const MachineInstr &MI) const;
49
50 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
51 int64_t Imm) const;
52
53 virtual unsigned getIEQOpcode() const;
54 virtual bool isMov(unsigned Opcode) const;
55 };
56
57 } // End llvm namespace
58
59 namespace R600_InstFlag {
60 enum TIF {
61 TRANS_ONLY = (1 << 0),
62 TEX = (1 << 1),
63 REDUCTION = (1 << 2),
64 FC = (1 << 3),
65 TRIG = (1 << 4),
66 OP3 = (1 << 5),
67 VECTOR = (1 << 6)
68 };
69 }
70
71 #endif // R600INSTRINFO_H_