src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Tablegen instruction definitions
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<32> Inst;
  21         bit Trig = 0;
  22   bit Op3 = 0;
  23
  24   let Inst = inst;
  25   let Namespace = "AMDIL";
  26   let OutOperandList = outs;
  27   let InOperandList = ins;
  28   let AsmString = asm;
  29   let Pattern = pattern;
  30   let Itinerary = itin;
  31
  32   let TSFlags{4} = Trig;
  33   let TSFlags{5} = Op3;
  34 }
  35
  36 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  37     AMDGPUInst <outs, ins, asm, pattern>
  38 {
  39   field bits<64> Inst;
  40
  41   let Namespace = "AMDIL";
  42 }
  43
  44 def MEMri : Operand<iPTRAny> {
  45   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  46 }
  47
  48 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  49
  50 class R600_ALU {
  51
  52   bits<7> DST_GPR = 0;
  53   bits<9> SRC0_SEL = 0;
  54   bits<1> SRC0_NEG = 0;
  55   bits<9> SRC1_SEL = 0;
  56   bits<1> SRC1_NEG = 0;
  57   bits<1> CLAMP = 0;
  58
  59 }
  60
  61
  62 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
  63                 InstrItinClass itin = AnyALU> :
  64   InstR600 <inst,
  65           (outs R600_Reg32:$dst),
  66           (ins R600_Reg32:$src, variable_ops),
  67           !strconcat(opName, " $dst, $src"),
  68           pattern,
  69           itin
  70   >;
  71
  72 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
  73                 InstrItinClass itin = AnyALU> :
  74   InstR600 <inst,
  75           (outs R600_Reg32:$dst),
  76           (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
  77           !strconcat(opName, " $dst, $src0, $src1"),
  78           pattern,
  79           itin
  80   >;
  81
  82 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
  83                 InstrItinClass itin = AnyALU> :
  84   InstR600 <inst,
  85           (outs R600_Reg32:$dst),
  86           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
  87           !strconcat(opName, " $dst, $src0, $src1, $src2"),
  88           pattern,
  89           itin>{
  90
  91     let Op3 = 1;
  92   }
  93
  94 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
  95                       InstrItinClass itin = VecALU> :
  96   InstR600 <inst,
  97           (outs R600_Reg32:$dst),
  98           ins,
  99           asm,
 100           pattern,
 101           itin
 102
 103   >;
 104
 105 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
 106                 InstrItinClass itin = AnyALU> :
 107   InstR600 <inst,
 108           (outs R600_Reg128:$dst),
 109           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 110           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 111           pattern,
 112           itin
 113   >;
 114
 115 def TEX_SHADOW : PatLeaf<
 116   (imm),
 117   [{uint32_t TType = (uint32_t)N->getZExtValue();
 118     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 119   }]
 120 >;
 121
 122 def FP_ZERO : PatLeaf <
 123   (fpimm),
 124   [{return N->getValueAPF().isZero();}]
 125 >;
 126
 127 def FP_ONE : PatLeaf <
 128   (fpimm),
 129   [{return N->isExactlyValue(1.0);}]
 130 >;
 131
 132 def COND_EQ : PatLeaf <
 133   (cond),
 134   [{switch(N->get()){{default: return false;
 135                      case ISD::SETOEQ: case ISD::SETUEQ:
 136                      case ISD::SETEQ: return true;}}}]
 137 >;
 138
 139 def COND_NE : PatLeaf <
 140   (cond),
 141   [{switch(N->get()){{default: return false;
 142                      case ISD::SETONE: case ISD::SETUNE:
 143                      case ISD::SETNE: return true;}}}]
 144 >;
 145 def COND_GT : PatLeaf <
 146   (cond),
 147   [{switch(N->get()){{default: return false;
 148                      case ISD::SETOGT: case ISD::SETUGT:
 149                      case ISD::SETGT: return true;}}}]
 150 >;
 151
 152 def COND_GE : PatLeaf <
 153   (cond),
 154   [{switch(N->get()){{default: return false;
 155                      case ISD::SETOGE: case ISD::SETUGE:
 156                      case ISD::SETGE: return true;}}}]
 157 >;
 158
 159 def COND_LT : PatLeaf <
 160   (cond),
 161   [{switch(N->get()){{default: return false;
 162                      case ISD::SETOLT: case ISD::SETULT:
 163                      case ISD::SETLT: return true;}}}]
 164 >;
 165
 166 def COND_LE : PatLeaf <
 167   (cond),
 168   [{switch(N->get()){{default: return false;
 169                      case ISD::SETOLE: case ISD::SETULE:
 170                      case ISD::SETLE: return true;}}}]
 171 >;
 172
 173 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
 174                  string asm> :
 175     InstR600ISA <outs, ins, asm, []>
 176 {
 177   bits<7>  RW_GPR;
 178   bits<7>  INDEX_GPR;
 179   bits<4>  RAT_ID;
 180
 181   bits<2>  RIM;
 182   bits<2>  TYPE;
 183   bits<1>  RW_REL;
 184   bits<2>  ELEM_SIZE;
 185
 186   bits<12> ARRAY_SIZE;
 187   bits<4>  COMP_MASK;
 188   bits<4>  BURST_COUNT;
 189   bits<1>  VPM;
 190   bits<1>  EOP;
 191   bits<1>  MARK;
 192   bits<1>  BARRIER;
 193
 194   /* CF_ALLOC_EXPORT_WORD0_RAT */
 195   let Inst{3-0}   = RAT_ID;
 196   let Inst{9-4}   = rat_inst;
 197   let Inst{10}    = 0; /* Reserved */
 198   let Inst{12-11} = RIM;
 199   let Inst{14-13} = TYPE;
 200   let Inst{21-15} = RW_GPR;
 201   let Inst{22}    = RW_REL;
 202   let Inst{29-23} = INDEX_GPR;
 203   let Inst{31-30} = ELEM_SIZE;
 204
 205   /* CF_ALLOC_EXPORT_WORD1_BUF */
 206   let Inst{43-32} = ARRAY_SIZE;
 207   let Inst{47-44} = COMP_MASK;
 208   let Inst{51-48} = BURST_COUNT;
 209   let Inst{52}    = VPM;
 210   let Inst{53}    = EOP;
 211   let Inst{61-54} = cf_inst;
 212   let Inst{62}    = MARK;
 213   let Inst{63}    = BARRIER;
 214 }
 215
 216 /*
 217 def store_global : PatFrag<(ops node:$value, node:$ptr),
 218                            (store node:$value, node:$ptr),
 219                            [{
 220                             const Value *Src;
 221                             const PointerType *Type;
 222                             if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
 223                                  PT = dyn_cast<PointerType>(Src->getType()))) {
 224                               return PT->getAddressSpace() == 1;
 225                             }
 226                             return false;
 227                            }]>;
 228
 229 */
 230
 231 def load_param : PatFrag<(ops node:$ptr),
 232                          (load node:$ptr),
 233                           [{
 234                            return true;
 235                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 236                            if (Src) {
 237                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 238                                 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
 239                            }
 240                            return false;
 241                           }]>;
 242
 243 //class EG_CF <bits<32> inst, string asm> :
 244 //    InstR600 <inst, (outs), (ins), asm, []>;
 245
 246 /* XXX: We will use this when we emit the real ISA.
 247   bits<24> ADDR = 0;
 248   bits<3> JTS = 0;
 249
 250   bits<3> PC = 0;
 251   bits<5> CF_CONS = 0;
 252   bits<2> COND = 0;
 253   bits<6> COUNT = 0;
 254   bits<1> VPM = 0;
 255   bits<1> EOP = 0;
 256   bits<8> CF_INST = 0;
 257   bits<1> WQM = 0;
 258   bits<1> B = 0;
 259
 260   let Inst{23-0} = ADDR;
 261   let Inst{26-24} = JTS;
 262   let Inst{34-32} = PC;
 263   let Inst{39-35} = CF_CONST;
 264   let Inst{41-40} = COND;
 265   let Inst{47-42} = COUNT;
 266   let Inst{52} = VPM;
 267   let Inst{53} = EOP;
 268   let Inst{61-54} = CF_INST;
 269   let Inst{62} = WQM;
 270   let Inst{63} = B;
 271 //}
 272 */
 273 def isR600 : Predicate<"Subtarget.device()"
 274                             "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
 275 def isEG : Predicate<"Subtarget.device()"
 276                             "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
 277                             "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 278 def isCayman : Predicate<"Subtarget.device()"
 279                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 280 def isEGorCayman : Predicate<"Subtarget.device()"
 281                             "->getGeneration() == AMDILDeviceInfo::HD5XXX"
 282                             "|| Subtarget.device()->getGeneration() =="
 283                             "AMDILDeviceInfo::HD6XXX">;
 284
 285 def isR600toCayman : Predicate<
 286                      "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
 287
 288
 289 let Predicates = [isR600toCayman] in {
 290
 291 /* ------------------------------------------- */
 292 /* Common Instructions R600, R700, Evergreen, Cayman */
 293 /* ------------------------------------------- */
 294 def ADD : R600_2OP <
 295   0x0, "ADD",
 296   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
 297 >;
 298
 299 // Non-IEEE MUL: 0 * anything = 0
 300 def MUL : R600_2OP <
 301   0x1, "MUL NON-IEEE",
 302   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 303 >;
 304
 305 def MUL_IEEE : R600_2OP <
 306   0x2, "MUL_IEEE",
 307   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
 308 >;
 309
 310 def MAX : R600_2OP <
 311   0x3, "MAX",
 312   [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
 313 >;
 314
 315 def MIN : R600_2OP <
 316   0x4, "MIN",
 317   [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
 318 >;
 319
 320 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 321  * so some of the instruction names don't match the asm string.
 322  * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 323  */
 324
 325 def SETE : R600_2OP <
 326   0x08, "SETE",
 327   [(set R600_Reg32:$dst,
 328    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 329              COND_EQ))]
 330 >;
 331
 332 def SGT : R600_2OP <
 333   0x09, "SETGT",
 334   [(set R600_Reg32:$dst,
 335    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 336               COND_GT))]
 337 >;
 338
 339 def SGE : R600_2OP <
 340   0xA, "SETGE",
 341   [(set R600_Reg32:$dst,
 342    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 343               COND_GE))]
 344 >;
 345
 346 def SNE : R600_2OP <
 347   0xB, "SETNE",
 348   [(set R600_Reg32:$dst,
 349    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 350     COND_NE))]
 351 >;
 352
 353 def FRACT : R600_1OP <
 354   0x10, "FRACT",
 355   [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
 356 >;
 357
 358 def TRUNC : R600_1OP <
 359   0x11, "TRUNC",
 360   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 361 >;
 362
 363 def CEIL : R600_1OP <
 364   0x12, "CEIL",
 365   [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
 366 >;
 367
 368 def RNDNE : R600_1OP <
 369   0x13, "RNDNE",
 370   [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
 371 >;
 372
 373 def FLOOR : R600_1OP <
 374   0x14, "FLOOR",
 375   [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
 376 >;
 377
 378 def MOV : R600_1OP <0x19, "MOV", []>;
 379
 380 def KILLGT : R600_2OP <
 381   0x2D, "KILLGT",
 382   []
 383 >;
 384
 385 def AND_INT : R600_2OP <
 386   0x30, "AND_INT",
 387   [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
 388 >;
 389
 390 def OR_INT : R600_2OP <
 391   0x31, "OR_INT",
 392   [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
 393 >;
 394
 395 def XOR_INT : R600_2OP <
 396   0x32, "XOR_INT",
 397   [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
 398 >;
 399
 400 def NOT_INT : R600_1OP <
 401   0x33, "NOT_INT",
 402   [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
 403 >;
 404
 405 def ADD_INT : R600_2OP <
 406   0x34, "ADD_INT",
 407   [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
 408 >;
 409
 410 def SUB_INT : R600_2OP <
 411         0x35, "SUB_INT",
 412         [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
 413 >;
 414
 415 def MAX_INT : R600_2OP <
 416   0x36, "MAX_INT",
 417   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 418
 419 def MIN_INT : R600_2OP <
 420   0x37, "MIN_INT",
 421   [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 422
 423 def MAX_UINT : R600_2OP <
 424   0x38, "MAX_UINT",
 425   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
 426 >;
 427
 428 def MIN_UINT : R600_2OP <
 429   0x39, "MIN_UINT",
 430   [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
 431 >;
 432
 433 def SETE_INT : R600_2OP <
 434   0x3A, "SETE_INT",
 435   [(set (i32 R600_Reg32:$dst),
 436    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
 437 >;
 438
 439 def SETGT_INT : R600_2OP <
 440   0x3B, "SGT_INT",
 441   [(set (i32 R600_Reg32:$dst),
 442    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
 443 >;
 444
 445 def SETGE_INT : R600_2OP <
 446         0x3C, "SETGE_INT",
 447         [(set (i32 R600_Reg32:$dst),
 448    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
 449 >;
 450
 451 def SETNE_INT : R600_2OP <
 452   0x3D, "SETNE_INT",
 453   [(set (i32 R600_Reg32:$dst),
 454    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
 455 >;
 456
 457 def SETGT_UINT : R600_2OP <
 458   0x3E, "SETGT_UINT",
 459   [(set (i32 R600_Reg32:$dst),
 460    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
 461 >;
 462
 463 def SETGE_UINT : R600_2OP <
 464   0x3F, "SETGE_UINT",
 465   [(set (i32 R600_Reg32:$dst),
 466     (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
 467 >;
 468
 469 def CNDE_INT : R600_3OP <
 470         0x1C, "CNDE_INT",
 471   [(set (i32 R600_Reg32:$dst),
 472    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 473 >;
 474
 475 /* Texture instructions */
 476
 477
 478 def TEX_LD : R600_TEX <
 479   0x03, "TEX_LD",
 480   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
 481 > {
 482 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
 483 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
 484 }
 485
 486 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 487   0x04, "TEX_GET_TEXTURE_RESINFO",
 488   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 489 >;
 490
 491 def TEX_GET_GRADIENTS_H : R600_TEX <
 492   0x07, "TEX_GET_GRADIENTS_H",
 493   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 494 >;
 495
 496 def TEX_GET_GRADIENTS_V : R600_TEX <
 497   0x08, "TEX_GET_GRADIENTS_V",
 498   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 499 >;
 500
 501 def TEX_SET_GRADIENTS_H : R600_TEX <
 502   0x0B, "TEX_SET_GRADIENTS_H",
 503   []
 504 >;
 505
 506 def TEX_SET_GRADIENTS_V : R600_TEX <
 507   0x0C, "TEX_SET_GRADIENTS_V",
 508   []
 509 >;
 510
 511 def TEX_SAMPLE : R600_TEX <
 512   0x10, "TEX_SAMPLE",
 513   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 514 >;
 515
 516 def TEX_SAMPLE_C : R600_TEX <
 517   0x18, "TEX_SAMPLE_C",
 518   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 519 >;
 520
 521 def TEX_SAMPLE_L : R600_TEX <
 522   0x11, "TEX_SAMPLE_L",
 523   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 524 >;
 525
 526 def TEX_SAMPLE_C_L : R600_TEX <
 527   0x19, "TEX_SAMPLE_C_L",
 528   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 529 >;
 530
 531 def TEX_SAMPLE_LB : R600_TEX <
 532   0x12, "TEX_SAMPLE_LB",
 533   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 534 >;
 535
 536 def TEX_SAMPLE_C_LB : R600_TEX <
 537   0x1A, "TEX_SAMPLE_C_LB",
 538   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 539 >;
 540
 541 def TEX_SAMPLE_G : R600_TEX <
 542   0x14, "TEX_SAMPLE_G",
 543   []
 544 >;
 545
 546 def TEX_SAMPLE_C_G : R600_TEX <
 547   0x1C, "TEX_SAMPLE_C_G",
 548   []
 549 >;
 550
 551 def KILP : Pat <
 552   (int_AMDGPU_kilp),
 553   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
 554 >;
 555
 556 def KIL : Pat <
 557   (int_AMDGPU_kill R600_Reg32:$src0),
 558   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
 559 >;
 560
 561 /* Helper classes for common instructions */
 562
 563 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
 564   inst, "MUL_LIT",
 565   []
 566 >;
 567
 568 class MULADD_Common <bits<32> inst> : R600_3OP <
 569   inst, "MULADD",
 570   [(set (f32 R600_Reg32:$dst),
 571    (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 572 >;
 573
 574 class CNDE_Common <bits<32> inst> : R600_3OP <
 575   inst, "CNDE",
 576   [(set (f32 R600_Reg32:$dst),
 577    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 578 >;
 579
 580 class CNDGT_Common <bits<32> inst> : R600_3OP <
 581   inst, "CNDGT",
 582   []
 583 >;
 584
 585 class CNDGE_Common <bits<32> inst> : R600_3OP <
 586   inst, "CNDGE",
 587   [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 588 >;
 589
 590 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
 591   inst,
 592   (ins R600_Reg128:$src0, R600_Reg128:$src1),
 593   "DOT4 $dst $src0, $src1",
 594   [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 595 >;
 596
 597 class CUBE_Common <bits<32> inst> : InstR600 <
 598   inst,
 599   (outs R600_Reg128:$dst),
 600   (ins R600_Reg128:$src),
 601   "CUBE $dst $src",
 602   [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 603   VecALU
 604 >;
 605
 606 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
 607   inst, "EXP_IEEE",
 608   [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
 609 >;
 610
 611 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
 612   inst, "FLT_TO_INT",
 613   [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))]
 614 >;
 615
 616 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 617   inst, "INT_TO_FLT",
 618   [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
 619 >;
 620
 621 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 622   inst, "LOG_CLAMPED",
 623   []
 624 >;
 625
 626 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
 627   inst, "LOG_IEEE",
 628   [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
 629 >;
 630
 631 class LSHL_Common <bits<32> inst> : R600_2OP <
 632   inst, "LSHL $dst, $src0, $src1",
 633   [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
 634 >;
 635
 636 class LSHR_Common <bits<32> inst> : R600_2OP <
 637   inst, "LSHR $dst, $src0, $src1",
 638   [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
 639 >;
 640
 641 class ASHR_Common <bits<32> inst> : R600_2OP <
 642   inst, "ASHR $dst, $src0, $src1",
 643   [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
 644 >;
 645
 646 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
 647   inst, "MULHI_INT $dst, $src0, $src1",
 648   [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
 649 >;
 650
 651 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
 652   inst, "MULHI $dst, $src0, $src1",
 653   [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
 654 >;
 655
 656 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
 657   inst, "MULLO_INT $dst, $src0, $src1",
 658   [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
 659 >;
 660
 661 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
 662   inst, "MULLO_UINT $dst, $src0, $src1",
 663   []
 664 >;
 665
 666 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 667   inst, "RECIP_CLAMPED",
 668   []
 669 >;
 670
 671 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
 672   inst, "RECIP_IEEE",
 673   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
 674 >;
 675
 676 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
 677   inst, "RECIP_INT $dst, $src",
 678   [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))]
 679 >;
 680
 681 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
 682   inst, "RECIPSQRT_CLAMPED",
 683   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 684 >;
 685
 686 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 687   inst, "RECIPSQRT_IEEE",
 688   []
 689 >;
 690
 691 class SIN_Common <bits<32> inst> : R600_1OP <
 692   inst, "SIN",
 693   [(set R600_Reg32:$dst, (int_AMDIL_sin R600_Reg32:$src))]>{
 694   let Trig = 1;
 695 }
 696
 697 class COS_Common <bits<32> inst> : R600_1OP <
 698   inst, "COS",
 699   [(set R600_Reg32:$dst, (int_AMDIL_cos R600_Reg32:$src))]> {
 700   let Trig = 1;
 701 }
 702
 703 /* Helper patterns for complex intrinsics */
 704 /* -------------------------------------- */
 705
 706 class DIV_Common <InstR600 recip_ieee> : Pat<
 707   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 708   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 709 >;
 710
 711 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 712   (int_AMDGPU_ssg R600_Reg32:$src),
 713   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 714 >;
 715
 716 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 717   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 718   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 719 >;
 720
 721 /* ---------------------- */
 722 /* R600 / R700 Only Instructions */
 723 /* ---------------------- */
 724
 725 let Predicates = [isR600] in {
 726
 727   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 728   def MULADD_r600 : MULADD_Common<0x10>;
 729   def CNDE_r600 : CNDE_Common<0x18>;
 730   def CNDGT_r600 : CNDGT_Common<0x19>;
 731   def CNDGE_r600 : CNDGE_Common<0x1A>;
 732   def DOT4_r600 : DOT4_Common<0x50>;
 733   def CUBE_r600 : CUBE_Common<0x52>;
 734   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 735   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 736   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 737   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 738   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 739   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 740   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 741   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 742   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 743   def SIN_r600 : SIN_Common<0x6E>;
 744   def COS_r600 : COS_Common<0x6F>;
 745   def ASHR_r600 : ASHR_Common<0x70>;
 746   def LSHR_r600 : LSHR_Common<0x71>;
 747   def LSHL_r600 : LSHL_Common<0x72>;
 748   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 749   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 750   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 751   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 752   def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
 753
 754   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 755   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 756   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 757   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 758
 759 }
 760
 761 /* ----------------- */
 762 /* R700+ Trig helper */
 763 /* ----------------- */
 764
 765 /*
 766 class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
 767   (trig_inst R600_Reg32:$src),
 768   (trig_inst (fmul R600_Reg32:$src, (PI))))
 769 >;
 770 */
 771
 772 /* ---------------------- */
 773 /* Evergreen Instructions */
 774 /* ---------------------- */
 775
 776
 777 let Predicates = [isEG] in {
 778
 779 def RAT_WRITE_CACHELESS_eg :
 780     EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
 781                                    R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
 782 {
 783   let RIM         = 0;
 784   /* XXX: Have a separate instruction for non-indexed writes. */
 785   let TYPE        = 1;
 786   let RW_REL      = 0;
 787   let ELEM_SIZE   = 0;
 788
 789   let ARRAY_SIZE  = 0;
 790   let COMP_MASK   = 1;
 791   let BURST_COUNT = 0;
 792   let VPM         = 0;
 793   let EOP         = 0;
 794   let MARK        = 0;
 795   let BARRIER     = 1;
 796 }
 797
 798 def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
 799                                 (ins R600_TReg32_X:$src, i32imm:$buffer_id),
 800                                 "VTX_READ_eg $dst, $src", []>
 801 {
 802 /*
 803   bits<7> DST_GPR;
 804   bits<7> SRC_GPR;
 805   bits<8> BUFFER_ID;
 806 */
 807   /* If any of these field below need to be calculated at compile time, and
 808    * a ins operand for them and move them to the list of operands above. */
 809
 810   /* XXX: This instruction is manual encoded, so none of these values are used.
 811    */
 812 /*
 813   bits<5> VC_INST          = 0; //VC_INST_FETCH
 814   bits<2> FETCH_TYPE       = 2;
 815   bits<1> FETCH_WHOLE_QUAD = 1;
 816   bits<1> SRC_REL          = 0;
 817   bits<2> SRC_SEL_X        = 0;
 818   bits<6> MEGA_FETCH_COUNT = 4;
 819 */
 820 /*
 821
 822   bits<1> DST_REL          = 0;
 823   bits<3> DST_SEL_X        = 0;
 824   bits<3> DST_SEL_Y        = 7; //Masked
 825   bits<3> DST_SEL_Z        = 7; //Masked
 826   bits<3> DST_SEL_W        = 7; //Masked
 827   bits<1> USE_CONST_FIELDS = 1; //Masked
 828   bits<6> DATA_FORMAT      = 0;
 829   bits<2> NUM_FORMAT_ALL   = 0;
 830   bits<1> FORMAT_COMP_ALL  = 0;
 831   bits<1> SRF_MODE_ALL     = 0;
 832 */
 833
 834 /*
 835   let Inst{4-0}   = VC_INST;
 836   let Inst{6-5}   = FETCH_TYPE;
 837   let Inst{7}     = FETCH_WHOLE_QUAD;
 838   let Inst{15-8}  = BUFFER_ID;
 839   let Inst{22-16} = SRC_GPR;
 840   let Inst{23}    = SRC_REL;
 841   let Inst{25-24} = SRC_SEL_X;
 842   let Inst{31-26} = MEGA_FETCH_COUNT;
 843 */
 844   /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you
 845    * from statically setting bits > 31.  This field will be set by
 846    * getMachineValueOp which can set bits > 31.
 847    */
 848 //  let Inst{32-38} = DST_GPR;
 849
 850   /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */
 851
 852 /*
 853   let Inst{39}    = DST_REL;
 854   let Inst{40}    = 0; //Reserved
 855   let Inst{43-41} = DST_SEL_X;
 856   let Inst{46-44} = DST_SEL_Y;
 857   let Inst{49-47} = DST_SEL_Z;
 858   let Inst{52-50} = DST_SEL_W;
 859   let Inst{53}    = USE_CONST_FIELDS;
 860   let Inst{59-54} = DATA_FORMAT;
 861   let Inst{61-60} = NUM_FORMAT_ALL;
 862   let Inst{62}    = FORMAT_COMP_ALL;
 863   let Inst{63}    = SRF_MODE_ALL;
 864 */
 865 }
 866
 867 /* XXX: Need to convert PTR to rat_id */
 868 /*
 869 def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
 870            (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
 871                                                   (f32 R600_Reg32:$value),
 872                                                    sel_x),
 873                                     (f32 ZERO), 0, R600_Reg32:$ptr)>;
 874 */
 875
 876 class VTX_Param_Read_Pattern <ValueType vt> : Pat <
 877     (vt (load_param ADDRParam:$mem)),
 878     (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>;
 879
 880 def : VTX_Param_Read_Pattern <f32>;
 881 def : VTX_Param_Read_Pattern <i32>;
 882
 883 } // End isEG Predicate
 884
 885 /* ------------------------------- */
 886 /* Evergreen / Cayman Instructions */
 887 /* ------------------------------- */
 888
 889 let Predicates = [isEGorCayman] in {
 890
 891 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
 892   (intr R600_Reg32:$src),
 893   (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
 894 >;
 895
 896   def MULADD_eg : MULADD_Common<0x14>;
 897   def ASHR_eg : ASHR_Common<0x15>;
 898   def LSHR_eg : LSHR_Common<0x16>;
 899   def LSHL_eg : LSHL_Common<0x17>;
 900   def CNDE_eg : CNDE_Common<0x19>;
 901   def CNDGT_eg : CNDGT_Common<0x1A>;
 902   def CNDGE_eg : CNDGE_Common<0x1B>;
 903   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 904   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 905   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 906   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 907   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 908   def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 909   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 910   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 911   def SIN_eg : SIN_Common<0x8D>;
 912   def COS_eg : COS_Common<0x8E>;
 913   def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 914   def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 915   def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 916   def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 917   def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 918   def DOT4_eg : DOT4_Common<0xBE>;
 919   def CUBE_eg : CUBE_Common<0xC0>;
 920
 921   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
 922   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
 923   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
 924   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 925
 926   def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
 927   def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
 928
 929   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
 930     let Pattern = [];
 931   }
 932
 933   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
 934
 935   def : Pat<(fp_to_sint R600_Reg32:$src),
 936     (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
 937
 938 }
 939
 940 let Predicates = [isCayman] in {
 941
 942   /* XXX: I'm not sure if this opcode is correct. */
 943   def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
 944
 945 } // End isCayman
 946
 947 /* Other Instructions */
 948
 949 let isCodeGenOnly = 1 in {
 950 /*
 951   def SWIZZLE : AMDGPUShaderInst <
 952     (outs GPRV4F32:$dst),
 953     (ins GPRV4F32:$src0, i32imm:$src1),
 954     "SWIZZLE $dst, $src0, $src1",
 955     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
 956   >;
 957 */
 958
 959   def LAST : AMDGPUShaderInst <
 960     (outs),
 961     (ins),
 962     "LAST",
 963     []
 964   >;
 965
 966   def GET_CHAN : AMDGPUShaderInst <
 967     (outs R600_Reg32:$dst),
 968     (ins R600_Reg128:$src0, i32imm:$src1),
 969     "GET_CHAN $dst, $src0, $src1",
 970     []
 971   >;
 972
 973   def MULLIT : AMDGPUShaderInst <
 974     (outs R600_Reg128:$dst),
 975     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
 976     "MULLIT $dst, $src0, $src1",
 977     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 978   >;
 979
 980 let usesCustomInserter = 1, isPseudo = 1 in {
 981
 982 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
 983   (outs R600_TReg32:$dst),
 984   (ins),
 985   asm,
 986   [(set R600_TReg32:$dst, (intr))]
 987 >;
 988
 989 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
 990 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
 991 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
 992
 993 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
 994 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
 995 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
 996
 997 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
 998 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
 999 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
1000
1001 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
1002                                      int_r600_read_global_size_x>;
1003 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
1004                                      int_r600_read_global_size_y>;
1005 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
1006                                      int_r600_read_global_size_z>;
1007
1008 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
1009                                     int_r600_read_local_size_x>;
1010 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
1011                                     int_r600_read_local_size_y>;
1012 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
1013                                     int_r600_read_local_size_z>;
1014
1015 def R600_LOAD_CONST : AMDGPUShaderInst <
1016   (outs R600_Reg32:$dst),
1017   (ins i32imm:$src0),
1018   "R600_LOAD_CONST $dst, $src0",
1019   [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1020 >;
1021
1022 def LOAD_INPUT : AMDGPUShaderInst <
1023   (outs R600_Reg32:$dst),
1024   (ins i32imm:$src),
1025   "LOAD_INPUT $dst, $src",
1026   [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1027 >;
1028
1029 def RESERVE_REG : AMDGPUShaderInst <
1030   (outs),
1031   (ins i32imm:$src),
1032   "RESERVE_REG $src",
1033   [(int_AMDGPU_reserve_reg imm:$src)]
1034 >;
1035
1036 def STORE_OUTPUT: AMDGPUShaderInst <
1037   (outs),
1038   (ins R600_Reg32:$src0, i32imm:$src1),
1039   "STORE_OUTPUT $src0, $src1",
1040   [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1041 >;
1042
1043 def TXD: AMDGPUShaderInst <
1044   (outs R600_Reg128:$dst),
1045   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1046   "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1047   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1048 >;
1049
1050 def TXD_SHADOW: AMDGPUShaderInst <
1051   (outs R600_Reg128:$dst),
1052   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1053   "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1054   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1055 >;
1056
1057 } // End usesCustomInserter = 1, isPseudo = 1
1058
1059 } // End isCodeGenOnly = 1
1060
1061
1062
1063 let isPseudo = 1 in {
1064
1065 def LOAD_VTX : AMDGPUShaderInst <
1066     (outs R600_Reg32:$dst),
1067     (ins MEMri:$mem),
1068     "LOAD_VTX",
1069     [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
1070 >;
1071
1072
1073 } //End isPseudo
1074
1075 //===----------------------------------------------------------------------===//
1076 // ISel Patterns
1077 //===----------------------------------------------------------------------===//
1078
1079 // SGT Reverse args
1080 def : Pat <
1081   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1082   (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1083 >;
1084
1085 // SGE Reverse args
1086 def : Pat <
1087   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1088   (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1089 >;
1090
1091 // SETGT_INT reverse args
1092 def : Pat <
1093   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1094   (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1095 >;
1096
1097 // SETGE_INT reverse args
1098 def : Pat <
1099   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1100   (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1101 >;
1102
1103 // SETGT_UINT reverse args
1104 def : Pat <
1105   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1106   (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1107 >;
1108
1109 // SETGE_UINT reverse args
1110 def : Pat <
1111   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1112   (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1113 >;
1114
1115 // The next two patterns are special cases for handling 'true if ordered' and
1116 // 'true if unordered' conditionals.  The assumption here is that the behavior of
1117 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1118 // described here:
1119 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1120 // We assume that  SETE returns false when one of the operands is NAN and
1121 // SNE returns true when on of the operands is NAN
1122
1123 //SETE - 'true if ordered'
1124 def : Pat <
1125   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1126   (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1127 >;
1128
1129 //SNE - 'true if unordered'
1130 def : Pat <
1131   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1132   (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1133 >;
1134
1135 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1136 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1137 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1138 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1139
1140 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1141 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1142 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1143 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1144
1145 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1146 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1147 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1148 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1149
1150 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1151 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1152 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1153 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1154
1155 } // End isR600toCayman Predicate