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[mesa.git] / src / gallium / drivers / radeon / R600Instructions.td
1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // R600 Tablegen instruction definitions
11 //
12 //===----------------------------------------------------------------------===//
13
14 include "R600Intrinsics.td"
15
16 class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern,
17 InstrItinClass itin>
18 : AMDGPUInst <outs, ins, asm, pattern> {
19
20 field bits<64> Inst;
21 bit Trig = 0;
22 bit Op3 = 0;
23 bit isVector = 0;
24 bits<2> FlagOperandIdx = 0;
25
26 bits<11> op_code = inst;
27 //let Inst = inst;
28 let Namespace = "AMDGPU";
29 let OutOperandList = outs;
30 let InOperandList = ins;
31 let AsmString = asm;
32 let Pattern = pattern;
33 let Itinerary = itin;
34
35 let TSFlags{4} = Trig;
36 let TSFlags{5} = Op3;
37
38 // Vector instructions are instructions that must fill all slots in an
39 // instruction group
40 let TSFlags{6} = isVector;
41 let TSFlags{8-7} = FlagOperandIdx;
42 }
43
44 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
45 AMDGPUInst <outs, ins, asm, pattern>
46 {
47 field bits<64> Inst;
48
49 let Namespace = "AMDGPU";
50 }
51
52 def MEMxi : Operand<iPTR> {
53 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
54 }
55
56 def MEMrr : Operand<iPTR> {
57 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
58 }
59
60 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
61 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
62 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
63
64 class R600_ALU {
65
66 bits<7> DST_GPR = 0;
67 bits<9> SRC0_SEL = 0;
68 bits<1> SRC0_NEG = 0;
69 bits<9> SRC1_SEL = 0;
70 bits<1> SRC1_NEG = 0;
71 bits<1> CLAMP = 0;
72
73 }
74
75 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
76 (ops PRED_SEL_OFF)>;
77
78
79 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
80 InstrItinClass itin = AnyALU> :
81 InstR600 <inst,
82 (outs R600_Reg32:$dst),
83 (ins R600_Reg32:$src, R600_Pred:$p, variable_ops),
84 !strconcat(opName, " $dst, $src ($p)"),
85 pattern,
86 itin>{
87 bits<7> dst;
88 bits<9> src;
89 let Inst{8-0} = src;
90 let Inst{49-39} = inst;
91 let Inst{59-53} = dst;
92 }
93
94 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
95 InstrItinClass itin = AnyALU> :
96 InstR600 <inst,
97 (outs R600_Reg32:$dst),
98 (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops),
99 !strconcat(opName, " $dst, $src0, $src1"),
100 pattern,
101 itin>{
102 bits<7> dst;
103 bits<9> src0;
104 bits<9> src1;
105 let Inst{8-0} = src0;
106 let Inst{21-13} = src1;
107 let Inst{49-39} = inst;
108 let Inst{59-53} = dst;
109 }
110
111 class R600_3OP <bits<11> inst, string opName, list<dag> pattern,
112 InstrItinClass itin = AnyALU> :
113 InstR600 <inst,
114 (outs R600_Reg32:$dst),
115 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops),
116 !strconcat(opName, " $dst, $src0, $src1, $src2"),
117 pattern,
118 itin>{
119 bits<7> dst;
120 bits<9> src0;
121 bits<9> src1;
122 bits<9> src2;
123 let Inst{8-0} = src0;
124 let Inst{21-13} = src1;
125 let Inst{40-32} = src2;
126 let Inst{49-45} = inst{4-0};
127 let Inst{59-53} = dst;
128 let Op3 = 1;
129 }
130
131
132
133 def PRED_X : InstR600 <0, (outs R600_Predicate_Bit:$dst),
134 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
135 "PRED $dst, $src0, $src1",
136 [], NullALU>
137 {
138 bits<7> dst;
139 bits<9> src0;
140 bits<11> src1;
141 let Inst{8-0} = src0;
142 let Inst{49-39} = src1;
143 let Inst{59-53} = dst;
144 let FlagOperandIdx = 3;
145 }
146
147 let isTerminator = 1, isBranch = 1, isPseudo = 1 in {
148 def JUMP : InstR600 <0x10,
149 (outs),
150 (ins brtarget:$target, R600_Pred:$p),
151 "JUMP $target ($p)",
152 [], AnyALU
153 >;
154 }
155
156 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
157 InstrItinClass itin = VecALU> :
158 InstR600 <inst,
159 (outs R600_Reg32:$dst),
160 ins,
161 asm,
162 pattern,
163 itin>{
164 bits<7> dst;
165 let Inst{49-39} = inst;
166 let Inst{59-53} = dst;
167 }
168
169 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
170 InstrItinClass itin = AnyALU> :
171 InstR600 <inst,
172 (outs R600_Reg128:$dst),
173 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
174 !strconcat(opName, "$dst, $src0, $src1, $src2"),
175 pattern,
176 itin>{
177 let Inst {10-0} = inst;
178 }
179
180 def TEX_SHADOW : PatLeaf<
181 (imm),
182 [{uint32_t TType = (uint32_t)N->getZExtValue();
183 return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
184 }]
185 >;
186
187 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
188 dag ins, string asm, list<dag> pattern> :
189 InstR600ISA <outs, ins, asm, pattern>
190 {
191 bits<7> RW_GPR;
192 bits<7> INDEX_GPR;
193
194 bits<2> RIM;
195 bits<2> TYPE;
196 bits<1> RW_REL;
197 bits<2> ELEM_SIZE;
198
199 bits<12> ARRAY_SIZE;
200 bits<4> COMP_MASK;
201 bits<4> BURST_COUNT;
202 bits<1> VPM;
203 bits<1> eop;
204 bits<1> MARK;
205 bits<1> BARRIER;
206
207 // CF_ALLOC_EXPORT_WORD0_RAT
208 let Inst{3-0} = rat_id;
209 let Inst{9-4} = rat_inst;
210 let Inst{10} = 0; // Reserved
211 let Inst{12-11} = RIM;
212 let Inst{14-13} = TYPE;
213 let Inst{21-15} = RW_GPR;
214 let Inst{22} = RW_REL;
215 let Inst{29-23} = INDEX_GPR;
216 let Inst{31-30} = ELEM_SIZE;
217
218 // CF_ALLOC_EXPORT_WORD1_BUF
219 let Inst{43-32} = ARRAY_SIZE;
220 let Inst{47-44} = COMP_MASK;
221 let Inst{51-48} = BURST_COUNT;
222 let Inst{52} = VPM;
223 let Inst{53} = eop;
224 let Inst{61-54} = cf_inst;
225 let Inst{62} = MARK;
226 let Inst{63} = BARRIER;
227 }
228
229 def load_param : PatFrag<(ops node:$ptr),
230 (load node:$ptr),
231 [{
232 const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
233 if (Src) {
234 PointerType * PT = dyn_cast<PointerType>(Src->getType());
235 return PT && PT->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS;
236 }
237 return false;
238 }]>;
239
240 def isR600 : Predicate<"Subtarget.device()"
241 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
242 def isR700 : Predicate<"Subtarget.device()"
243 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
244 "Subtarget.device()->getDeviceFlag()"
245 ">= OCL_DEVICE_RV710">;
246 def isEG : Predicate<
247 "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
248 "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
249 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
250
251 def isCayman : Predicate<"Subtarget.device()"
252 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
253 def isEGorCayman : Predicate<"Subtarget.device()"
254 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
255 "|| Subtarget.device()->getGeneration() =="
256 "AMDGPUDeviceInfo::HD6XXX">;
257
258 def isR600toCayman : Predicate<
259 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
260
261
262 let Predicates = [isR600toCayman] in {
263
264 //===----------------------------------------------------------------------===//
265 // Common Instructions R600, R700, Evergreen, Cayman
266 //===----------------------------------------------------------------------===//
267
268 def ADD : R600_2OP <
269 0x0, "ADD",
270 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
271 >;
272
273 // Non-IEEE MUL: 0 * anything = 0
274 def MUL : R600_2OP <
275 0x1, "MUL NON-IEEE",
276 [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
277 >;
278
279 def MUL_IEEE : R600_2OP <
280 0x2, "MUL_IEEE",
281 [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
282 >;
283
284 def MAX : R600_2OP <
285 0x3, "MAX",
286 [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
287 >;
288
289 def MIN : R600_2OP <
290 0x4, "MIN",
291 [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
292 >;
293
294 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
295 // so some of the instruction names don't match the asm string.
296 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
297
298 def SETE : R600_2OP <
299 0x08, "SETE",
300 [(set R600_Reg32:$dst,
301 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
302 COND_EQ))]
303 >;
304
305 def SGT : R600_2OP <
306 0x09, "SETGT",
307 [(set R600_Reg32:$dst,
308 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
309 COND_GT))]
310 >;
311
312 def SGE : R600_2OP <
313 0xA, "SETGE",
314 [(set R600_Reg32:$dst,
315 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
316 COND_GE))]
317 >;
318
319 def SNE : R600_2OP <
320 0xB, "SETNE",
321 [(set R600_Reg32:$dst,
322 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
323 COND_NE))]
324 >;
325
326 def FRACT : R600_1OP <
327 0x10, "FRACT",
328 [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
329 >;
330
331 def TRUNC : R600_1OP <
332 0x11, "TRUNC",
333 [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
334 >;
335
336 def CEIL : R600_1OP <
337 0x12, "CEIL",
338 [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
339 >;
340
341 def RNDNE : R600_1OP <
342 0x13, "RNDNE",
343 [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
344 >;
345
346 def FLOOR : R600_1OP <
347 0x14, "FLOOR",
348 [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
349 >;
350
351 def MOV : InstR600 <0x19, (outs R600_Reg32:$dst),
352 (ins R600_Reg32:$src0, i32imm:$flags,
353 R600_Pred:$p),
354 "MOV $dst, $src0", [], AnyALU> {
355 let FlagOperandIdx = 2;
356 bits<7> dst;
357 bits<9> src0;
358 let Inst{8-0} = src0;
359 let Inst{49-39} = op_code;
360 let Inst{59-53} = dst;
361 }
362
363 class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
364 (outs R600_Reg32:$dst),
365 (ins R600_Reg32:$alu_literal, R600_Pred:$p, immType:$imm),
366 "MOV_IMM $dst, $imm",
367 [], AnyALU
368 >{
369 bits<7> dst;
370 bits<9> alu_literal;
371 bits<9> p;
372 let Inst{8-0} = alu_literal;
373 let Inst{21-13} = p;
374 let Inst{49-39} = op_code;
375 let Inst{59-53} = dst;
376 }
377
378 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
379 def : Pat <
380 (imm:$val),
381 (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
382 >;
383
384 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
385 def : Pat <
386 (fpimm:$val),
387 (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
388 >;
389
390 def KILLGT : InstR600 <0x2D,
391 (outs R600_Reg32:$dst),
392 (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags, R600_Pred:$p,
393 variable_ops),
394 "KILLGT $dst, $src0, $src1, $flags ($p)",
395 [],
396 NullALU>{
397 let FlagOperandIdx = 3;
398 bits<7> dst;
399 bits<9> src0;
400 bits<9> src1;
401 let Inst{8-0} = src0;
402 let Inst{21-13} = src1;
403 let Inst{49-39} = op_code;
404 let Inst{59-53} = dst;
405 }
406
407 def AND_INT : R600_2OP <
408 0x30, "AND_INT",
409 [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
410 >;
411
412 def OR_INT : R600_2OP <
413 0x31, "OR_INT",
414 [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
415 >;
416
417 def XOR_INT : R600_2OP <
418 0x32, "XOR_INT",
419 [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
420 >;
421
422 def NOT_INT : R600_1OP <
423 0x33, "NOT_INT",
424 [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
425 >;
426
427 def ADD_INT : R600_2OP <
428 0x34, "ADD_INT",
429 [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
430 >;
431
432 def SUB_INT : R600_2OP <
433 0x35, "SUB_INT",
434 [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
435 >;
436
437 def MAX_INT : R600_2OP <
438 0x36, "MAX_INT",
439 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
440
441 def MIN_INT : R600_2OP <
442 0x37, "MIN_INT",
443 [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
444
445 def MAX_UINT : R600_2OP <
446 0x38, "MAX_UINT",
447 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
448 >;
449
450 def MIN_UINT : R600_2OP <
451 0x39, "MIN_UINT",
452 [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
453 >;
454
455 def SETE_INT : R600_2OP <
456 0x3A, "SETE_INT",
457 [(set (i32 R600_Reg32:$dst),
458 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
459 >;
460
461 def SETGT_INT : R600_2OP <
462 0x3B, "SGT_INT",
463 [(set (i32 R600_Reg32:$dst),
464 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
465 >;
466
467 def SETGE_INT : R600_2OP <
468 0x3C, "SETGE_INT",
469 [(set (i32 R600_Reg32:$dst),
470 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
471 >;
472
473 def SETNE_INT : R600_2OP <
474 0x3D, "SETNE_INT",
475 [(set (i32 R600_Reg32:$dst),
476 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
477 >;
478
479 def SETGT_UINT : R600_2OP <
480 0x3E, "SETGT_UINT",
481 [(set (i32 R600_Reg32:$dst),
482 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
483 >;
484
485 def SETGE_UINT : R600_2OP <
486 0x3F, "SETGE_UINT",
487 [(set (i32 R600_Reg32:$dst),
488 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
489 >;
490
491 def CNDE_INT : R600_3OP <
492 0x1C, "CNDE_INT",
493 [(set (i32 R600_Reg32:$dst),
494 (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
495 >;
496
497 //===----------------------------------------------------------------------===//
498 // Texture instructions
499 //===----------------------------------------------------------------------===//
500
501 def TEX_LD : R600_TEX <
502 0x03, "TEX_LD",
503 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
504 > {
505 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
506 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
507 }
508
509 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
510 0x04, "TEX_GET_TEXTURE_RESINFO",
511 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
512 >;
513
514 def TEX_GET_GRADIENTS_H : R600_TEX <
515 0x07, "TEX_GET_GRADIENTS_H",
516 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
517 >;
518
519 def TEX_GET_GRADIENTS_V : R600_TEX <
520 0x08, "TEX_GET_GRADIENTS_V",
521 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
522 >;
523
524 def TEX_SET_GRADIENTS_H : R600_TEX <
525 0x0B, "TEX_SET_GRADIENTS_H",
526 []
527 >;
528
529 def TEX_SET_GRADIENTS_V : R600_TEX <
530 0x0C, "TEX_SET_GRADIENTS_V",
531 []
532 >;
533
534 def TEX_SAMPLE : R600_TEX <
535 0x10, "TEX_SAMPLE",
536 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
537 >;
538
539 def TEX_SAMPLE_C : R600_TEX <
540 0x18, "TEX_SAMPLE_C",
541 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
542 >;
543
544 def TEX_SAMPLE_L : R600_TEX <
545 0x11, "TEX_SAMPLE_L",
546 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
547 >;
548
549 def TEX_SAMPLE_C_L : R600_TEX <
550 0x19, "TEX_SAMPLE_C_L",
551 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
552 >;
553
554 def TEX_SAMPLE_LB : R600_TEX <
555 0x12, "TEX_SAMPLE_LB",
556 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
557 >;
558
559 def TEX_SAMPLE_C_LB : R600_TEX <
560 0x1A, "TEX_SAMPLE_C_LB",
561 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
562 >;
563
564 def TEX_SAMPLE_G : R600_TEX <
565 0x14, "TEX_SAMPLE_G",
566 []
567 >;
568
569 def TEX_SAMPLE_C_G : R600_TEX <
570 0x1C, "TEX_SAMPLE_C_G",
571 []
572 >;
573
574 //===----------------------------------------------------------------------===//
575 // Helper classes for common instructions
576 //===----------------------------------------------------------------------===//
577
578 class MUL_LIT_Common <bits<11> inst> : R600_3OP <
579 inst, "MUL_LIT",
580 []
581 >;
582
583 class MULADD_Common <bits<11> inst> : R600_3OP <
584 inst, "MULADD",
585 [(set (f32 R600_Reg32:$dst),
586 (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
587 >;
588
589 class CNDE_Common <bits<11> inst> : R600_3OP <
590 inst, "CNDE",
591 [(set (f32 R600_Reg32:$dst),
592 (select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)))]
593 >;
594
595 class CNDGT_Common <bits<11> inst> : R600_3OP <
596 inst, "CNDGT",
597 []
598 >;
599
600 class CNDGE_Common <bits<11> inst> : R600_3OP <
601 inst, "CNDGE",
602 [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
603 >;
604
605 class DOT4_Common <bits<11> inst> : R600_REDUCTION <
606 inst,
607 (ins R600_Reg128:$src0, R600_Reg128:$src1, i32imm:$flags),
608 "DOT4 $dst $src0, $src1",
609 []
610 > {
611 bits<9> src0;
612 bits<9> src1;
613 let Inst{8-0} = src0;
614 let Inst{21-13} = src1;
615 let FlagOperandIdx = 3;
616 }
617
618 class DOT4_Pat <Instruction dot4> : Pat <
619 (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1),
620 (dot4 R600_Reg128:$src0, R600_Reg128:$src1, 0)
621 >;
622
623 multiclass CUBE_Common <bits<11> inst> {
624
625 def _pseudo : InstR600 <
626 inst,
627 (outs R600_Reg128:$dst),
628 (ins R600_Reg128:$src),
629 "CUBE $dst $src",
630 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
631 VecALU
632 >;
633
634 def _real : InstR600 <
635 inst,
636 (outs R600_Reg32:$dst),
637 (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
638 "CUBE $dst, $src0, $src1",
639 [], VecALU
640 >{
641 let FlagOperandIdx = 3;
642 bits<7> dst;
643 bits<9> src0;
644 bits<9> src1;
645 let Inst{8-0} = src0;
646 let Inst{21-13} = src1;
647 let Inst{49-39} = inst;
648 let Inst{59-53} = dst;
649 }
650 }
651
652 class EXP_IEEE_Common <bits<11> inst> : R600_1OP <
653 inst, "EXP_IEEE",
654 [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
655 >;
656
657 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP <
658 inst, "FLT_TO_INT",
659 [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))]
660 >;
661
662 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP <
663 inst, "INT_TO_FLT",
664 [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
665 >;
666
667 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP <
668 inst, "FLT_TO_UINT",
669 [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))]
670 >;
671
672 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP <
673 inst, "UINT_TO_FLT",
674 [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))]
675 >;
676
677 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
678 inst, "LOG_CLAMPED",
679 []
680 >;
681
682 class LOG_IEEE_Common <bits<11> inst> : R600_1OP <
683 inst, "LOG_IEEE",
684 [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
685 >;
686
687 class LSHL_Common <bits<11> inst> : R600_2OP <
688 inst, "LSHL $dst, $src0, $src1",
689 [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
690 >;
691
692 class LSHR_Common <bits<11> inst> : R600_2OP <
693 inst, "LSHR $dst, $src0, $src1",
694 [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
695 >;
696
697 class ASHR_Common <bits<11> inst> : R600_2OP <
698 inst, "ASHR $dst, $src0, $src1",
699 [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
700 >;
701
702 class MULHI_INT_Common <bits<11> inst> : R600_2OP <
703 inst, "MULHI_INT $dst, $src0, $src1",
704 [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
705 >;
706
707 class MULHI_UINT_Common <bits<11> inst> : R600_2OP <
708 inst, "MULHI $dst, $src0, $src1",
709 [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
710 >;
711
712 class MULLO_INT_Common <bits<11> inst> : R600_2OP <
713 inst, "MULLO_INT $dst, $src0, $src1",
714 [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
715 >;
716
717 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <
718 inst, "MULLO_UINT $dst, $src0, $src1",
719 []
720 >;
721
722 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
723 inst, "RECIP_CLAMPED",
724 []
725 >;
726
727 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
728 inst, "RECIP_IEEE",
729 [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
730 >;
731
732 class RECIP_UINT_Common <bits<11> inst> : R600_1OP <
733 inst, "RECIP_INT $dst, $src",
734 [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))]
735 >;
736
737 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP <
738 inst, "RECIPSQRT_CLAMPED",
739 [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
740 >;
741
742 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
743 inst, "RECIPSQRT_IEEE",
744 []
745 >;
746
747 class SIN_Common <bits<11> inst> : R600_1OP <
748 inst, "SIN", []>{
749 let Trig = 1;
750 }
751
752 class COS_Common <bits<11> inst> : R600_1OP <
753 inst, "COS", []> {
754 let Trig = 1;
755 }
756
757 //===----------------------------------------------------------------------===//
758 // Helper patterns for complex intrinsics
759 //===----------------------------------------------------------------------===//
760
761 multiclass DIV_Common <InstR600 recip_ieee> {
762 def : Pat<
763 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
764 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
765 >;
766
767 def : Pat<
768 (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
769 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
770 >;
771 }
772
773 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
774 (int_AMDGPU_ssg R600_Reg32:$src),
775 (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
776 >;
777
778 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
779 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
780 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
781 >;
782
783 //===----------------------------------------------------------------------===//
784 // R600 / R700 Instructions
785 //===----------------------------------------------------------------------===//
786
787 let Predicates = [isR600] in {
788
789 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
790 def MULADD_r600 : MULADD_Common<0x10>;
791 def CNDE_r600 : CNDE_Common<0x18>;
792 def CNDGT_r600 : CNDGT_Common<0x19>;
793 def CNDGE_r600 : CNDGE_Common<0x1A>;
794 def DOT4_r600 : DOT4_Common<0x50>;
795 def : DOT4_Pat <DOT4_r600>;
796 defm CUBE_r600 : CUBE_Common<0x52>;
797 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
798 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
799 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
800 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
801 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
802 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
803 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
804 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
805 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
806 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
807 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
808 def SIN_r600 : SIN_Common<0x6E>;
809 def COS_r600 : COS_Common<0x6F>;
810 def ASHR_r600 : ASHR_Common<0x70>;
811 def LSHR_r600 : LSHR_Common<0x71>;
812 def LSHL_r600 : LSHL_Common<0x72>;
813 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
814 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
815 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
816 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
817 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
818
819 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
820 def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
821 def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
822 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
823
824 }
825
826 // Helper pattern for normalizing inputs to triginomic instructions for R700+
827 // cards.
828 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
829 (intr R600_Reg32:$src),
830 (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
831 >;
832
833 //===----------------------------------------------------------------------===//
834 // R700 Only instructions
835 //===----------------------------------------------------------------------===//
836
837 let Predicates = [isR700] in {
838 def SIN_r700 : SIN_Common<0x6E>;
839 def COS_r700 : COS_Common<0x6F>;
840
841 // R700 normalizes inputs to SIN/COS the same as EG
842 def : TRIG_eg <SIN_r700, int_AMDGPU_sin>;
843 def : TRIG_eg <COS_r700, int_AMDGPU_cos>;
844 }
845
846 //===----------------------------------------------------------------------===//
847 // Evergreen Only instructions
848 //===----------------------------------------------------------------------===//
849
850 let Predicates = [isEG] in {
851
852 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
853
854 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
855 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
856 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
857 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
858 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
859
860 } // End Predicates = [isEG]
861
862 //===----------------------------------------------------------------------===//
863 // Evergreen / Cayman Instructions
864 //===----------------------------------------------------------------------===//
865
866 let Predicates = [isEGorCayman] in {
867
868 // BFE_UINT - bit_extract, an optimization for mask and shift
869 // Src0 = Input
870 // Src1 = Offset
871 // Src2 = Width
872 //
873 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
874 //
875 // Example Usage:
876 // (Offset, Width)
877 //
878 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
879 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
880 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
881 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
882 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
883 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
884 R600_Reg32:$src1,
885 R600_Reg32:$src2))],
886 VecALU
887 >;
888
889 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
890 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
891 R600_Reg32:$src2))],
892 VecALU
893 >;
894
895 def MULADD_eg : MULADD_Common<0x14>;
896 def ASHR_eg : ASHR_Common<0x15>;
897 def LSHR_eg : LSHR_Common<0x16>;
898 def LSHL_eg : LSHL_Common<0x17>;
899 def CNDE_eg : CNDE_Common<0x19>;
900 def CNDGT_eg : CNDGT_Common<0x1A>;
901 def CNDGE_eg : CNDGE_Common<0x1B>;
902 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
903 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
904 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
905 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
906 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
907 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
908 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
909 def SIN_eg : SIN_Common<0x8D>;
910 def COS_eg : COS_Common<0x8E>;
911 def DOT4_eg : DOT4_Common<0xBE>;
912 def : DOT4_Pat <DOT4_eg>;
913 defm CUBE_eg : CUBE_Common<0xC0>;
914
915 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
916 def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
917 def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
918 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
919
920 def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
921 def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
922
923 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
924 let Pattern = [];
925 }
926
927 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
928
929 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
930 let Pattern = [];
931 }
932
933 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
934
935 def : Pat<(fp_to_sint R600_Reg32:$src),
936 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
937
938 def : Pat<(fp_to_uint R600_Reg32:$src),
939 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
940
941 //===----------------------------------------------------------------------===//
942 // Memory read/write instructions
943 //===----------------------------------------------------------------------===//
944
945 let usesCustomInserter = 1 in {
946
947 def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
948 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
949 "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr, $eop",
950 []>
951 {
952 let RIM = 0;
953 // XXX: Have a separate instruction for non-indexed writes.
954 let TYPE = 1;
955 let RW_REL = 0;
956 let ELEM_SIZE = 0;
957
958 let ARRAY_SIZE = 0;
959 let COMP_MASK = 1;
960 let BURST_COUNT = 0;
961 let VPM = 0;
962 let MARK = 0;
963 let BARRIER = 1;
964 }
965
966 } // End usesCustomInserter = 1
967
968 // i32 global_store
969 def : Pat <
970 (global_store (i32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
971 (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
972 >;
973
974 // Floating point global_store
975 def : Pat <
976 (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
977 (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
978 >;
979
980 class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>
981 : InstR600ISA <outs, (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr", pattern> {
982
983 // Operands
984 bits<7> DST_GPR;
985 bits<7> SRC_GPR;
986
987 // Static fields
988 bits<5> VC_INST = 0;
989 bits<2> FETCH_TYPE = 2;
990 bits<1> FETCH_WHOLE_QUAD = 0;
991 bits<8> BUFFER_ID = buffer_id;
992 bits<1> SRC_REL = 0;
993 // XXX: We can infer this field based on the SRC_GPR. This would allow us
994 // to store vertex addresses in any channel, not just X.
995 bits<2> SRC_SEL_X = 0;
996 bits<6> MEGA_FETCH_COUNT;
997 bits<1> DST_REL = 0;
998 bits<3> DST_SEL_X;
999 bits<3> DST_SEL_Y;
1000 bits<3> DST_SEL_Z;
1001 bits<3> DST_SEL_W;
1002 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1003 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1004 // however, based on my testing if USE_CONST_FIELDS is set, then all
1005 // these fields need to be set to 0.
1006 bits<1> USE_CONST_FIELDS = 0;
1007 bits<6> DATA_FORMAT;
1008 bits<2> NUM_FORMAT_ALL = 1;
1009 bits<1> FORMAT_COMP_ALL = 0;
1010 bits<1> SRF_MODE_ALL = 0;
1011
1012 // LLVM can only encode 64-bit instructions, so these fields are manually
1013 // encoded in R600CodeEmitter
1014 //
1015 // bits<16> OFFSET;
1016 // bits<2> ENDIAN_SWAP = 0;
1017 // bits<1> CONST_BUF_NO_STRIDE = 0;
1018 // bits<1> MEGA_FETCH = 0;
1019 // bits<1> ALT_CONST = 0;
1020 // bits<2> BUFFER_INDEX_MODE = 0;
1021
1022 // VTX_WORD0
1023 let Inst{4-0} = VC_INST;
1024 let Inst{6-5} = FETCH_TYPE;
1025 let Inst{7} = FETCH_WHOLE_QUAD;
1026 let Inst{15-8} = BUFFER_ID;
1027 let Inst{22-16} = SRC_GPR;
1028 let Inst{23} = SRC_REL;
1029 let Inst{25-24} = SRC_SEL_X;
1030 let Inst{31-26} = MEGA_FETCH_COUNT;
1031
1032 // VTX_WORD1_GPR
1033 let Inst{38-32} = DST_GPR;
1034 let Inst{39} = DST_REL;
1035 let Inst{40} = 0; // Reserved
1036 let Inst{43-41} = DST_SEL_X;
1037 let Inst{46-44} = DST_SEL_Y;
1038 let Inst{49-47} = DST_SEL_Z;
1039 let Inst{52-50} = DST_SEL_W;
1040 let Inst{53} = USE_CONST_FIELDS;
1041 let Inst{59-54} = DATA_FORMAT;
1042 let Inst{61-60} = NUM_FORMAT_ALL;
1043 let Inst{62} = FORMAT_COMP_ALL;
1044 let Inst{63} = SRF_MODE_ALL;
1045
1046 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1047 // is done in R600CodeEmitter
1048 //
1049 // Inst{79-64} = OFFSET;
1050 // Inst{81-80} = ENDIAN_SWAP;
1051 // Inst{82} = CONST_BUF_NO_STRIDE;
1052 // Inst{83} = MEGA_FETCH;
1053 // Inst{84} = ALT_CONST;
1054 // Inst{86-85} = BUFFER_INDEX_MODE;
1055 // Inst{95-86} = 0; Reserved
1056
1057 // VTX_WORD3 (Padding)
1058 //
1059 // Inst{127-96} = 0;
1060 }
1061
1062 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1063 : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
1064
1065 let MEGA_FETCH_COUNT = 1;
1066 let DST_SEL_X = 0;
1067 let DST_SEL_Y = 7; // Masked
1068 let DST_SEL_Z = 7; // Masked
1069 let DST_SEL_W = 7; // Masked
1070 let DATA_FORMAT = 1; // FMT_8
1071 }
1072
1073 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1074 : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
1075
1076 let MEGA_FETCH_COUNT = 4;
1077 let DST_SEL_X = 0;
1078 let DST_SEL_Y = 7; // Masked
1079 let DST_SEL_Z = 7; // Masked
1080 let DST_SEL_W = 7; // Masked
1081 let DATA_FORMAT = 0xD; // COLOR_32
1082
1083 // This is not really necessary, but there were some GPU hangs that appeared
1084 // to be caused by ALU instructions in the next instruction group that wrote
1085 // to the $ptr registers of the VTX_READ.
1086 // e.g.
1087 // %T3_X<def> = VTX_READ_PARAM_i32_eg %T2_X<kill>, 24
1088 // %T2_X<def> = MOV %ZERO
1089 //Adding this constraint prevents this from happening.
1090 let Constraints = "$ptr.ptr = $dst";
1091 }
1092
1093 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1094 : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> {
1095
1096 let MEGA_FETCH_COUNT = 16;
1097 let DST_SEL_X = 0;
1098 let DST_SEL_Y = 1;
1099 let DST_SEL_Z = 2;
1100 let DST_SEL_W = 3;
1101 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1102
1103 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1104 // that holds its buffer address to avoid potential hangs. We can't use
1105 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1106 // registers are different sizes.
1107 }
1108
1109 //===----------------------------------------------------------------------===//
1110 // VTX Read from parameter memory space
1111 //===----------------------------------------------------------------------===//
1112
1113 class VTX_READ_PARAM_32_eg <ValueType vt> : VTX_READ_32_eg <0,
1114 [(set (vt R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1115 >;
1116
1117 def VTX_READ_PARAM_i32_eg : VTX_READ_PARAM_32_eg<i32>;
1118 def VTX_READ_PARAM_f32_eg : VTX_READ_PARAM_32_eg<f32>;
1119
1120
1121 //===----------------------------------------------------------------------===//
1122 // VTX Read from global memory space
1123 //===----------------------------------------------------------------------===//
1124
1125 // 8-bit reads
1126 def VTX_READ_GLOBAL_i8_eg : VTX_READ_8_eg <1,
1127 [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
1128 >;
1129
1130 // 32-bit reads
1131
1132 class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1,
1133 [(set (vt R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1134 >;
1135
1136 def VTX_READ_GLOBAL_i32_eg : VTX_READ_GLOBAL_eg<i32>;
1137 def VTX_READ_GLOBAL_f32_eg : VTX_READ_GLOBAL_eg<f32>;
1138
1139 // 128-bit reads
1140
1141 class VTX_READ_GLOBAL_128_eg <ValueType vt> : VTX_READ_128_eg <1,
1142 [(set (vt R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1143 >;
1144
1145 def VTX_READ_GLOBAL_v4i32_eg : VTX_READ_GLOBAL_128_eg<v4i32>;
1146 def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>;
1147
1148 }
1149
1150 let Predicates = [isCayman] in {
1151
1152 let isVector = 1 in {
1153
1154 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1155
1156 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1157 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1158 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1159 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1160
1161 } // End isVector = 1
1162
1163 // RECIP_UINT emulation for Cayman
1164 def : Pat <
1165 (AMDGPUurecip R600_Reg32:$src0),
1166 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1167 (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000)))
1168 >;
1169
1170 } // End isCayman
1171
1172 let isCodeGenOnly = 1 in {
1173
1174 def MULLIT : AMDGPUShaderInst <
1175 (outs R600_Reg128:$dst),
1176 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
1177 "MULLIT $dst, $src0, $src1",
1178 [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
1179 >;
1180
1181 let usesCustomInserter = 1, isPseudo = 1 in {
1182
1183 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
1184 (outs R600_TReg32:$dst),
1185 (ins),
1186 asm,
1187 [(set R600_TReg32:$dst, (intr))]
1188 >;
1189
1190 def R600_LOAD_CONST : AMDGPUShaderInst <
1191 (outs R600_Reg32:$dst),
1192 (ins i32imm:$src0),
1193 "R600_LOAD_CONST $dst, $src0",
1194 [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1195 >;
1196
1197 def RESERVE_REG : AMDGPUShaderInst <
1198 (outs),
1199 (ins i32imm:$src),
1200 "RESERVE_REG $src",
1201 [(int_AMDGPU_reserve_reg imm:$src)]
1202 >;
1203
1204 def TXD: AMDGPUShaderInst <
1205 (outs R600_Reg128:$dst),
1206 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1207 "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1208 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1209 >;
1210
1211 def TXD_SHADOW: AMDGPUShaderInst <
1212 (outs R600_Reg128:$dst),
1213 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1214 "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1215 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1216 >;
1217
1218 } // End usesCustomInserter = 1, isPseudo = 1
1219
1220 } // End isCodeGenOnly = 1
1221
1222 def CLAMP_R600 : CLAMP <R600_Reg32>;
1223 def FABS_R600 : FABS<R600_Reg32>;
1224 def FNEG_R600 : FNEG<R600_Reg32>;
1225
1226 let usesCustomInserter = 1 in {
1227
1228 def MASK_WRITE : AMDGPUShaderInst <
1229 (outs),
1230 (ins R600_Reg32:$src),
1231 "MASK_WRITE $src",
1232 []
1233 >;
1234
1235 } // End usesCustomInserter = 1
1236
1237 //===---------------------------------------------------------------------===//
1238 // Return instruction
1239 //===---------------------------------------------------------------------===//
1240 let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
1241 def RETURN : ILFormat<(outs), (ins variable_ops),
1242 "RETURN", [(IL_retflag)]>;
1243 }
1244
1245 //===----------------------------------------------------------------------===//
1246 // ISel Patterns
1247 //===----------------------------------------------------------------------===//
1248
1249 // KIL Patterns
1250 def KILP : Pat <
1251 (int_AMDGPU_kilp),
1252 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO), 0))
1253 >;
1254
1255 def KIL : Pat <
1256 (int_AMDGPU_kill R600_Reg32:$src0),
1257 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0), 0))
1258 >;
1259
1260 // SGT Reverse args
1261 def : Pat <
1262 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1263 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1264 >;
1265
1266 // SGE Reverse args
1267 def : Pat <
1268 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1269 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1270 >;
1271
1272 // SETGT_INT reverse args
1273 def : Pat <
1274 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1275 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1276 >;
1277
1278 // SETGE_INT reverse args
1279 def : Pat <
1280 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1281 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1282 >;
1283
1284 // SETGT_UINT reverse args
1285 def : Pat <
1286 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1287 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1288 >;
1289
1290 // SETGE_UINT reverse args
1291 def : Pat <
1292 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1293 (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1294 >;
1295
1296 // The next two patterns are special cases for handling 'true if ordered' and
1297 // 'true if unordered' conditionals. The assumption here is that the behavior of
1298 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1299 // described here:
1300 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1301 // We assume that SETE returns false when one of the operands is NAN and
1302 // SNE returns true when on of the operands is NAN
1303
1304 //SETE - 'true if ordered'
1305 def : Pat <
1306 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1307 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1308 >;
1309
1310 //SNE - 'true if unordered'
1311 def : Pat <
1312 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1313 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1314 >;
1315
1316 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1317 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1318 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1319 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1320
1321 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sel_x>;
1322 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sel_y>;
1323 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sel_z>;
1324 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sel_w>;
1325
1326 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1327 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1328 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1329 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1330
1331 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sel_x>;
1332 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sel_y>;
1333 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sel_z>;
1334 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sel_w>;
1335
1336 def : Vector_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
1337 def : Vector_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
1338
1339 // bitconvert patterns
1340
1341 def : BitConvert <i32, f32, R600_Reg32>;
1342 def : BitConvert <f32, i32, R600_Reg32>;
1343 def : BitConvert <v4f32, v4i32, R600_Reg128>;
1344
1345 } // End isR600toCayman Predicate