src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Tablegen instruction definitions
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<11> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<64> Inst;
  21   bit Trig = 0;
  22   bit Op3 = 0;
  23   bit isVector = 0;
  24   bits<2> FlagOperandIdx = 0;
  25
  26   bits<11> op_code = inst;
  27   //let Inst = inst;
  28   let Namespace = "AMDGPU";
  29   let OutOperandList = outs;
  30   let InOperandList = ins;
  31   let AsmString = asm;
  32   let Pattern = pattern;
  33   let Itinerary = itin;
  34
  35   let TSFlags{4} = Trig;
  36   let TSFlags{5} = Op3;
  37
  38   // Vector instructions are instructions that must fill all slots in an
  39   // instruction group
  40   let TSFlags{6} = isVector;
  41   let TSFlags{8-7} = FlagOperandIdx;
  42 }
  43
  44 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  45     AMDGPUInst <outs, ins, asm, pattern>
  46 {
  47   field bits<64> Inst;
  48
  49   let Namespace = "AMDGPU";
  50 }
  51
  52 def MEMxi : Operand<iPTR> {
  53   let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
  54 }
  55
  56 def MEMrr : Operand<iPTR> {
  57   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  58 }
  59
  60 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  61 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
  62 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
  63
  64 class R600_ALU {
  65
  66   bits<7> DST_GPR = 0;
  67   bits<9> SRC0_SEL = 0;
  68   bits<1> SRC0_NEG = 0;
  69   bits<9> SRC1_SEL = 0;
  70   bits<1> SRC1_NEG = 0;
  71   bits<1> CLAMP = 0;
  72
  73 }
  74
  75 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
  76                                      (ops PRED_SEL_OFF)>;
  77
  78
  79 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
  80                 InstrItinClass itin = AnyALU> :
  81   InstR600 <inst,
  82           (outs R600_Reg32:$dst),
  83           (ins R600_Reg32:$src, R600_Pred:$p, variable_ops),
  84           !strconcat(opName, " $dst, $src ($p)"),
  85           pattern,
  86           itin>{
  87     bits<7> dst;
  88     bits<9> src;
  89     let Inst{8-0}   = src;
  90     let Inst{49-39} = inst;
  91     let Inst{59-53} = dst;
  92   }
  93
  94 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
  95                 InstrItinClass itin = AnyALU> :
  96   InstR600 <inst,
  97           (outs R600_Reg32:$dst),
  98           (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops),
  99           !strconcat(opName, " $dst, $src0, $src1"),
 100           pattern,
 101           itin>{
 102     bits<7> dst;
 103     bits<9> src0;
 104     bits<9> src1;
 105     let Inst{8-0}   = src0;
 106     let Inst{21-13} = src1;
 107     let Inst{49-39} = inst;
 108     let Inst{59-53} = dst;
 109   }
 110
 111 class R600_3OP <bits<11> inst, string opName, list<dag> pattern,
 112                 InstrItinClass itin = AnyALU> :
 113   InstR600 <inst,
 114           (outs R600_Reg32:$dst),
 115           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops),
 116           !strconcat(opName, " $dst, $src0, $src1, $src2"),
 117           pattern,
 118           itin>{
 119     bits<7> dst;
 120     bits<9> src0;
 121     bits<9> src1;
 122     bits<9> src2;
 123     let Inst{8-0}   = src0;
 124     let Inst{21-13} = src1;
 125     let Inst{40-32} = src2;
 126     let Inst{49-45} = inst{4-0};
 127     let Inst{59-53} = dst;
 128     let Op3 = 1;
 129   }
 130
 131
 132
 133 def PRED_X : InstR600 <0, (outs R600_Predicate_Bit:$dst),
 134            (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
 135            "PRED $dst, $src0, $src1",
 136            [], NullALU>
 137 {
 138   bits<7> dst;
 139   bits<9> src0;
 140   bits<11> src1;
 141   let Inst{8-0}   = src0;
 142   let Inst{49-39} = src1;
 143   let Inst{59-53} = dst;
 144   let FlagOperandIdx = 3;
 145 }
 146
 147 let isTerminator = 1, isBranch = 1, isPseudo = 1 in {
 148 def JUMP : InstR600 <0x10,
 149           (outs),
 150           (ins brtarget:$target, R600_Pred:$p),
 151           "JUMP $target ($p)",
 152           [], AnyALU
 153   >;
 154 }
 155
 156 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
 157                       InstrItinClass itin = VecALU> :
 158   InstR600 <inst,
 159           (outs R600_Reg32:$dst),
 160           ins,
 161           asm,
 162           pattern,
 163           itin>{
 164     bits<7> dst;
 165     let Inst{49-39} = inst;
 166     let Inst{59-53} = dst;
 167   }
 168
 169 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
 170                 InstrItinClass itin = AnyALU> :
 171   InstR600 <inst,
 172           (outs R600_Reg128:$dst),
 173           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 174           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 175           pattern,
 176           itin>{
 177     let Inst {10-0} = inst;
 178   }
 179
 180 def TEX_SHADOW : PatLeaf<
 181   (imm),
 182   [{uint32_t TType = (uint32_t)N->getZExtValue();
 183     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 184   }]
 185 >;
 186
 187 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
 188                  dag ins, string asm, list<dag> pattern> :
 189     InstR600ISA <outs, ins, asm, pattern>
 190 {
 191   bits<7>  RW_GPR;
 192   bits<7>  INDEX_GPR;
 193
 194   bits<2>  RIM;
 195   bits<2>  TYPE;
 196   bits<1>  RW_REL;
 197   bits<2>  ELEM_SIZE;
 198
 199   bits<12> ARRAY_SIZE;
 200   bits<4>  COMP_MASK;
 201   bits<4>  BURST_COUNT;
 202   bits<1>  VPM;
 203   bits<1>  eop;
 204   bits<1>  MARK;
 205   bits<1>  BARRIER;
 206
 207   // CF_ALLOC_EXPORT_WORD0_RAT
 208   let Inst{3-0}   = rat_id;
 209   let Inst{9-4}   = rat_inst;
 210   let Inst{10}    = 0; // Reserved
 211   let Inst{12-11} = RIM;
 212   let Inst{14-13} = TYPE;
 213   let Inst{21-15} = RW_GPR;
 214   let Inst{22}    = RW_REL;
 215   let Inst{29-23} = INDEX_GPR;
 216   let Inst{31-30} = ELEM_SIZE;
 217
 218   // CF_ALLOC_EXPORT_WORD1_BUF
 219   let Inst{43-32} = ARRAY_SIZE;
 220   let Inst{47-44} = COMP_MASK;
 221   let Inst{51-48} = BURST_COUNT;
 222   let Inst{52}    = VPM;
 223   let Inst{53}    = eop;
 224   let Inst{61-54} = cf_inst;
 225   let Inst{62}    = MARK;
 226   let Inst{63}    = BARRIER;
 227 }
 228
 229 def load_param : PatFrag<(ops node:$ptr),
 230                          (load node:$ptr),
 231                           [{
 232                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 233                            if (Src) {
 234                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 235                                 return PT && PT->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS;
 236                            }
 237                            return false;
 238                           }]>;
 239
 240 def isR600 : Predicate<"Subtarget.device()"
 241                             "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
 242 def isR700 : Predicate<"Subtarget.device()"
 243                             "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
 244                             "Subtarget.device()->getDeviceFlag()"
 245                             ">= OCL_DEVICE_RV710">;
 246 def isEG : Predicate<
 247   "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
 248   "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
 249   "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 250
 251 def isCayman : Predicate<"Subtarget.device()"
 252                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 253 def isEGorCayman : Predicate<"Subtarget.device()"
 254                             "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
 255                             "|| Subtarget.device()->getGeneration() =="
 256                             "AMDGPUDeviceInfo::HD6XXX">;
 257
 258 def isR600toCayman : Predicate<
 259                      "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
 260
 261 //===----------------------------------------------------------------------===//
 262 // Interpolation Instructions
 263 //===----------------------------------------------------------------------===//
 264
 265 def INTERP: SDNode<"AMDGPUISD::INTERP",
 266   SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>
 267   >;
 268
 269 def INTERP_P0: SDNode<"AMDGPUISD::INTERP_P0",
 270   SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisInt<1>]>
 271   >;
 272
 273 let usesCustomInserter = 1 in {
 274 def input_perspective :  AMDGPUShaderInst <
 275   (outs R600_Reg128:$dst),
 276   (ins i32imm:$src0, i32imm:$src1),
 277   "input_perspective $src0 $src1 : dst",
 278   [(set R600_Reg128:$dst, (INTERP (i32 imm:$src0), (i32 imm:$src1)))]>;
 279 }  // End usesCustomInserter = 1
 280
 281 def input_constant :  AMDGPUShaderInst <
 282   (outs R600_Reg128:$dst),
 283   (ins i32imm:$src),
 284   "input_perspective $src : dst",
 285   [(set R600_Reg128:$dst, (INTERP_P0 (i32 imm:$src)))]>;
 286
 287
 288
 289 def INTERP_XY : InstR600 <0xD6,
 290   (outs R600_Reg32:$dst),
 291   (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
 292   "INTERP_XY dst",
 293   [], AnyALU>
 294 {
 295   let FlagOperandIdx = 3;
 296 }
 297
 298 def INTERP_ZW : InstR600 <0xD7,
 299   (outs R600_Reg32:$dst),
 300   (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
 301   "INTERP_ZW dst",
 302   [], AnyALU>
 303 {
 304   let FlagOperandIdx = 3;
 305 }
 306
 307 def INTERP_LOAD_P0 : InstR600 <0xE0,
 308   (outs R600_Reg32:$dst),
 309   (ins R600_Reg32:$src, i32imm:$flags),
 310   "INTERP_LOAD_P0 dst",
 311   [], AnyALU>
 312 {
 313   let FlagOperandIdx = 2;
 314 }
 315
 316 let Predicates = [isR600toCayman] in {
 317
 318 //===----------------------------------------------------------------------===//
 319 // Common Instructions R600, R700, Evergreen, Cayman
 320 //===----------------------------------------------------------------------===//
 321
 322 def ADD : R600_2OP <
 323   0x0, "ADD",
 324   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
 325 >;
 326
 327 // Non-IEEE MUL: 0 * anything = 0
 328 def MUL : R600_2OP <
 329   0x1, "MUL NON-IEEE",
 330   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 331 >;
 332
 333 def MUL_IEEE : R600_2OP <
 334   0x2, "MUL_IEEE",
 335   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
 336 >;
 337
 338 def MAX : R600_2OP <
 339   0x3, "MAX",
 340   [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
 341 >;
 342
 343 def MIN : R600_2OP <
 344   0x4, "MIN",
 345   [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
 346 >;
 347
 348 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 349 // so some of the instruction names don't match the asm string.
 350 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 351
 352 def SETE : R600_2OP <
 353   0x08, "SETE",
 354   [(set R600_Reg32:$dst,
 355    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 356              COND_EQ))]
 357 >;
 358
 359 def SGT : R600_2OP <
 360   0x09, "SETGT",
 361   [(set R600_Reg32:$dst,
 362    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 363               COND_GT))]
 364 >;
 365
 366 def SGE : R600_2OP <
 367   0xA, "SETGE",
 368   [(set R600_Reg32:$dst,
 369    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 370               COND_GE))]
 371 >;
 372
 373 def SNE : R600_2OP <
 374   0xB, "SETNE",
 375   [(set R600_Reg32:$dst,
 376    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 377     COND_NE))]
 378 >;
 379
 380 def FRACT : R600_1OP <
 381   0x10, "FRACT",
 382   [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
 383 >;
 384
 385 def TRUNC : R600_1OP <
 386   0x11, "TRUNC",
 387   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 388 >;
 389
 390 def CEIL : R600_1OP <
 391   0x12, "CEIL",
 392   [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
 393 >;
 394
 395 def RNDNE : R600_1OP <
 396   0x13, "RNDNE",
 397   [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
 398 >;
 399
 400 def FLOOR : R600_1OP <
 401   0x14, "FLOOR",
 402   [(set R600_Reg32:$dst, (ffloor R600_Reg32:$src))]
 403 >;
 404
 405 def MOV : InstR600 <0x19, (outs R600_Reg32:$dst),
 406                           (ins R600_Reg32:$src0, i32imm:$flags,
 407                                R600_Pred:$p),
 408                           "MOV $dst, $src0", [], AnyALU> {
 409   let FlagOperandIdx = 2;
 410   bits<7> dst;
 411   bits<9> src0;
 412   let Inst{8-0}   = src0;
 413   let Inst{49-39} = op_code;
 414   let Inst{59-53} = dst;
 415 }
 416
 417 class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
 418   (outs R600_Reg32:$dst),
 419   (ins R600_Reg32:$alu_literal, R600_Pred:$p, immType:$imm),
 420   "MOV_IMM $dst, $imm",
 421   [], AnyALU
 422 >{
 423   bits<7> dst;
 424   bits<9> alu_literal;
 425   bits<9> p;
 426   let Inst{8-0}   = alu_literal;
 427   let Inst{21-13} = p;
 428   let Inst{49-39} = op_code;
 429   let Inst{59-53} = dst;
 430 }
 431
 432 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
 433 def : Pat <
 434   (imm:$val),
 435   (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
 436 >;
 437
 438 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
 439 def : Pat <
 440   (fpimm:$val),
 441   (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
 442 >;
 443
 444 def KILLGT : InstR600 <0x2D,
 445           (outs R600_Reg32:$dst),
 446           (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags, R600_Pred:$p,
 447                variable_ops),
 448           "KILLGT $dst, $src0, $src1, $flags ($p)",
 449           [],
 450           NullALU>{
 451   let FlagOperandIdx = 3;
 452   bits<7> dst;
 453   bits<9> src0;
 454   bits<9> src1;
 455   let Inst{8-0}   = src0;
 456   let Inst{21-13} = src1;
 457   let Inst{49-39} = op_code;
 458   let Inst{59-53} = dst;
 459 }
 460
 461 def AND_INT : R600_2OP <
 462   0x30, "AND_INT",
 463   [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
 464 >;
 465
 466 def OR_INT : R600_2OP <
 467   0x31, "OR_INT",
 468   [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
 469 >;
 470
 471 def XOR_INT : R600_2OP <
 472   0x32, "XOR_INT",
 473   [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
 474 >;
 475
 476 def NOT_INT : R600_1OP <
 477   0x33, "NOT_INT",
 478   [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
 479 >;
 480
 481 def ADD_INT : R600_2OP <
 482   0x34, "ADD_INT",
 483   [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
 484 >;
 485
 486 def SUB_INT : R600_2OP <
 487         0x35, "SUB_INT",
 488         [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
 489 >;
 490
 491 def MAX_INT : R600_2OP <
 492   0x36, "MAX_INT",
 493   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 494
 495 def MIN_INT : R600_2OP <
 496   0x37, "MIN_INT",
 497   [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 498
 499 def MAX_UINT : R600_2OP <
 500   0x38, "MAX_UINT",
 501   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
 502 >;
 503
 504 def MIN_UINT : R600_2OP <
 505   0x39, "MIN_UINT",
 506   [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
 507 >;
 508
 509 def SETE_INT : R600_2OP <
 510   0x3A, "SETE_INT",
 511   [(set (i32 R600_Reg32:$dst),
 512    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
 513 >;
 514
 515 def SETGT_INT : R600_2OP <
 516   0x3B, "SGT_INT",
 517   [(set (i32 R600_Reg32:$dst),
 518    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
 519 >;
 520
 521 def SETGE_INT : R600_2OP <
 522         0x3C, "SETGE_INT",
 523         [(set (i32 R600_Reg32:$dst),
 524    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
 525 >;
 526
 527 def SETNE_INT : R600_2OP <
 528   0x3D, "SETNE_INT",
 529   [(set (i32 R600_Reg32:$dst),
 530    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
 531 >;
 532
 533 def SETGT_UINT : R600_2OP <
 534   0x3E, "SETGT_UINT",
 535   [(set (i32 R600_Reg32:$dst),
 536    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
 537 >;
 538
 539 def SETGE_UINT : R600_2OP <
 540   0x3F, "SETGE_UINT",
 541   [(set (i32 R600_Reg32:$dst),
 542     (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
 543 >;
 544
 545 def CNDE_INT : R600_3OP <
 546         0x1C, "CNDE_INT",
 547   [(set (i32 R600_Reg32:$dst),
 548    (selectcc (i32 R600_Reg32:$src0), 0,
 549        (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
 550        COND_EQ))]
 551 >;
 552
 553 def CNDGE_INT : R600_3OP <
 554         0x1E, "CNDGE_INT",
 555   [(set (i32 R600_Reg32:$dst),
 556    (selectcc (i32 R600_Reg32:$src0), 0,
 557        (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
 558        COND_GE))]
 559 >;
 560
 561 def CNDGT_INT : R600_3OP <
 562         0x1D, "CNDGT_INT",
 563   [(set (i32 R600_Reg32:$dst),
 564    (selectcc (i32 R600_Reg32:$src0), 0,
 565        (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
 566        COND_GT))]
 567 >;
 568
 569 //===----------------------------------------------------------------------===//
 570 // Texture instructions
 571 //===----------------------------------------------------------------------===//
 572
 573 def TEX_LD : R600_TEX <
 574   0x03, "TEX_LD",
 575   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
 576 > {
 577 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
 578 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
 579 }
 580
 581 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 582   0x04, "TEX_GET_TEXTURE_RESINFO",
 583   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 584 >;
 585
 586 def TEX_GET_GRADIENTS_H : R600_TEX <
 587   0x07, "TEX_GET_GRADIENTS_H",
 588   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 589 >;
 590
 591 def TEX_GET_GRADIENTS_V : R600_TEX <
 592   0x08, "TEX_GET_GRADIENTS_V",
 593   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 594 >;
 595
 596 def TEX_SET_GRADIENTS_H : R600_TEX <
 597   0x0B, "TEX_SET_GRADIENTS_H",
 598   []
 599 >;
 600
 601 def TEX_SET_GRADIENTS_V : R600_TEX <
 602   0x0C, "TEX_SET_GRADIENTS_V",
 603   []
 604 >;
 605
 606 def TEX_SAMPLE : R600_TEX <
 607   0x10, "TEX_SAMPLE",
 608   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 609 >;
 610
 611 def TEX_SAMPLE_C : R600_TEX <
 612   0x18, "TEX_SAMPLE_C",
 613   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 614 >;
 615
 616 def TEX_SAMPLE_L : R600_TEX <
 617   0x11, "TEX_SAMPLE_L",
 618   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 619 >;
 620
 621 def TEX_SAMPLE_C_L : R600_TEX <
 622   0x19, "TEX_SAMPLE_C_L",
 623   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 624 >;
 625
 626 def TEX_SAMPLE_LB : R600_TEX <
 627   0x12, "TEX_SAMPLE_LB",
 628   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 629 >;
 630
 631 def TEX_SAMPLE_C_LB : R600_TEX <
 632   0x1A, "TEX_SAMPLE_C_LB",
 633   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 634 >;
 635
 636 def TEX_SAMPLE_G : R600_TEX <
 637   0x14, "TEX_SAMPLE_G",
 638   []
 639 >;
 640
 641 def TEX_SAMPLE_C_G : R600_TEX <
 642   0x1C, "TEX_SAMPLE_C_G",
 643   []
 644 >;
 645
 646 //===----------------------------------------------------------------------===//
 647 // Helper classes for common instructions
 648 //===----------------------------------------------------------------------===//
 649
 650 class MUL_LIT_Common <bits<11> inst> : R600_3OP <
 651   inst, "MUL_LIT",
 652   []
 653 >;
 654
 655 class MULADD_Common <bits<11> inst> : R600_3OP <
 656   inst, "MULADD",
 657   [(set (f32 R600_Reg32:$dst),
 658    (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 659 >;
 660
 661 class CNDE_Common <bits<11> inst> : R600_3OP <
 662   inst, "CNDE",
 663   [(set R600_Reg32:$dst,
 664    (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
 665        (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
 666        COND_EQ))]
 667 >;
 668
 669 class CNDGT_Common <bits<11> inst> : R600_3OP <
 670   inst, "CNDGT",
 671   [(set R600_Reg32:$dst,
 672    (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
 673        (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
 674        COND_GT))]
 675 >;
 676
 677 class CNDGE_Common <bits<11> inst> : R600_3OP <
 678   inst, "CNDGE",
 679   [(set R600_Reg32:$dst,
 680    (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
 681        (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
 682        COND_GE))]
 683 >;
 684
 685 class DOT4_Common <bits<11> inst> : R600_REDUCTION <
 686   inst,
 687   (ins R600_Reg128:$src0, R600_Reg128:$src1, i32imm:$flags),
 688   "DOT4 $dst $src0, $src1",
 689   []
 690   > {
 691   bits<9> src0;
 692   bits<9> src1;
 693   let Inst{8-0}   = src0;
 694   let Inst{21-13} = src1;
 695   let FlagOperandIdx = 3;
 696 }
 697
 698 class DOT4_Pat <Instruction dot4> : Pat <
 699   (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1),
 700   (dot4 R600_Reg128:$src0, R600_Reg128:$src1, 0)
 701 >;
 702
 703 multiclass CUBE_Common <bits<11> inst> {
 704
 705   def _pseudo : InstR600 <
 706     inst,
 707     (outs R600_Reg128:$dst),
 708     (ins R600_Reg128:$src),
 709     "CUBE $dst $src",
 710     [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 711     VecALU
 712   >;
 713
 714   def _real : InstR600 <
 715     inst,
 716     (outs R600_Reg32:$dst),
 717     (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
 718     "CUBE $dst, $src0, $src1",
 719     [], VecALU
 720   >{
 721     let FlagOperandIdx = 3;
 722     bits<7> dst;
 723     bits<9> src0;
 724     bits<9> src1;
 725     let Inst{8-0}   = src0;
 726     let Inst{21-13} = src1;
 727     let Inst{49-39} = inst;
 728     let Inst{59-53} = dst;
 729   }
 730 }
 731
 732 class EXP_IEEE_Common <bits<11> inst> : R600_1OP <
 733   inst, "EXP_IEEE",
 734   [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
 735 >;
 736
 737 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP <
 738   inst, "FLT_TO_INT",
 739   [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))]
 740 >;
 741
 742 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP <
 743   inst, "INT_TO_FLT",
 744   [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
 745 >;
 746
 747 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP <
 748   inst, "FLT_TO_UINT",
 749   [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))]
 750 >;
 751
 752 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP <
 753   inst, "UINT_TO_FLT",
 754   [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))]
 755 >;
 756
 757 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
 758   inst, "LOG_CLAMPED",
 759   []
 760 >;
 761
 762 class LOG_IEEE_Common <bits<11> inst> : R600_1OP <
 763   inst, "LOG_IEEE",
 764   [(set R600_Reg32:$dst, (flog2 R600_Reg32:$src))]
 765 >;
 766
 767 class LSHL_Common <bits<11> inst> : R600_2OP <
 768   inst, "LSHL $dst, $src0, $src1",
 769   [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
 770 >;
 771
 772 class LSHR_Common <bits<11> inst> : R600_2OP <
 773   inst, "LSHR $dst, $src0, $src1",
 774   [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
 775 >;
 776
 777 class ASHR_Common <bits<11> inst> : R600_2OP <
 778   inst, "ASHR $dst, $src0, $src1",
 779   [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
 780 >;
 781
 782 class MULHI_INT_Common <bits<11> inst> : R600_2OP <
 783   inst, "MULHI_INT $dst, $src0, $src1",
 784   [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
 785 >;
 786
 787 class MULHI_UINT_Common <bits<11> inst> : R600_2OP <
 788   inst, "MULHI $dst, $src0, $src1",
 789   [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
 790 >;
 791
 792 class MULLO_INT_Common <bits<11> inst> : R600_2OP <
 793   inst, "MULLO_INT $dst, $src0, $src1",
 794   [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
 795 >;
 796
 797 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <
 798   inst, "MULLO_UINT $dst, $src0, $src1",
 799   []
 800 >;
 801
 802 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
 803   inst, "RECIP_CLAMPED",
 804   []
 805 >;
 806
 807 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
 808   inst, "RECIP_IEEE",
 809   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
 810 >;
 811
 812 class RECIP_UINT_Common <bits<11> inst> : R600_1OP <
 813   inst, "RECIP_INT $dst, $src",
 814   [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))]
 815 >;
 816
 817 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP <
 818   inst, "RECIPSQRT_CLAMPED",
 819   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 820 >;
 821
 822 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
 823   inst, "RECIPSQRT_IEEE",
 824   []
 825 >;
 826
 827 class SIN_Common <bits<11> inst> : R600_1OP <
 828   inst, "SIN", []>{
 829   let Trig = 1;
 830 }
 831
 832 class COS_Common <bits<11> inst> : R600_1OP <
 833   inst, "COS", []> {
 834   let Trig = 1;
 835 }
 836
 837 //===----------------------------------------------------------------------===//
 838 // Helper patterns for complex intrinsics
 839 //===----------------------------------------------------------------------===//
 840
 841 multiclass DIV_Common <InstR600 recip_ieee> {
 842 def : Pat<
 843   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 844   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 845 >;
 846
 847 def : Pat<
 848   (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
 849   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 850 >;
 851 }
 852
 853 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 854   (int_AMDGPU_ssg R600_Reg32:$src),
 855   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 856 >;
 857
 858 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 859   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 860   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 861 >;
 862
 863 //===----------------------------------------------------------------------===//
 864 // R600 / R700 Instructions
 865 //===----------------------------------------------------------------------===//
 866
 867 let Predicates = [isR600] in {
 868
 869   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 870   def MULADD_r600 : MULADD_Common<0x10>;
 871   def CNDE_r600 : CNDE_Common<0x18>;
 872   def CNDGT_r600 : CNDGT_Common<0x19>;
 873   def CNDGE_r600 : CNDGE_Common<0x1A>;
 874   def DOT4_r600 : DOT4_Common<0x50>;
 875   def : DOT4_Pat <DOT4_r600>;
 876   defm CUBE_r600 : CUBE_Common<0x52>;
 877   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 878   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 879   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 880   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 881   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 882   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 883   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 884   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 885   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 886   def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
 887   def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
 888   def SIN_r600 : SIN_Common<0x6E>;
 889   def COS_r600 : COS_Common<0x6F>;
 890   def ASHR_r600 : ASHR_Common<0x70>;
 891   def LSHR_r600 : LSHR_Common<0x71>;
 892   def LSHL_r600 : LSHL_Common<0x72>;
 893   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 894   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 895   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 896   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 897   def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
 898
 899   defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 900   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 901   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 902   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 903
 904 }
 905
 906 // Helper pattern for normalizing inputs to triginomic instructions for R700+
 907 // cards.
 908 class COS_PAT <InstR600 trig> : Pat<
 909   (fcos R600_Reg32:$src),
 910   (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
 911 >;
 912
 913 class SIN_PAT <InstR600 trig> : Pat<
 914   (fsin R600_Reg32:$src),
 915   (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
 916 >;
 917
 918 //===----------------------------------------------------------------------===//
 919 // R700 Only instructions
 920 //===----------------------------------------------------------------------===//
 921
 922 let Predicates = [isR700] in {
 923   def SIN_r700 : SIN_Common<0x6E>;
 924   def COS_r700 : COS_Common<0x6F>;
 925
 926   // R700 normalizes inputs to SIN/COS the same as EG
 927   def : SIN_PAT <SIN_r700>;
 928   def : COS_PAT <COS_r700>;
 929 }
 930
 931 //===----------------------------------------------------------------------===//
 932 // Evergreen Only instructions
 933 //===----------------------------------------------------------------------===//
 934
 935 let Predicates = [isEG] in {
 936
 937 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 938
 939 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 940 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 941 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 942 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 943 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 944
 945 } // End Predicates = [isEG]
 946
 947 //===----------------------------------------------------------------------===//
 948 // Evergreen / Cayman Instructions
 949 //===----------------------------------------------------------------------===//
 950
 951 let Predicates = [isEGorCayman] in {
 952
 953   // BFE_UINT - bit_extract, an optimization for mask and shift
 954   // Src0 = Input
 955   // Src1 = Offset
 956   // Src2 = Width
 957   //
 958   // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
 959   //
 960   // Example Usage:
 961   // (Offset, Width)
 962   //
 963   // (0, 8)           = (Input << 24) >> 24  = (Input &  0xff)       >> 0
 964   // (8, 8)           = (Input << 16) >> 24  = (Input &  0xffff)     >> 8
 965   // (16,8)           = (Input <<  8) >> 24  = (Input &  0xffffff)   >> 16
 966   // (24,8)           = (Input <<  0) >> 24  = (Input &  0xffffffff) >> 24
 967   def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
 968     [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
 969                                                       R600_Reg32:$src1,
 970                                                       R600_Reg32:$src2))],
 971     VecALU
 972   >;
 973
 974   def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
 975     [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
 976                                           R600_Reg32:$src2))],
 977     VecALU
 978   >;
 979
 980   def MULADD_eg : MULADD_Common<0x14>;
 981   def ASHR_eg : ASHR_Common<0x15>;
 982   def LSHR_eg : LSHR_Common<0x16>;
 983   def LSHL_eg : LSHL_Common<0x17>;
 984   def CNDE_eg : CNDE_Common<0x19>;
 985   def CNDGT_eg : CNDGT_Common<0x1A>;
 986   def CNDGE_eg : CNDGE_Common<0x1B>;
 987   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 988   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 989   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 990   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 991   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 992   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 993   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 994   def SIN_eg : SIN_Common<0x8D>;
 995   def COS_eg : COS_Common<0x8E>;
 996   def DOT4_eg : DOT4_Common<0xBE>;
 997   def : DOT4_Pat <DOT4_eg>;
 998   defm CUBE_eg : CUBE_Common<0xC0>;
 999
1000   defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1001   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
1002   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
1003   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1004
1005   def : SIN_PAT <SIN_eg>;
1006   def : COS_PAT <COS_eg>;
1007
1008   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1009     let Pattern = [];
1010   }
1011
1012   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1013
1014   def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1015     let Pattern = [];
1016   }
1017
1018   def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1019
1020   def : Pat<(fp_to_sint R600_Reg32:$src),
1021     (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
1022
1023   def : Pat<(fp_to_uint R600_Reg32:$src),
1024     (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
1025
1026   def : Pat<(fsqrt R600_Reg32:$src),
1027     (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
1028
1029 //===----------------------------------------------------------------------===//
1030 // Memory read/write instructions
1031 //===----------------------------------------------------------------------===//
1032
1033 let usesCustomInserter = 1 in {
1034
1035 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name> : EG_CF_RAT <
1036   0x57, 0x2, 0, (outs), ins, !strconcat(name, " $rw_gpr, $index_gpr, $eop"), []>
1037 {
1038   let RIM         = 0;
1039   // XXX: Have a separate instruction for non-indexed writes.
1040   let TYPE        = 1;
1041   let RW_REL      = 0;
1042   let ELEM_SIZE   = 0;
1043
1044   let ARRAY_SIZE  = 0;
1045   let COMP_MASK   = comp_mask;
1046   let BURST_COUNT = 0;
1047   let VPM         = 0;
1048   let MARK        = 0;
1049   let BARRIER     = 1;
1050 }
1051
1052 } // End usesCustomInserter = 1
1053
1054 // 32-bit store
1055 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1056   (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
1057   0x1, "RAT_WRITE_CACHELESS_32_eg"
1058 >;
1059
1060 // i32 global_store
1061 def : Pat <
1062   (global_store (i32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
1063   (RAT_WRITE_CACHELESS_32_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
1064 >;
1065
1066 // Floating point global_store
1067 def : Pat <
1068   (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
1069   (RAT_WRITE_CACHELESS_32_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr, 0)
1070 >;
1071
1072 //128-bit store
1073 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1074   (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, i32imm:$eop),
1075   0xf, "RAT_WRITE_CACHELESS_128"
1076 >;
1077
1078 // v4f32 global store
1079 def : Pat <
1080   (global_store (v4f32 R600_Reg128:$val), R600_TReg32_X:$ptr),
1081   (RAT_WRITE_CACHELESS_128_eg R600_Reg128:$val, R600_TReg32_X:$ptr, 0)
1082 >;
1083
1084 class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>
1085     : InstR600ISA <outs, (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr", pattern> {
1086
1087   // Operands
1088   bits<7> DST_GPR;
1089   bits<7> SRC_GPR;
1090
1091   // Static fields
1092   bits<5> VC_INST = 0;
1093   bits<2> FETCH_TYPE = 2;
1094   bits<1> FETCH_WHOLE_QUAD = 0;
1095   bits<8> BUFFER_ID = buffer_id;
1096   bits<1> SRC_REL = 0;
1097   // XXX: We can infer this field based on the SRC_GPR.  This would allow us
1098   // to store vertex addresses in any channel, not just X.
1099   bits<2> SRC_SEL_X = 0;
1100   bits<6> MEGA_FETCH_COUNT;
1101   bits<1> DST_REL = 0;
1102   bits<3> DST_SEL_X;
1103   bits<3> DST_SEL_Y;
1104   bits<3> DST_SEL_Z;
1105   bits<3> DST_SEL_W;
1106   // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1107   // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1108   // however, based on my testing if USE_CONST_FIELDS is set, then all
1109   // these fields need to be set to 0.
1110   bits<1> USE_CONST_FIELDS = 0;
1111   bits<6> DATA_FORMAT;
1112   bits<2> NUM_FORMAT_ALL = 1;
1113   bits<1> FORMAT_COMP_ALL = 0;
1114   bits<1> SRF_MODE_ALL = 0;
1115
1116   // LLVM can only encode 64-bit instructions, so these fields are manually
1117   // encoded in R600CodeEmitter
1118   //
1119   // bits<16> OFFSET;
1120   // bits<2>  ENDIAN_SWAP = 0;
1121   // bits<1>  CONST_BUF_NO_STRIDE = 0;
1122   // bits<1>  MEGA_FETCH = 0;
1123   // bits<1>  ALT_CONST = 0;
1124   // bits<2>  BUFFER_INDEX_MODE = 0;
1125
1126   // VTX_WORD0
1127   let Inst{4-0}   = VC_INST;
1128   let Inst{6-5}   = FETCH_TYPE;
1129   let Inst{7}     = FETCH_WHOLE_QUAD;
1130   let Inst{15-8}  = BUFFER_ID;
1131   let Inst{22-16} = SRC_GPR;
1132   let Inst{23}    = SRC_REL;
1133   let Inst{25-24} = SRC_SEL_X;
1134   let Inst{31-26} = MEGA_FETCH_COUNT;
1135
1136   // VTX_WORD1_GPR
1137   let Inst{38-32} = DST_GPR;
1138   let Inst{39}    = DST_REL;
1139   let Inst{40}    = 0; // Reserved
1140   let Inst{43-41} = DST_SEL_X;
1141   let Inst{46-44} = DST_SEL_Y;
1142   let Inst{49-47} = DST_SEL_Z;
1143   let Inst{52-50} = DST_SEL_W;
1144   let Inst{53}    = USE_CONST_FIELDS;
1145   let Inst{59-54} = DATA_FORMAT;
1146   let Inst{61-60} = NUM_FORMAT_ALL;
1147   let Inst{62}    = FORMAT_COMP_ALL;
1148   let Inst{63}    = SRF_MODE_ALL;
1149
1150   // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1151   // is done in R600CodeEmitter
1152   //
1153   // Inst{79-64} = OFFSET;
1154   // Inst{81-80} = ENDIAN_SWAP;
1155   // Inst{82}    = CONST_BUF_NO_STRIDE;
1156   // Inst{83}    = MEGA_FETCH;
1157   // Inst{84}    = ALT_CONST;
1158   // Inst{86-85} = BUFFER_INDEX_MODE;
1159   // Inst{95-86} = 0; Reserved
1160
1161   // VTX_WORD3 (Padding)
1162   //
1163   // Inst{127-96} = 0;
1164 }
1165
1166 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1167     : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
1168
1169   let MEGA_FETCH_COUNT = 1;
1170   let DST_SEL_X = 0;
1171   let DST_SEL_Y = 7;   // Masked
1172   let DST_SEL_Z = 7;   // Masked
1173   let DST_SEL_W = 7;   // Masked
1174   let DATA_FORMAT = 1; // FMT_8
1175 }
1176
1177 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1178     : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
1179
1180   let MEGA_FETCH_COUNT = 4;
1181   let DST_SEL_X        = 0;
1182   let DST_SEL_Y        = 7;   // Masked
1183   let DST_SEL_Z        = 7;   // Masked
1184   let DST_SEL_W        = 7;   // Masked
1185   let DATA_FORMAT      = 0xD; // COLOR_32
1186
1187   // This is not really necessary, but there were some GPU hangs that appeared
1188   // to be caused by ALU instructions in the next instruction group that wrote
1189   // to the $ptr registers of the VTX_READ.
1190   // e.g.
1191   // %T3_X<def> = VTX_READ_PARAM_i32_eg %T2_X<kill>, 24
1192   // %T2_X<def> = MOV %ZERO
1193   //Adding this constraint prevents this from happening.
1194   let Constraints = "$ptr.ptr = $dst";
1195 }
1196
1197 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1198     : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> {
1199
1200   let MEGA_FETCH_COUNT = 16;
1201   let DST_SEL_X        =  0;
1202   let DST_SEL_Y        =  1;
1203   let DST_SEL_Z        =  2;
1204   let DST_SEL_W        =  3;
1205   let DATA_FORMAT      =  0x22; // COLOR_32_32_32_32
1206
1207   // XXX: Need to force VTX_READ_128 instructions to write to the same register
1208   // that holds its buffer address to avoid potential hangs.  We can't use
1209   // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1210   // registers are different sizes.
1211 }
1212
1213 //===----------------------------------------------------------------------===//
1214 // VTX Read from parameter memory space
1215 //===----------------------------------------------------------------------===//
1216
1217 class VTX_READ_PARAM_32_eg <ValueType vt> : VTX_READ_32_eg <0,
1218   [(set (vt R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1219 >;
1220
1221 def VTX_READ_PARAM_i32_eg : VTX_READ_PARAM_32_eg<i32>;
1222 def VTX_READ_PARAM_f32_eg : VTX_READ_PARAM_32_eg<f32>;
1223
1224
1225 //===----------------------------------------------------------------------===//
1226 // VTX Read from global memory space
1227 //===----------------------------------------------------------------------===//
1228
1229 // 8-bit reads
1230 def VTX_READ_GLOBAL_i8_eg : VTX_READ_8_eg <1,
1231   [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
1232 >;
1233
1234 // 32-bit reads
1235
1236 class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1,
1237   [(set (vt R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1238 >;
1239
1240 def VTX_READ_GLOBAL_i32_eg : VTX_READ_GLOBAL_eg<i32>;
1241 def VTX_READ_GLOBAL_f32_eg : VTX_READ_GLOBAL_eg<f32>;
1242
1243 // 128-bit reads
1244
1245 class VTX_READ_GLOBAL_128_eg <ValueType vt> : VTX_READ_128_eg <1,
1246   [(set (vt R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1247 >;
1248
1249 def VTX_READ_GLOBAL_v4i32_eg : VTX_READ_GLOBAL_128_eg<v4i32>;
1250 def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>;
1251
1252 //===----------------------------------------------------------------------===//
1253 // Constant Loads
1254 // XXX: We are currently storing all constants in the global address space.
1255 //===----------------------------------------------------------------------===//
1256
1257 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1258   [(set (f32 R600_TReg32_X:$dst), (constant_load ADDRVTX_READ:$ptr))]
1259 >;
1260
1261 }
1262
1263 let Predicates = [isCayman] in {
1264
1265 let isVector = 1 in {
1266
1267 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1268
1269 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1270 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1271 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1272 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1273
1274 } // End isVector = 1
1275
1276 // RECIP_UINT emulation for Cayman
1277 def : Pat <
1278   (AMDGPUurecip R600_Reg32:$src0),
1279   (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1280                             (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000)))
1281 >;
1282
1283 } // End isCayman
1284
1285 let isCodeGenOnly = 1 in {
1286
1287   def MULLIT : AMDGPUShaderInst <
1288     (outs R600_Reg128:$dst),
1289     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
1290     "MULLIT $dst, $src0, $src1",
1291     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
1292   >;
1293
1294 let usesCustomInserter = 1, isPseudo = 1 in {
1295
1296 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
1297   (outs R600_TReg32:$dst),
1298   (ins),
1299   asm,
1300   [(set R600_TReg32:$dst, (intr))]
1301 >;
1302
1303 def R600_LOAD_CONST : AMDGPUShaderInst <
1304   (outs R600_Reg32:$dst),
1305   (ins i32imm:$src0),
1306   "R600_LOAD_CONST $dst, $src0",
1307   [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1308 >;
1309
1310 def RESERVE_REG : AMDGPUShaderInst <
1311   (outs),
1312   (ins i32imm:$src),
1313   "RESERVE_REG $src",
1314   [(int_AMDGPU_reserve_reg imm:$src)]
1315 >;
1316
1317 def TXD: AMDGPUShaderInst <
1318   (outs R600_Reg128:$dst),
1319   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1320   "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1321   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1322 >;
1323
1324 def TXD_SHADOW: AMDGPUShaderInst <
1325   (outs R600_Reg128:$dst),
1326   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1327   "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1328   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1329 >;
1330
1331 } // End usesCustomInserter = 1, isPseudo = 1
1332
1333 } // End isCodeGenOnly = 1
1334
1335 def CLAMP_R600 :  CLAMP <R600_Reg32>;
1336 def FABS_R600 : FABS<R600_Reg32>;
1337 def FNEG_R600 : FNEG<R600_Reg32>;
1338
1339 let usesCustomInserter = 1 in {
1340
1341 def MASK_WRITE : AMDGPUShaderInst <
1342     (outs),
1343     (ins R600_Reg32:$src),
1344     "MASK_WRITE $src",
1345     []
1346 >;
1347
1348 } // End usesCustomInserter = 1
1349
1350 //===---------------------------------------------------------------------===//
1351 // Return instruction
1352 //===---------------------------------------------------------------------===//
1353 let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
1354   def RETURN          : ILFormat<(outs), (ins variable_ops),
1355       "RETURN", [(IL_retflag)]>;
1356 }
1357
1358 //===----------------------------------------------------------------------===//
1359 // ISel Patterns
1360 //===----------------------------------------------------------------------===//
1361
1362 // KIL Patterns
1363 def KILP : Pat <
1364   (int_AMDGPU_kilp),
1365   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO), 0))
1366 >;
1367
1368 def KIL : Pat <
1369   (int_AMDGPU_kill R600_Reg32:$src0),
1370   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0), 0))
1371 >;
1372
1373 // SGT Reverse args
1374 def : Pat <
1375   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1376   (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1377 >;
1378
1379 // SGE Reverse args
1380 def : Pat <
1381   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1382   (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1383 >;
1384
1385 // SETGT_INT reverse args
1386 def : Pat <
1387   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1388   (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1389 >;
1390
1391 // SETGE_INT reverse args
1392 def : Pat <
1393   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1394   (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1395 >;
1396
1397 // SETGT_UINT reverse args
1398 def : Pat <
1399   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1400   (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1401 >;
1402
1403 // SETGE_UINT reverse args
1404 def : Pat <
1405   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1406   (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1407 >;
1408
1409 // The next two patterns are special cases for handling 'true if ordered' and
1410 // 'true if unordered' conditionals.  The assumption here is that the behavior of
1411 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1412 // described here:
1413 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1414 // We assume that  SETE returns false when one of the operands is NAN and
1415 // SNE returns true when on of the operands is NAN
1416
1417 //SETE - 'true if ordered'
1418 def : Pat <
1419   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1420   (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1421 >;
1422
1423 //SNE - 'true if unordered'
1424 def : Pat <
1425   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1426   (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1427 >;
1428
1429 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1430 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1431 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1432 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1433
1434 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sel_x>;
1435 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sel_y>;
1436 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sel_z>;
1437 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sel_w>;
1438
1439 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1440 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1441 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1442 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1443
1444 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sel_x>;
1445 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sel_y>;
1446 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sel_z>;
1447 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sel_w>;
1448
1449 def : Vector_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
1450 def : Vector_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
1451
1452 // bitconvert patterns
1453
1454 def : BitConvert <i32, f32, R600_Reg32>;
1455 def : BitConvert <f32, i32, R600_Reg32>;
1456 def : BitConvert <v4f32, v4i32, R600_Reg128>;
1457
1458 } // End isR600toCayman Predicate