src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - TODO: Add brief description -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // TODO: Add full description
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<32> Inst;
  21         bit Trig = 0;
  22   bit Op3 = 0;
  23
  24   let Inst = inst;
  25   let Namespace = "AMDIL";
  26   let OutOperandList = outs;
  27   let InOperandList = ins;
  28   let AsmString = asm;
  29   let Pattern = pattern;
  30   let Itinerary = itin;
  31
  32   let TSFlags{4} = Trig;
  33   let TSFlags{5} = Op3;
  34 }
  35
  36 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  37     AMDGPUInst <outs, ins, asm, pattern>
  38 {
  39   field bits<64> Inst;
  40
  41   let Namespace = "AMDIL";
  42 }
  43
  44 def MEMri : Operand<iPTRAny> {
  45   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  46 }
  47
  48 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  49
  50 class R600_ALU {
  51
  52   bits<7> DST_GPR = 0;
  53   bits<9> SRC0_SEL = 0;
  54   bits<1> SRC0_NEG = 0;
  55   bits<9> SRC1_SEL = 0;
  56   bits<1> SRC1_NEG = 0;
  57   bits<1> CLAMP = 0;
  58
  59 }
  60
  61
  62 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
  63                 InstrItinClass itin = AnyALU> :
  64   InstR600 <inst,
  65           (outs R600_Reg32:$dst),
  66           (ins R600_Reg32:$src, variable_ops),
  67           !strconcat(opName, " $dst, $src"),
  68           pattern,
  69           itin
  70   >;
  71
  72 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
  73                 InstrItinClass itin = AnyALU> :
  74   InstR600 <inst,
  75           (outs R600_Reg32:$dst),
  76           (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
  77           !strconcat(opName, " $dst, $src0, $src1"),
  78           pattern,
  79           itin
  80   >;
  81
  82 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
  83                 InstrItinClass itin = AnyALU> :
  84   InstR600 <inst,
  85           (outs R600_Reg32:$dst),
  86           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
  87           !strconcat(opName, " $dst, $src0, $src1, $src2"),
  88           pattern,
  89           itin>{
  90
  91     let Op3 = 1;
  92   }
  93
  94 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
  95                       InstrItinClass itin = VecALU> :
  96   InstR600 <inst,
  97           (outs R600_Reg32:$dst),
  98           ins,
  99           asm,
 100           pattern,
 101           itin
 102
 103   >;
 104
 105 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
 106                 InstrItinClass itin = AnyALU> :
 107   InstR600 <inst,
 108           (outs R600_Reg128:$dst),
 109           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 110           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 111           pattern,
 112           itin
 113   >;
 114
 115 def TEX_SHADOW : PatLeaf<
 116   (imm),
 117   [{uint32_t TType = (uint32_t)N->getZExtValue();
 118     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 119   }]
 120 >;
 121
 122 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
 123                  string asm> :
 124     InstR600ISA <outs, ins, asm, []>
 125 {
 126   bits<7>  RW_GPR;
 127   bits<7>  INDEX_GPR;
 128   bits<4>  RAT_ID;
 129
 130   bits<2>  RIM;
 131   bits<2>  TYPE;
 132   bits<1>  RW_REL;
 133   bits<2>  ELEM_SIZE;
 134
 135   bits<12> ARRAY_SIZE;
 136   bits<4>  COMP_MASK;
 137   bits<4>  BURST_COUNT;
 138   bits<1>  VPM;
 139   bits<1>  EOP;
 140   bits<1>  MARK;
 141   bits<1>  BARRIER;
 142
 143   /* CF_ALLOC_EXPORT_WORD0_RAT */
 144   let Inst{3-0}   = RAT_ID;
 145   let Inst{9-4}   = rat_inst;
 146   let Inst{10}    = 0; /* Reserved */
 147   let Inst{12-11} = RIM;
 148   let Inst{14-13} = TYPE;
 149   let Inst{21-15} = RW_GPR;
 150   let Inst{22}    = RW_REL;
 151   let Inst{29-23} = INDEX_GPR;
 152   let Inst{31-30} = ELEM_SIZE;
 153
 154   /* CF_ALLOC_EXPORT_WORD1_BUF */
 155 /* XXX: We can't have auto encoding of 64-bit instructions until LLVM 3.1 :( */
 156 /*
 157   let Inst{43-32} = ARRAY_SIZE;
 158   let Inst{47-44} = COMP_MASK;
 159   let Inst{51-48} = BURST_COUNT;
 160   let Inst{52}    = VPM;
 161   let Inst{53}    = EOP;
 162   let Inst{61-54} = cf_inst;
 163   let Inst{62}    = MARK;
 164   let Inst{63}    = BARRIER;
 165 */
 166 }
 167
 168 /*
 169 def store_global : PatFrag<(ops node:$value, node:$ptr),
 170                            (store node:$value, node:$ptr),
 171                            [{
 172                             const Value *Src;
 173                             const PointerType *Type;
 174                             if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
 175                                  PT = dyn_cast<PointerType>(Src->getType()))) {
 176                               return PT->getAddressSpace() == 1;
 177                             }
 178                             return false;
 179                            }]>;
 180
 181 */
 182
 183 def load_param : PatFrag<(ops node:$ptr),
 184                          (load node:$ptr),
 185                           [{
 186                            return true;
 187                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 188                            if (Src) {
 189                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 190                                 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
 191                            }
 192                            return false;
 193                           }]>;
 194
 195 //class EG_CF <bits<32> inst, string asm> :
 196 //    InstR600 <inst, (outs), (ins), asm, []>;
 197
 198 /* XXX: We will use this when we emit the real ISA.
 199   bits<24> ADDR = 0;
 200   bits<3> JTS = 0;
 201
 202   bits<3> PC = 0;
 203   bits<5> CF_CONS = 0;
 204   bits<2> COND = 0;
 205   bits<6> COUNT = 0;
 206   bits<1> VPM = 0;
 207   bits<1> EOP = 0;
 208   bits<8> CF_INST = 0;
 209   bits<1> WQM = 0;
 210   bits<1> B = 0;
 211
 212   let Inst{23-0} = ADDR;
 213   let Inst{26-24} = JTS;
 214   let Inst{34-32} = PC;
 215   let Inst{39-35} = CF_CONST;
 216   let Inst{41-40} = COND;
 217   let Inst{47-42} = COUNT;
 218   let Inst{52} = VPM;
 219   let Inst{53} = EOP;
 220   let Inst{61-54} = CF_INST;
 221   let Inst{62} = WQM;
 222   let Inst{63} = B;
 223 //}
 224 */
 225 def isR600 : Predicate<"Subtarget.device()"
 226                             "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
 227 def isEG : Predicate<"Subtarget.device()"
 228                             "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
 229                             "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 230 def isCayman : Predicate<"Subtarget.device()"
 231                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 232 def isEGorCayman : Predicate<"Subtarget.device()"
 233                             "->getGeneration() >= AMDILDeviceInfo::HD5XXX">;
 234
 235 def isR600toCayman : Predicate<
 236                      "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
 237
 238
 239 let Predicates = [isR600toCayman] in {
 240
 241 /* ------------------------------------------- */
 242 /* Common Instructions R600, R700, Evergreen, Cayman */
 243 /* ------------------------------------------- */
 244 let Gen = AMDGPUGen.R600_CAYMAN  in {
 245
 246 def ADD : R600_2OP <
 247   0x0, "ADD",
 248   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))] > {
 249   let AMDILOp = AMDILInst.ADD_f32;
 250 }
 251 // Non-IEEE MUL: 0 * anything = 0
 252 def MUL : R600_2OP <
 253   0x1, "MUL NON-IEEE",
 254   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 255 >;
 256
 257 def MUL_IEEE : R600_2OP <
 258   0x2, "MUL_IEEE",
 259   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]> {
 260   let AMDILOp = AMDILInst.MUL_IEEE_f32;
 261 }
 262
 263 def MAX : R600_2OP <
 264   0x3, "MAX",
 265   [(set R600_Reg32:$dst, (int_AMDIL_max R600_Reg32:$src0, R600_Reg32:$src1))]> {
 266   let AMDILOp = AMDILInst.MAX_f32;
 267 }
 268
 269 def MIN : R600_2OP <
 270   0x4, "MIN",
 271   [(set R600_Reg32:$dst, (int_AMDIL_min R600_Reg32:$src0, R600_Reg32:$src1))]> {
 272   let AMDILOp = AMDILInst.MIN_f32;
 273 }
 274
 275 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 276  * so some of the instruction names don't match the asm string.
 277  * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 278  */
 279
 280 def SETE : R600_2OP <
 281   0x08, "SETE",
 282   [(set R600_Reg32:$dst, (int_AMDGPU_seq R600_Reg32:$src0, R600_Reg32:$src1))]> {
 283   let AMDILOp = AMDILInst.FEQ;
 284 }
 285
 286 def SGT : R600_2OP <
 287   0x09, "SETGT",
 288   [(set R600_Reg32:$dst, (int_AMDGPU_sgt R600_Reg32:$src0, R600_Reg32:$src1))]
 289 >;
 290
 291 def SGE : R600_2OP <
 292   0xA, "SETGE",
 293   [(set R600_Reg32:$dst, (int_AMDGPU_sge R600_Reg32:$src0, R600_Reg32:$src1))]> {
 294   let AMDILOp = AMDILInst.FGE;
 295 }
 296
 297 def SNE : R600_2OP <
 298   0xB, "SETNE",
 299   [(set R600_Reg32:$dst, (int_AMDGPU_sne R600_Reg32:$src0, R600_Reg32:$src1))]> {
 300   let AMDILOp = AMDILInst.FNE;
 301 }
 302
 303 def FRACT : R600_1OP <
 304   0x10, "FRACT",
 305   []> {
 306   let AMDILOp = AMDILInst.FRAC_f32;
 307 }
 308
 309 def TRUNC : R600_1OP <
 310   0x11, "TRUNC",
 311   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 312 >;
 313
 314 def CEIL : R600_1OP <
 315   0x12, "CEIL",
 316   [(set R600_Reg32:$dst, (int_AMDIL_round_neginf R600_Reg32:$src))]> {
 317   let AMDILOp = AMDILInst.ROUND_NEGINF_f32;
 318 }
 319
 320 def RNDNE : R600_1OP <
 321   0x13, "RNDNE",
 322   [(set R600_Reg32:$dst, (int_AMDIL_round_nearest R600_Reg32:$src))]> {
 323   let AMDILOp = AMDILInst.ROUND_NEAREST_f32;
 324 }
 325
 326 def FLOOR : R600_1OP <
 327   0x14, "FLOOR",
 328   [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
 329 >;
 330
 331 def MOV : R600_1OP <0x19, "MOV", []>;
 332
 333 def KILLGT : R600_2OP <
 334   0x2D, "KILLGT",
 335   []
 336 >;
 337
 338 def AND_INT : R600_2OP <
 339   0x30, "AND_INT",
 340   []> {
 341   let AMDILOp = AMDILInst.AND_i32;
 342 }
 343
 344 def OR_INT : R600_2OP <
 345   0x31, "OR_INT",
 346   []>{
 347   let AMDILOp = AMDILInst.BINARY_OR_i32;
 348 }
 349
 350 def XOR_INT : R600_2OP <
 351   0x32, "XOR_INT",
 352   []
 353 >;
 354
 355 def NOT_INT : R600_1OP <
 356   0x33, "NOT_INT",
 357   []>{
 358   let AMDILOp = AMDILInst.BINARY_NOT_i32;
 359 }
 360
 361 def ADD_INT : R600_2OP <
 362   0x34, "ADD_INT",
 363   []>{
 364   let AMDILOp = AMDILInst.ADD_i32;
 365 }
 366
 367 def SUB_INT : R600_2OP <
 368         0x35, "SUB_INT",
 369         []
 370 >;
 371
 372 def MAX_INT : R600_2OP <
 373   0x36, "MAX_INT",
 374   [(set R600_Reg32:$dst, (int_AMDGPU_imax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 375
 376 def MIN_INT : R600_2OP <
 377   0x37, "MIN_INT",
 378   [(set R600_Reg32:$dst, (int_AMDGPU_imin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 379
 380 def MAX_UINT : R600_2OP <
 381   0x38, "MAX_UINT",
 382   [(set R600_Reg32:$dst, (int_AMDGPU_umax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 383
 384 def MIN_UINT : R600_2OP <
 385   0x39, "MIN_UINT",
 386   [(set R600_Reg32:$dst, (int_AMDGPU_umin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 387
 388
 389 def SETE_INT : R600_2OP <
 390   0x3A, "SETE_INT",
 391   []>{
 392   let AMDILOp = AMDILInst.IEQ;
 393 }
 394
 395 def SETGT_INT : R600_2OP <
 396   0x3B, "SGT_INT",
 397   []
 398 >;
 399
 400 def SETGE_INT : R600_2OP <
 401         0x3C, "SETGE_INT",
 402         []>{
 403   let AMDILOp = AMDILInst.IGE;
 404 }
 405
 406 def SETNE_INT : R600_2OP <
 407   0x3D, "SETNE_INT",
 408   []>{
 409   let AMDILOp = AMDILInst.INE;
 410 }
 411
 412 def SETGT_UINT : R600_2OP <
 413   0x3E, "SETGT_UINT",
 414   []>{
 415   let AMDILOp = AMDILInst.UGT;
 416 }
 417
 418 def SETGE_UINT : R600_2OP <
 419   0x3F, "SETGE_UINT",
 420   []>{
 421   let AMDILOp = AMDILInst.UGE;
 422 }
 423
 424 def CNDE_INT : R600_3OP <
 425         0x1C, "CNDE_INT",
 426         []
 427 >;
 428
 429 /* Texture instructions */
 430
 431
 432 def TEX_LD : R600_TEX <
 433   0x03, "TEX_LD",
 434   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2))]
 435 >;
 436
 437 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 438   0x04, "TEX_GET_TEXTURE_RESINFO",
 439   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 440 >;
 441
 442 def TEX_GET_GRADIENTS_H : R600_TEX <
 443   0x07, "TEX_GET_GRADIENTS_H",
 444   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 445 >;
 446
 447 def TEX_GET_GRADIENTS_V : R600_TEX <
 448   0x08, "TEX_GET_GRADIENTS_V",
 449   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 450 >;
 451
 452 def TEX_SAMPLE : R600_TEX <
 453   0x10, "TEX_SAMPLE",
 454   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 455 >;
 456
 457 def TEX_SAMPLE_C : R600_TEX <
 458   0x18, "TEX_SAMPLE_C",
 459   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 460 >;
 461
 462 def TEX_SAMPLE_L : R600_TEX <
 463   0x11, "TEX_SAMPLE_L",
 464   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 465 >;
 466
 467 def TEX_SAMPLE_C_L : R600_TEX <
 468   0x19, "TEX_SAMPLE_C_L",
 469   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 470 >;
 471
 472 def TEX_SAMPLE_LB : R600_TEX <
 473   0x12, "TEX_SAMPLE_LB",
 474   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 475 >;
 476
 477 def TEX_SAMPLE_C_LB : R600_TEX <
 478   0x1A, "TEX_SAMPLE_C_LB",
 479   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 480 >;
 481
 482 def TEX_SAMPLE_G : R600_TEX <
 483   0x14, "TEX_SAMPLE_G",
 484   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, imm:$src1, imm:$src2))]
 485 >;
 486
 487 def TEX_SAMPLE_C_G : R600_TEX <
 488   0x1C, "TEX_SAMPLE_C_G",
 489   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 490 >;
 491
 492 } // End Gen R600_CAYMAN
 493
 494 def KILP : Pat <
 495   (int_AMDGPU_kilp),
 496   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
 497 >;
 498
 499 def KIL : Pat <
 500   (int_AMDGPU_kill R600_Reg32:$src0),
 501   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
 502 >;
 503
 504 /* Helper classes for common instructions */
 505
 506 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
 507   inst, "MUL_LIT",
 508   []
 509 >;
 510
 511 class MULADD_Common <bits<32> inst> : R600_3OP <
 512   inst, "MULADD",
 513   []> {
 514   let AMDILOp = AMDILInst.MAD_f32;
 515 }
 516
 517 class CNDE_Common <bits<32> inst> : R600_3OP <
 518   inst, "CNDE",
 519   []> {
 520   let AMDILOp = AMDILInst.CMOVLOG_f32;
 521 }
 522
 523 class CNDGT_Common <bits<32> inst> : R600_3OP <
 524   inst, "CNDGT",
 525   []
 526 >;
 527
 528 class CNDGE_Common <bits<32> inst> : R600_3OP <
 529   inst, "CNDGE",
 530   [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 531 >;
 532
 533 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
 534   inst,
 535   (ins R600_Reg128:$src0, R600_Reg128:$src1),
 536   "DOT4 $dst $src0, $src1",
 537   [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 538 >;
 539
 540 class CUBE_Common <bits<32> inst> : InstR600 <
 541   inst,
 542   (outs R600_Reg128:$dst),
 543   (ins R600_Reg128:$src),
 544   "CUBE $dst $src",
 545   [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 546   VecALU
 547 >;
 548
 549 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
 550   inst, "EXP_IEEE",
 551   []> {
 552   let AMDILOp = AMDILInst.EXP_f32;
 553 }
 554
 555 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
 556   inst, "FLT_TO_INT", []> {
 557   let AMDILOp = AMDILInst.FTOI;
 558 }
 559
 560 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 561   inst, "INT_TO_FLT", []> {
 562   let AMDILOp = AMDILInst.ITOF;
 563 }
 564
 565 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 566   inst, "LOG_CLAMPED",
 567   []
 568 >;
 569
 570 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
 571   inst, "LOG_IEEE",
 572   []> {
 573   let AMDILOp = AMDILInst.LOG_f32;
 574 }
 575
 576 class LSHL_Common <bits<32> inst> : R600_2OP <
 577   inst, "LSHL $dst, $src0, $src1",
 578   [] >{
 579   let AMDILOp = AMDILInst.SHL_i32;
 580 }
 581
 582 class LSHR_Common <bits<32> inst> : R600_2OP <
 583   inst, "LSHR $dst, $src0, $src1",
 584   [] >{
 585   let AMDILOp = AMDILInst.USHR_i32;
 586 }
 587
 588 class ASHR_Common <bits<32> inst> : R600_2OP <
 589   inst, "ASHR $dst, $src0, $src1",
 590   [] >{
 591   let AMDILOp = AMDILInst.SHR_i32;
 592 }
 593
 594 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
 595   inst, "MULHI_INT $dst, $src0, $src1",
 596   [] >{
 597   let AMDILOp = AMDILInst.SMULHI_i32;
 598 }
 599
 600 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
 601         inst, "MULHI $dst, $src0, $src1",
 602         []
 603 >;
 604
 605 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
 606   inst, "MULLO_INT $dst, $src0, $src1",
 607   [] >{
 608   let AMDILOp = AMDILInst.SMUL_i32;
 609 }
 610
 611 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
 612   inst, "MULLO_UINT $dst, $src0, $src1",
 613   []
 614 >;
 615
 616 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 617   inst, "RECIP_CLAMPED",
 618   []
 619 >;
 620
 621 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
 622   inst, "RECIP_IEEE",
 623   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
 624   let AMDILOp = AMDILInst.RSQ_f32;
 625 }
 626
 627 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
 628   inst, "RECIP_INT $dst, $src",
 629   []
 630 >;
 631
 632 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
 633   inst, "RECIPSQRT_CLAMPED",
 634   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 635 >;
 636
 637 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 638   inst, "RECIPSQRT_IEEE",
 639   []
 640 >;
 641
 642 class SIN_Common <bits<32> inst> : R600_1OP <
 643   inst, "SIN",
 644   []>{
 645   let AMDILOp = AMDILInst.SIN_f32;
 646   let Trig = 1;
 647 }
 648
 649 class COS_Common <bits<32> inst> : R600_1OP <
 650   inst, "COS",
 651   []> {
 652   let AMDILOp = AMDILInst.COS_f32;
 653   let Trig = 1;
 654 }
 655
 656 /* Helper patterns for complex intrinsics */
 657 /* -------------------------------------- */
 658
 659 class DIV_Common <InstR600 recip_ieee> : Pat<
 660   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 661   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 662 >;
 663
 664 class LRP_Common <InstR600 muladd> : Pat <
 665   (int_AMDGPU_lrp R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
 666   (muladd R600_Reg32:$src0, R600_Reg32:$src1, (MUL (SUB_f32 ONE, R600_Reg32:$src0), R600_Reg32:$src2))
 667 >;
 668
 669 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 670   (int_AMDGPU_ssg R600_Reg32:$src),
 671   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 672 >;
 673
 674 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 675   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 676   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 677 >;
 678
 679 /* ---------------------- */
 680 /* R600 / R700 Only Instructions */
 681 /* ---------------------- */
 682
 683 let Predicates = [isR600] in {
 684
 685 let Gen = AMDGPUGen.R600 in {
 686
 687   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 688   def MULADD_r600 : MULADD_Common<0x10>;
 689   def CNDE_r600 : CNDE_Common<0x18>;
 690   def CNDGT_r600 : CNDGT_Common<0x19>;
 691   def CNDGE_r600 : CNDGE_Common<0x1A>;
 692   def DOT4_r600 : DOT4_Common<0x50>;
 693   def CUBE_r600 : CUBE_Common<0x52>;
 694   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 695   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 696   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 697   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 698   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 699   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 700   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 701   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 702   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 703   def SIN_r600 : SIN_Common<0x6E>;
 704   def COS_r600 : COS_Common<0x6F>;
 705   def ASHR_r600 : ASHR_Common<0x70>;
 706   def LSHR_r600 : LSHR_Common<0x71>;
 707   def LSHL_r600 : LSHL_Common<0x72>;
 708   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 709   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 710   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 711   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 712   def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
 713
 714 } // End AMDGPUGen.R600
 715
 716   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 717   def LRP_r600 : LRP_Common<MULADD_r600>;
 718   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 719   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 720   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 721
 722 }
 723
 724 /* ----------------- */
 725 /* R700+ Trig helper */
 726 /* ----------------- */
 727
 728 /*
 729 class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
 730   (trig_inst R600_Reg32:$src),
 731   (trig_inst (fmul R600_Reg32:$src, (PI))))
 732 >;
 733 */
 734
 735 /* ---------------------- */
 736 /* Evergreen Instructions */
 737 /* ---------------------- */
 738
 739
 740 let Predicates = [isEG] in {
 741
 742 let Gen = AMDGPUGen.EG in {
 743
 744 def RAT_WRITE_CACHELESS_eg :
 745     EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
 746                                    R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
 747 {
 748 /*
 749   let Inst{3-0}   = RAT_ID;
 750   let Inst{21-15} = RW_GPR;
 751   let Inst{29-23} = INDEX_GPR;
 752   /* Propery of the UAV */
 753   let Inst{31-30} = ELEM_SIZE;
 754 */
 755   let RIM         = 0;
 756   /* XXX: Have a separate instruction for non-indexed writes. */
 757   let TYPE        = 1;
 758   let RW_REL      = 0;
 759   let ELEM_SIZE   = 0;
 760
 761 /*
 762   let ARRAY_SIZE  = 0;
 763   let COMP_MASK   = 1;
 764   let BURST_COUNT = 0;
 765   let VPM         = 0;
 766   let EOP         = 0;
 767   let MARK        = 0;
 768   let BARRIER     = 1;
 769 */
 770 }
 771
 772 def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
 773                                 (ins R600_TReg32_X:$src, i32imm:$buffer_id),
 774                                 "VTX_READ_eg $dst, $src", []>
 775 {
 776 /*
 777   bits<7> DST_GPR;
 778   bits<7> SRC_GPR;
 779   bits<8> BUFFER_ID;
 780 */
 781   /* If any of these field below need to be calculated at compile time, and
 782    * a ins operand for them and move them to the list of operands above. */
 783
 784   /* XXX: This instruction is manual encoded, so none of these values are used.
 785    */
 786 /*
 787   bits<5> VC_INST          = 0; //VC_INST_FETCH
 788   bits<2> FETCH_TYPE       = 2;
 789   bits<1> FETCH_WHOLE_QUAD = 1;
 790   bits<1> SRC_REL          = 0;
 791   bits<2> SRC_SEL_X        = 0;
 792   bits<6> MEGA_FETCH_COUNT = 4;
 793 */
 794 /*
 795
 796   bits<1> DST_REL          = 0;
 797   bits<3> DST_SEL_X        = 0;
 798   bits<3> DST_SEL_Y        = 7; //Masked
 799   bits<3> DST_SEL_Z        = 7; //Masked
 800   bits<3> DST_SEL_W        = 7; //Masked
 801   bits<1> USE_CONST_FIELDS = 1; //Masked
 802   bits<6> DATA_FORMAT      = 0;
 803   bits<2> NUM_FORMAT_ALL   = 0;
 804   bits<1> FORMAT_COMP_ALL  = 0;
 805   bits<1> SRF_MODE_ALL     = 0;
 806 */
 807
 808 /*
 809   let Inst{4-0}   = VC_INST;
 810   let Inst{6-5}   = FETCH_TYPE;
 811   let Inst{7}     = FETCH_WHOLE_QUAD;
 812   let Inst{15-8}  = BUFFER_ID;
 813   let Inst{22-16} = SRC_GPR;
 814   let Inst{23}    = SRC_REL;
 815   let Inst{25-24} = SRC_SEL_X;
 816   let Inst{31-26} = MEGA_FETCH_COUNT;
 817 */
 818   /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you
 819    * from statically setting bits > 31.  This field will be set by
 820    * getMachineValueOp which can set bits > 31.
 821    */
 822 //  let Inst{32-38} = DST_GPR;
 823
 824   /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */
 825
 826 /*
 827   let Inst{39}    = DST_REL;
 828   let Inst{40}    = 0; //Reserved
 829   let Inst{43-41} = DST_SEL_X;
 830   let Inst{46-44} = DST_SEL_Y;
 831   let Inst{49-47} = DST_SEL_Z;
 832   let Inst{52-50} = DST_SEL_W;
 833   let Inst{53}    = USE_CONST_FIELDS;
 834   let Inst{59-54} = DATA_FORMAT;
 835   let Inst{61-60} = NUM_FORMAT_ALL;
 836   let Inst{62}    = FORMAT_COMP_ALL;
 837   let Inst{63}    = SRF_MODE_ALL;
 838 */
 839 }
 840
 841
 842
 843 } // End AMDGPUGen.EG
 844 /* XXX: Need to convert PTR to rat_id */
 845 /*
 846 def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
 847            (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
 848                                                   (f32 R600_Reg32:$value),
 849                                                    sel_x),
 850                                     (f32 ZERO), 0, R600_Reg32:$ptr)>;
 851 */
 852
 853 class VTX_Param_Read_Pattern <ValueType vt> : Pat <
 854     (vt (load_param ADDRParam:$mem)),
 855     (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>;
 856
 857 def : VTX_Param_Read_Pattern <f32>;
 858 def : VTX_Param_Read_Pattern <i32>;
 859
 860 } // End isEG Predicate
 861
 862 /* ------------------------------- */
 863 /* Evergreen / Cayman Instructions */
 864 /* ------------------------------- */
 865
 866 let Predicates = [isEGorCayman] in {
 867
 868 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
 869   (intr R600_Reg32:$src),
 870   (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
 871 >;
 872
 873 let Gen = AMDGPUGen.EG_CAYMAN in {
 874
 875   def MULADD_eg : MULADD_Common<0x14>;
 876   def ASHR_eg : ASHR_Common<0x15>;
 877   def LSHR_eg : LSHR_Common<0x16>;
 878   def LSHL_eg : LSHL_Common<0x17>;
 879   def CNDE_eg : CNDE_Common<0x19>;
 880   def CNDGT_eg : CNDGT_Common<0x1A>;
 881   def CNDGE_eg : CNDGE_Common<0x1B>;
 882   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 883   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>;
 884   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 885   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 886   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 887   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 888   def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 889   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 890   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 891   def SIN_eg : SIN_Common<0x8D>;
 892   def COS_eg : COS_Common<0x8E>;
 893   def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 894   def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 895   def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 896   def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 897   def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 898   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
 899   def DOT4_eg : DOT4_Common<0xBE>;
 900   def CUBE_eg : CUBE_Common<0xC0>;
 901
 902 } // End AMDGPUGen.EG_CAYMAN
 903
 904   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
 905   def LRP_eg : LRP_Common<MULADD_eg>;
 906   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
 907   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
 908   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 909
 910   def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
 911   def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
 912
 913 }
 914
 915 let Predicates = [isCayman] in {
 916
 917 let Gen = AMDGPUGen.CAYMAN in {
 918
 919   /* XXX: I'm not sure if this opcode is correct. */
 920   def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
 921
 922 } // End AMDGPUGen.CAYMAN
 923
 924 } // End isCayman
 925
 926 /* Other Instructions */
 927
 928 let isCodeGenOnly = 1 in {
 929 /*
 930   def SWIZZLE : AMDGPUShaderInst <
 931     (outs GPRV4F32:$dst),
 932     (ins GPRV4F32:$src0, i32imm:$src1),
 933     "SWIZZLE $dst, $src0, $src1",
 934     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
 935   >;
 936 */
 937
 938   def LAST : AMDGPUShaderInst <
 939     (outs),
 940     (ins),
 941     "LAST",
 942     []
 943   >;
 944
 945   def GET_CHAN : AMDGPUShaderInst <
 946     (outs R600_Reg32:$dst),
 947     (ins R600_Reg128:$src0, i32imm:$src1),
 948     "GET_CHAN $dst, $src0, $src1",
 949     []
 950   >;
 951
 952   def MULLIT : AMDGPUShaderInst <
 953     (outs R600_Reg128:$dst),
 954     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
 955     "MULLIT $dst, $src0, $src1",
 956     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 957   >;
 958
 959 let usesCustomInserter = 1, isPseudo = 1 in {
 960
 961 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
 962   (outs R600_TReg32:$dst),
 963   (ins),
 964   asm,
 965   [(set R600_TReg32:$dst, (intr))]
 966 >;
 967
 968 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
 969 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
 970 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
 971
 972 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
 973 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
 974 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
 975
 976 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
 977 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
 978 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
 979
 980 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
 981                                      int_r600_read_global_size_x>;
 982 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
 983                                      int_r600_read_global_size_y>;
 984 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
 985                                      int_r600_read_global_size_z>;
 986
 987 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
 988                                     int_r600_read_local_size_x>;
 989 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
 990                                     int_r600_read_local_size_y>;
 991 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
 992                                     int_r600_read_local_size_z>;
 993
 994 } // End usesCustomInserter = 1, isPseudo = 1
 995
 996 } // End isCodeGenOnly = 1
 997
 998
 999
1000 let isPseudo = 1 in {
1001
1002 def LOAD_VTX : AMDGPUShaderInst <
1003     (outs R600_Reg32:$dst),
1004     (ins MEMri:$mem),
1005     "LOAD_VTX",
1006     [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
1007 >;
1008
1009
1010 } //End isPseudo
1011
1012 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1013 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1014 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1015 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1016
1017 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1018 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1019 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1020 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1021
1022 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1023 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1024 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1025 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1026
1027 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1028 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1029 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1030 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1031
1032
1033 include "R600ShaderPatterns.td"
1034
1035 // We need this pattern to avoid having real registers in PHI nodes.
1036 // For some reason this pattern only works when it comes after the other
1037 // instruction defs.
1038 def : Pat <
1039   (int_R600_load_input imm:$src),
1040   (LOAD_INPUT imm:$src)
1041 >;
1042
1043 } // End isR600toCayman Predicate