1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
26 let Namespace = "AMDIL";
27 let OutOperandList = outs;
28 let InOperandList = ins;
30 let Pattern = pattern;
33 let TSFlags{4} = Trig;
36 // Vector instructions are instructions that must fill all slots in an
38 let TSFlags{6} = isVector;
41 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
42 AMDGPUInst <outs, ins, asm, pattern>
46 let Namespace = "AMDIL";
49 def MEMxi : Operand<iPTR> {
50 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
53 def MEMrr : Operand<iPTR> {
54 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
57 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
58 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
59 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
73 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
74 InstrItinClass itin = AnyALU> :
76 (outs R600_Reg32:$dst),
77 (ins R600_Reg32:$src, variable_ops),
78 !strconcat(opName, " $dst, $src"),
83 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
84 InstrItinClass itin = AnyALU> :
86 (outs R600_Reg32:$dst),
87 (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
88 !strconcat(opName, " $dst, $src0, $src1"),
93 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
94 InstrItinClass itin = AnyALU> :
96 (outs R600_Reg32:$dst),
97 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
98 !strconcat(opName, " $dst, $src0, $src1, $src2"),
105 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
106 InstrItinClass itin = VecALU> :
108 (outs R600_Reg32:$dst),
116 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
117 InstrItinClass itin = AnyALU> :
119 (outs R600_Reg128:$dst),
120 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
121 !strconcat(opName, "$dst, $src0, $src1, $src2"),
126 def TEX_SHADOW : PatLeaf<
128 [{uint32_t TType = (uint32_t)N->getZExtValue();
129 return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
133 def COND_EQ : PatLeaf <
135 [{switch(N->get()){{default: return false;
136 case ISD::SETOEQ: case ISD::SETUEQ:
137 case ISD::SETEQ: return true;}}}]
140 def COND_NE : PatLeaf <
142 [{switch(N->get()){{default: return false;
143 case ISD::SETONE: case ISD::SETUNE:
144 case ISD::SETNE: return true;}}}]
146 def COND_GT : PatLeaf <
148 [{switch(N->get()){{default: return false;
149 case ISD::SETOGT: case ISD::SETUGT:
150 case ISD::SETGT: return true;}}}]
153 def COND_GE : PatLeaf <
155 [{switch(N->get()){{default: return false;
156 case ISD::SETOGE: case ISD::SETUGE:
157 case ISD::SETGE: return true;}}}]
160 def COND_LT : PatLeaf <
162 [{switch(N->get()){{default: return false;
163 case ISD::SETOLT: case ISD::SETULT:
164 case ISD::SETLT: return true;}}}]
167 def COND_LE : PatLeaf <
169 [{switch(N->get()){{default: return false;
170 case ISD::SETOLE: case ISD::SETULE:
171 case ISD::SETLE: return true;}}}]
174 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
175 dag ins, string asm, list<dag> pattern> :
176 InstR600ISA <outs, ins, asm, pattern>
194 /* CF_ALLOC_EXPORT_WORD0_RAT */
195 let Inst{3-0} = rat_id;
196 let Inst{9-4} = rat_inst;
197 let Inst{10} = 0; /* Reserved */
198 let Inst{12-11} = RIM;
199 let Inst{14-13} = TYPE;
200 let Inst{21-15} = RW_GPR;
201 let Inst{22} = RW_REL;
202 let Inst{29-23} = INDEX_GPR;
203 let Inst{31-30} = ELEM_SIZE;
205 /* CF_ALLOC_EXPORT_WORD1_BUF */
206 let Inst{43-32} = ARRAY_SIZE;
207 let Inst{47-44} = COMP_MASK;
208 let Inst{51-48} = BURST_COUNT;
211 let Inst{61-54} = cf_inst;
213 let Inst{63} = BARRIER;
217 def store_global : PatFrag<(ops node:$value, node:$ptr),
218 (store node:$value, node:$ptr),
221 const PointerType *Type;
222 if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
223 PT = dyn_cast<PointerType>(Src->getType()))) {
224 return PT->getAddressSpace() == 1;
231 def load_param : PatFrag<(ops node:$ptr),
234 const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
236 PointerType * PT = dyn_cast<PointerType>(Src->getType());
237 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
242 //class EG_CF <bits<32> inst, string asm> :
243 // InstR600 <inst, (outs), (ins), asm, []>;
245 /* XXX: We will use this when we emit the real ISA.
259 let Inst{23-0} = ADDR;
260 let Inst{26-24} = JTS;
261 let Inst{34-32} = PC;
262 let Inst{39-35} = CF_CONST;
263 let Inst{41-40} = COND;
264 let Inst{47-42} = COUNT;
267 let Inst{61-54} = CF_INST;
272 def isR600 : Predicate<"Subtarget.device()"
273 "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
274 def isR700 : Predicate<"Subtarget.device()"
275 "->getGeneration() == AMDILDeviceInfo::HD4XXX &&"
276 "Subtarget.device()->getDeviceFlag()"
277 ">= OCL_DEVICE_RV710">;
278 def isEG : Predicate<"Subtarget.device()"
279 "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
280 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
281 def isCayman : Predicate<"Subtarget.device()"
282 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
283 def isEGorCayman : Predicate<"Subtarget.device()"
284 "->getGeneration() == AMDILDeviceInfo::HD5XXX"
285 "|| Subtarget.device()->getGeneration() =="
286 "AMDILDeviceInfo::HD6XXX">;
288 def isR600toCayman : Predicate<
289 "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
292 let Predicates = [isR600toCayman] in {
294 /* ------------------------------------------- */
295 /* Common Instructions R600, R700, Evergreen, Cayman */
296 /* ------------------------------------------- */
299 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
302 // Non-IEEE MUL: 0 * anything = 0
305 [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
308 def MUL_IEEE : R600_2OP <
310 [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
315 [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
320 [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
323 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
324 * so some of the instruction names don't match the asm string.
325 * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
328 def SETE : R600_2OP <
330 [(set R600_Reg32:$dst,
331 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
337 [(set R600_Reg32:$dst,
338 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
344 [(set R600_Reg32:$dst,
345 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
351 [(set R600_Reg32:$dst,
352 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
356 def FRACT : R600_1OP <
358 [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
361 def TRUNC : R600_1OP <
363 [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
366 def CEIL : R600_1OP <
368 [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
371 def RNDNE : R600_1OP <
373 [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
376 def FLOOR : R600_1OP <
378 [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
381 def MOV : R600_1OP <0x19, "MOV", []>;
383 class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
384 (outs R600_Reg32:$dst),
385 (ins R600_Reg32:$alu_literal, immType:$imm),
386 "MOV_IMM $dst, $imm",
390 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
393 (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
396 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
399 (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
402 def KILLGT : R600_2OP <
407 def AND_INT : R600_2OP <
409 [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
412 def OR_INT : R600_2OP <
414 [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
417 def XOR_INT : R600_2OP <
419 [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
422 def NOT_INT : R600_1OP <
424 [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
427 def ADD_INT : R600_2OP <
429 [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
432 def SUB_INT : R600_2OP <
434 [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
437 def MAX_INT : R600_2OP <
439 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
441 def MIN_INT : R600_2OP <
443 [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
445 def MAX_UINT : R600_2OP <
447 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
450 def MIN_UINT : R600_2OP <
452 [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
455 def SETE_INT : R600_2OP <
457 [(set (i32 R600_Reg32:$dst),
458 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
461 def SETGT_INT : R600_2OP <
463 [(set (i32 R600_Reg32:$dst),
464 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
467 def SETGE_INT : R600_2OP <
469 [(set (i32 R600_Reg32:$dst),
470 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
473 def SETNE_INT : R600_2OP <
475 [(set (i32 R600_Reg32:$dst),
476 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
479 def SETGT_UINT : R600_2OP <
481 [(set (i32 R600_Reg32:$dst),
482 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
485 def SETGE_UINT : R600_2OP <
487 [(set (i32 R600_Reg32:$dst),
488 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
491 def CNDE_INT : R600_3OP <
493 [(set (i32 R600_Reg32:$dst),
494 (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
497 /* Texture instructions */
500 def TEX_LD : R600_TEX <
502 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
504 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
505 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
508 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
509 0x04, "TEX_GET_TEXTURE_RESINFO",
510 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
513 def TEX_GET_GRADIENTS_H : R600_TEX <
514 0x07, "TEX_GET_GRADIENTS_H",
515 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
518 def TEX_GET_GRADIENTS_V : R600_TEX <
519 0x08, "TEX_GET_GRADIENTS_V",
520 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
523 def TEX_SET_GRADIENTS_H : R600_TEX <
524 0x0B, "TEX_SET_GRADIENTS_H",
528 def TEX_SET_GRADIENTS_V : R600_TEX <
529 0x0C, "TEX_SET_GRADIENTS_V",
533 def TEX_SAMPLE : R600_TEX <
535 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
538 def TEX_SAMPLE_C : R600_TEX <
539 0x18, "TEX_SAMPLE_C",
540 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
543 def TEX_SAMPLE_L : R600_TEX <
544 0x11, "TEX_SAMPLE_L",
545 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
548 def TEX_SAMPLE_C_L : R600_TEX <
549 0x19, "TEX_SAMPLE_C_L",
550 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
553 def TEX_SAMPLE_LB : R600_TEX <
554 0x12, "TEX_SAMPLE_LB",
555 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
558 def TEX_SAMPLE_C_LB : R600_TEX <
559 0x1A, "TEX_SAMPLE_C_LB",
560 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
563 def TEX_SAMPLE_G : R600_TEX <
564 0x14, "TEX_SAMPLE_G",
568 def TEX_SAMPLE_C_G : R600_TEX <
569 0x1C, "TEX_SAMPLE_C_G",
573 /* Helper classes for common instructions */
575 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
580 class MULADD_Common <bits<32> inst> : R600_3OP <
582 [(set (f32 R600_Reg32:$dst),
583 (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
586 class CNDE_Common <bits<32> inst> : R600_3OP <
588 [(set (f32 R600_Reg32:$dst),
589 (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
592 class CNDGT_Common <bits<32> inst> : R600_3OP <
597 class CNDGE_Common <bits<32> inst> : R600_3OP <
599 [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
602 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
604 (ins R600_Reg128:$src0, R600_Reg128:$src1),
605 "DOT4 $dst $src0, $src1",
606 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
609 class CUBE_Common <bits<32> inst> : InstR600 <
611 (outs R600_Reg128:$dst),
612 (ins R600_Reg128:$src),
614 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
618 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
620 [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
623 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
625 [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))]
628 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
630 [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
633 class FLT_TO_UINT_Common <bits<32> inst> : R600_1OP <
635 [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))]
638 class UINT_TO_FLT_Common <bits<32> inst> : R600_1OP <
640 [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))]
643 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
648 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
650 [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
653 class LSHL_Common <bits<32> inst> : R600_2OP <
654 inst, "LSHL $dst, $src0, $src1",
655 [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
658 class LSHR_Common <bits<32> inst> : R600_2OP <
659 inst, "LSHR $dst, $src0, $src1",
660 [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
663 class ASHR_Common <bits<32> inst> : R600_2OP <
664 inst, "ASHR $dst, $src0, $src1",
665 [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
668 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
669 inst, "MULHI_INT $dst, $src0, $src1",
670 [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
673 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
674 inst, "MULHI $dst, $src0, $src1",
675 [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
678 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
679 inst, "MULLO_INT $dst, $src0, $src1",
680 [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
683 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
684 inst, "MULLO_UINT $dst, $src0, $src1",
688 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
689 inst, "RECIP_CLAMPED",
693 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
695 [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
698 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
699 inst, "RECIP_INT $dst, $src",
700 [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))]
703 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
704 inst, "RECIPSQRT_CLAMPED",
705 [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
708 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
709 inst, "RECIPSQRT_IEEE",
713 class SIN_Common <bits<32> inst> : R600_1OP <
718 class COS_Common <bits<32> inst> : R600_1OP <
723 /* Helper patterns for complex intrinsics */
724 /* -------------------------------------- */
726 class DIV_Common <InstR600 recip_ieee> : Pat<
727 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
728 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
731 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
732 (int_AMDGPU_ssg R600_Reg32:$src),
733 (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
736 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
737 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
738 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
741 /* ---------------------- */
742 /* R600 / R700 Only Instructions */
743 /* ---------------------- */
745 let Predicates = [isR600] in {
747 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
748 def MULADD_r600 : MULADD_Common<0x10>;
749 def CNDE_r600 : CNDE_Common<0x18>;
750 def CNDGT_r600 : CNDGT_Common<0x19>;
751 def CNDGE_r600 : CNDGE_Common<0x1A>;
752 def DOT4_r600 : DOT4_Common<0x50>;
753 def CUBE_r600 : CUBE_Common<0x52>;
754 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
755 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
756 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
757 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
758 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
759 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
760 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
761 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
762 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
763 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
764 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
765 def SIN_r600 : SIN_Common<0x6E>;
766 def COS_r600 : COS_Common<0x6F>;
767 def ASHR_r600 : ASHR_Common<0x70>;
768 def LSHR_r600 : LSHR_Common<0x71>;
769 def LSHL_r600 : LSHL_Common<0x72>;
770 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
771 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
772 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
773 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
774 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
776 def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
777 def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
778 def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
779 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
783 // Helper pattern for normalizing inputs to triginomic instructions for R700+
785 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
786 (intr R600_Reg32:$src),
787 (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
790 //===----------------------------------------------------------------------===//
791 // R700 Only instructions
792 //===----------------------------------------------------------------------===//
794 let Predicates = [isR700] in {
795 def SIN_r700 : SIN_Common<0x6E>;
796 def COS_r700 : COS_Common<0x6F>;
798 // R700 normalizes inputs to SIN/COS the same as EG
799 def : TRIG_eg <SIN_r700, int_AMDGPU_sin>;
800 def : TRIG_eg <COS_r700, int_AMDGPU_cos>;
803 //===----------------------------------------------------------------------===//
804 // Evergreen Only instructions
805 //===----------------------------------------------------------------------===//
807 let Predicates = [isEG] in {
809 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
811 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
812 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
813 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
814 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
815 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
817 } // End Predicates = [isEG]
819 /* ------------------------------- */
820 /* Evergreen / Cayman Instructions */
821 /* ------------------------------- */
823 let Predicates = [isEGorCayman] in {
825 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
826 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
831 def MULADD_eg : MULADD_Common<0x14>;
832 def ASHR_eg : ASHR_Common<0x15>;
833 def LSHR_eg : LSHR_Common<0x16>;
834 def LSHL_eg : LSHL_Common<0x17>;
835 def CNDE_eg : CNDE_Common<0x19>;
836 def CNDGT_eg : CNDGT_Common<0x1A>;
837 def CNDGE_eg : CNDGE_Common<0x1B>;
838 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
839 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
840 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
841 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
842 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
843 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
844 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
845 def SIN_eg : SIN_Common<0x8D>;
846 def COS_eg : COS_Common<0x8E>;
847 def DOT4_eg : DOT4_Common<0xBE>;
848 def CUBE_eg : CUBE_Common<0xC0>;
850 def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
851 def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
852 def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
853 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
855 def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
856 def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
858 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
862 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
864 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
868 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
870 def : Pat<(fp_to_sint R600_Reg32:$src),
871 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
873 def : Pat<(fp_to_uint R600_Reg32:$src),
874 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
876 //===----------------------------------------------------------------------===//
877 // Memory read/write instructions
878 //===----------------------------------------------------------------------===//
880 let usesCustomInserter = 1 in {
882 def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
883 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
884 "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr",
885 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]>
888 /* XXX: Have a separate instruction for non-indexed writes. */
902 } // End usesCustomInserter = 1
904 class VTX_READ_eg <int buffer_id, list<dag> pattern> : InstR600ISA <
905 (outs R600_TReg32_X:$dst),
907 "VTX_READ_eg $dst, $ptr",
911 def VTX_READ_PARAM_eg : VTX_READ_eg <0,
912 [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
915 def VTX_READ_GLOBAL_eg : VTX_READ_eg <1,
916 [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
921 let Predicates = [isCayman] in {
923 let isVector = 1 in {
925 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
927 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
928 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
929 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
930 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
932 } // End isVector = 1
934 // RECIP_UINT emulation for Cayman
936 (AMDGPUurecip R600_Reg32:$src0),
937 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
938 (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000)))
943 /* Other Instructions */
945 let isCodeGenOnly = 1 in {
947 def SWIZZLE : AMDGPUShaderInst <
948 (outs GPRV4F32:$dst),
949 (ins GPRV4F32:$src0, i32imm:$src1),
950 "SWIZZLE $dst, $src0, $src1",
951 [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
955 def LAST : AMDGPUShaderInst <
962 def GET_CHAN : AMDGPUShaderInst <
963 (outs R600_Reg32:$dst),
964 (ins R600_Reg128:$src0, i32imm:$src1),
965 "GET_CHAN $dst, $src0, $src1",
969 def MULLIT : AMDGPUShaderInst <
970 (outs R600_Reg128:$dst),
971 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
972 "MULLIT $dst, $src0, $src1",
973 [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
976 let usesCustomInserter = 1, isPseudo = 1 in {
978 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
979 (outs R600_TReg32:$dst),
982 [(set R600_TReg32:$dst, (intr))]
985 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
986 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
987 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
989 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
990 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
991 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
993 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
994 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
995 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
997 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
998 int_r600_read_global_size_x>;
999 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
1000 int_r600_read_global_size_y>;
1001 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
1002 int_r600_read_global_size_z>;
1004 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
1005 int_r600_read_local_size_x>;
1006 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
1007 int_r600_read_local_size_y>;
1008 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
1009 int_r600_read_local_size_z>;
1011 def R600_LOAD_CONST : AMDGPUShaderInst <
1012 (outs R600_Reg32:$dst),
1014 "R600_LOAD_CONST $dst, $src0",
1015 [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1018 def LOAD_INPUT : AMDGPUShaderInst <
1019 (outs R600_Reg32:$dst),
1021 "LOAD_INPUT $dst, $src",
1022 [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1025 def RESERVE_REG : AMDGPUShaderInst <
1029 [(int_AMDGPU_reserve_reg imm:$src)]
1032 def STORE_OUTPUT: AMDGPUShaderInst <
1034 (ins R600_Reg32:$src0, i32imm:$src1),
1035 "STORE_OUTPUT $src0, $src1",
1036 [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1039 def TXD: AMDGPUShaderInst <
1040 (outs R600_Reg128:$dst),
1041 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1042 "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1043 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1046 def TXD_SHADOW: AMDGPUShaderInst <
1047 (outs R600_Reg128:$dst),
1048 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1049 "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1050 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1053 } // End usesCustomInserter = 1, isPseudo = 1
1055 } // End isCodeGenOnly = 1
1057 def CLAMP_R600 : CLAMP <R600_Reg32>;
1058 def FABS_R600 : FABS<R600_Reg32>;
1059 def FNEG_R600 : FNEG<R600_Reg32>;
1061 let usesCustomInserter = 1 in {
1063 def MASK_WRITE : AMDGPUShaderInst <
1065 (ins R600_Reg32:$src),
1070 } // End usesCustomInserter = 1
1072 //===----------------------------------------------------------------------===//
1074 //===----------------------------------------------------------------------===//
1079 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1083 (int_AMDGPU_kill R600_Reg32:$src0),
1084 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
1089 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1090 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1095 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1096 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1099 // SETGT_INT reverse args
1101 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1102 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1105 // SETGE_INT reverse args
1107 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1108 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1111 // SETGT_UINT reverse args
1113 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1114 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1117 // SETGE_UINT reverse args
1119 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1120 (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1123 // The next two patterns are special cases for handling 'true if ordered' and
1124 // 'true if unordered' conditionals. The assumption here is that the behavior of
1125 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1127 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1128 // We assume that SETE returns false when one of the operands is NAN and
1129 // SNE returns true when on of the operands is NAN
1131 //SETE - 'true if ordered'
1133 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1134 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1137 //SNE - 'true if unordered'
1139 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1140 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1143 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1144 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1145 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1146 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1148 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1149 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1150 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1151 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1153 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1154 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1155 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1156 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1158 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1159 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1160 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1161 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1163 def : Vector_Build <v4f32, R600_Reg32>;
1164 def : Vector_Build <v4i32, R600_Reg32>;
1166 // bitconvert patterns
1168 def : BitConvert <i32, f32, R600_Reg32>;
1169 def : BitConvert <f32, i32, R600_Reg32>;
1171 } // End isR600toCayman Predicate