1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
25 let Namespace = "AMDIL";
26 let OutOperandList = outs;
27 let InOperandList = ins;
29 let Pattern = pattern;
32 let TSFlags{4} = Trig;
36 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
37 AMDGPUInst <outs, ins, asm, pattern>
41 let Namespace = "AMDIL";
44 def MEMri : Operand<iPTRAny> {
45 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
48 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
62 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
63 InstrItinClass itin = AnyALU> :
65 (outs R600_Reg32:$dst),
66 (ins R600_Reg32:$src, variable_ops),
67 !strconcat(opName, " $dst, $src"),
72 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
73 InstrItinClass itin = AnyALU> :
75 (outs R600_Reg32:$dst),
76 (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
77 !strconcat(opName, " $dst, $src0, $src1"),
82 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
83 InstrItinClass itin = AnyALU> :
85 (outs R600_Reg32:$dst),
86 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
87 !strconcat(opName, " $dst, $src0, $src1, $src2"),
94 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
95 InstrItinClass itin = VecALU> :
97 (outs R600_Reg32:$dst),
105 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
106 InstrItinClass itin = AnyALU> :
108 (outs R600_Reg128:$dst),
109 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
110 !strconcat(opName, "$dst, $src0, $src1, $src2"),
115 def TEX_SHADOW : PatLeaf<
117 [{uint32_t TType = (uint32_t)N->getZExtValue();
118 return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
122 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
124 InstR600ISA <outs, ins, asm, []>
143 /* CF_ALLOC_EXPORT_WORD0_RAT */
144 let Inst{3-0} = RAT_ID;
145 let Inst{9-4} = rat_inst;
146 let Inst{10} = 0; /* Reserved */
147 let Inst{12-11} = RIM;
148 let Inst{14-13} = TYPE;
149 let Inst{21-15} = RW_GPR;
150 let Inst{22} = RW_REL;
151 let Inst{29-23} = INDEX_GPR;
152 let Inst{31-30} = ELEM_SIZE;
154 /* CF_ALLOC_EXPORT_WORD1_BUF */
155 let Inst{43-32} = ARRAY_SIZE;
156 let Inst{47-44} = COMP_MASK;
157 let Inst{51-48} = BURST_COUNT;
160 let Inst{61-54} = cf_inst;
162 let Inst{63} = BARRIER;
166 def store_global : PatFrag<(ops node:$value, node:$ptr),
167 (store node:$value, node:$ptr),
170 const PointerType *Type;
171 if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
172 PT = dyn_cast<PointerType>(Src->getType()))) {
173 return PT->getAddressSpace() == 1;
180 def load_param : PatFrag<(ops node:$ptr),
184 const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
186 PointerType * PT = dyn_cast<PointerType>(Src->getType());
187 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
192 //class EG_CF <bits<32> inst, string asm> :
193 // InstR600 <inst, (outs), (ins), asm, []>;
195 /* XXX: We will use this when we emit the real ISA.
209 let Inst{23-0} = ADDR;
210 let Inst{26-24} = JTS;
211 let Inst{34-32} = PC;
212 let Inst{39-35} = CF_CONST;
213 let Inst{41-40} = COND;
214 let Inst{47-42} = COUNT;
217 let Inst{61-54} = CF_INST;
222 def isR600 : Predicate<"Subtarget.device()"
223 "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
224 def isEG : Predicate<"Subtarget.device()"
225 "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
226 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
227 def isCayman : Predicate<"Subtarget.device()"
228 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
229 def isEGorCayman : Predicate<"Subtarget.device()"
230 "->getGeneration() == AMDILDeviceInfo::HD5XXX"
231 "|| Subtarget.device()->getGeneration() =="
232 "AMDILDeviceInfo::HD6XXX">;
234 def isR600toCayman : Predicate<
235 "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
238 let Predicates = [isR600toCayman] in {
240 /* ------------------------------------------- */
241 /* Common Instructions R600, R700, Evergreen, Cayman */
242 /* ------------------------------------------- */
243 let Gen = AMDGPUGen.R600_CAYMAN in {
247 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
250 // Non-IEEE MUL: 0 * anything = 0
253 [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
256 def MUL_IEEE : R600_2OP <
258 [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
263 [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
268 [(set R600_Reg32:$dst, (int_AMDIL_min R600_Reg32:$src0, R600_Reg32:$src1))]> {
269 let AMDILOp = AMDILInst.MIN_f32;
272 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
273 * so some of the instruction names don't match the asm string.
274 * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
277 def SETE : R600_2OP <
279 [(set R600_Reg32:$dst, (int_AMDGPU_seq R600_Reg32:$src0, R600_Reg32:$src1))]> {
280 let AMDILOp = AMDILInst.FEQ;
285 [(set R600_Reg32:$dst, (int_AMDGPU_sgt R600_Reg32:$src0, R600_Reg32:$src1))]
290 [(set R600_Reg32:$dst, (int_AMDGPU_sge R600_Reg32:$src0, R600_Reg32:$src1))]> {
291 let AMDILOp = AMDILInst.FGE;
296 [(set R600_Reg32:$dst, (int_AMDGPU_sne R600_Reg32:$src0, R600_Reg32:$src1))]> {
297 let AMDILOp = AMDILInst.FNE;
300 def FRACT : R600_1OP <
303 let AMDILOp = AMDILInst.FRAC_f32;
306 def TRUNC : R600_1OP <
308 [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
311 def CEIL : R600_1OP <
313 [(set R600_Reg32:$dst, (int_AMDIL_round_posinf R600_Reg32:$src))]> {
314 let AMDILOp = AMDILInst.ROUND_POSINF_f32;
317 def RNDNE : R600_1OP <
319 [(set R600_Reg32:$dst, (int_AMDIL_round_nearest R600_Reg32:$src))]> {
320 let AMDILOp = AMDILInst.ROUND_NEAREST_f32;
323 def FLOOR : R600_1OP <
325 [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
328 def MOV : R600_1OP <0x19, "MOV", []>;
330 def KILLGT : R600_2OP <
335 def AND_INT : R600_2OP <
338 let AMDILOp = AMDILInst.AND_i32;
341 def OR_INT : R600_2OP <
344 let AMDILOp = AMDILInst.BINARY_OR_i32;
347 def XOR_INT : R600_2OP <
352 def NOT_INT : R600_1OP <
355 let AMDILOp = AMDILInst.BINARY_NOT_i32;
358 def ADD_INT : R600_2OP <
361 let AMDILOp = AMDILInst.ADD_i32;
364 def SUB_INT : R600_2OP <
366 [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
369 def MAX_INT : R600_2OP <
371 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
373 def MIN_INT : R600_2OP <
375 [(set R600_Reg32:$dst, (int_AMDGPU_imin R600_Reg32:$src0, R600_Reg32:$src1))]>;
377 def MAX_UINT : R600_2OP <
379 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
381 def MIN_UINT : R600_2OP <
383 [(set R600_Reg32:$dst, (int_AMDGPU_umin R600_Reg32:$src0, R600_Reg32:$src1))]>;
386 def SETE_INT : R600_2OP <
389 let AMDILOp = AMDILInst.IEQ;
392 def SETGT_INT : R600_2OP <
397 def SETGE_INT : R600_2OP <
400 let AMDILOp = AMDILInst.IGE;
403 def SETNE_INT : R600_2OP <
406 let AMDILOp = AMDILInst.INE;
409 def SETGT_UINT : R600_2OP <
412 let AMDILOp = AMDILInst.UGT;
415 def SETGE_UINT : R600_2OP <
418 let AMDILOp = AMDILInst.UGE;
421 def CNDE_INT : R600_3OP <
423 [(set (i32 R600_Reg32:$dst),
424 (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
427 /* Texture instructions */
430 def TEX_LD : R600_TEX <
432 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
434 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
435 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
438 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
439 0x04, "TEX_GET_TEXTURE_RESINFO",
440 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
443 def TEX_GET_GRADIENTS_H : R600_TEX <
444 0x07, "TEX_GET_GRADIENTS_H",
445 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
448 def TEX_GET_GRADIENTS_V : R600_TEX <
449 0x08, "TEX_GET_GRADIENTS_V",
450 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
453 def TEX_SET_GRADIENTS_H : R600_TEX <
454 0x0B, "TEX_SET_GRADIENTS_H",
458 def TEX_SET_GRADIENTS_V : R600_TEX <
459 0x0C, "TEX_SET_GRADIENTS_V",
463 def TEX_SAMPLE : R600_TEX <
465 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
468 def TEX_SAMPLE_C : R600_TEX <
469 0x18, "TEX_SAMPLE_C",
470 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
473 def TEX_SAMPLE_L : R600_TEX <
474 0x11, "TEX_SAMPLE_L",
475 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
478 def TEX_SAMPLE_C_L : R600_TEX <
479 0x19, "TEX_SAMPLE_C_L",
480 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
483 def TEX_SAMPLE_LB : R600_TEX <
484 0x12, "TEX_SAMPLE_LB",
485 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
488 def TEX_SAMPLE_C_LB : R600_TEX <
489 0x1A, "TEX_SAMPLE_C_LB",
490 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
493 def TEX_SAMPLE_G : R600_TEX <
494 0x14, "TEX_SAMPLE_G",
498 def TEX_SAMPLE_C_G : R600_TEX <
499 0x1C, "TEX_SAMPLE_C_G",
503 } // End Gen R600_CAYMAN
507 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
511 (int_AMDGPU_kill R600_Reg32:$src0),
512 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
515 /* Helper classes for common instructions */
517 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
522 class MULADD_Common <bits<32> inst> : R600_3OP <
525 let AMDILOp = AMDILInst.MAD_f32;
528 class CNDE_Common <bits<32> inst> : R600_3OP <
530 [(set (f32 R600_Reg32:$dst),
531 (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
534 class CNDGT_Common <bits<32> inst> : R600_3OP <
539 class CNDGE_Common <bits<32> inst> : R600_3OP <
541 [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
544 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
546 (ins R600_Reg128:$src0, R600_Reg128:$src1),
547 "DOT4 $dst $src0, $src1",
548 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
551 class CUBE_Common <bits<32> inst> : InstR600 <
553 (outs R600_Reg128:$dst),
554 (ins R600_Reg128:$src),
556 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
560 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
563 let AMDILOp = AMDILInst.EXP_f32;
566 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
567 inst, "FLT_TO_INT", []> {
568 let AMDILOp = AMDILInst.FTOI;
571 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
572 inst, "INT_TO_FLT", []> {
573 let AMDILOp = AMDILInst.ITOF;
576 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
581 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
584 let AMDILOp = AMDILInst.LOG_f32;
587 class LSHL_Common <bits<32> inst> : R600_2OP <
588 inst, "LSHL $dst, $src0, $src1",
590 let AMDILOp = AMDILInst.SHL_i32;
593 class LSHR_Common <bits<32> inst> : R600_2OP <
594 inst, "LSHR $dst, $src0, $src1",
596 let AMDILOp = AMDILInst.USHR_i32;
599 class ASHR_Common <bits<32> inst> : R600_2OP <
600 inst, "ASHR $dst, $src0, $src1",
602 let AMDILOp = AMDILInst.SHR_i32;
605 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
606 inst, "MULHI_INT $dst, $src0, $src1",
608 let AMDILOp = AMDILInst.SMULHI_i32;
611 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
612 inst, "MULHI $dst, $src0, $src1",
616 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
617 inst, "MULLO_INT $dst, $src0, $src1",
619 let AMDILOp = AMDILInst.SMUL_i32;
622 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
623 inst, "MULLO_UINT $dst, $src0, $src1",
627 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
628 inst, "RECIP_CLAMPED",
632 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
634 [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
635 let AMDILOp = AMDILInst.RSQ_f32;
638 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
639 inst, "RECIP_INT $dst, $src",
643 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
644 inst, "RECIPSQRT_CLAMPED",
645 [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
648 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
649 inst, "RECIPSQRT_IEEE",
653 class SIN_Common <bits<32> inst> : R600_1OP <
656 let AMDILOp = AMDILInst.SIN_f32;
660 class COS_Common <bits<32> inst> : R600_1OP <
663 let AMDILOp = AMDILInst.COS_f32;
667 /* Helper patterns for complex intrinsics */
668 /* -------------------------------------- */
670 class DIV_Common <InstR600 recip_ieee> : Pat<
671 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
672 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
675 class LRP_Common <InstR600 muladd> : Pat <
676 (int_AMDGPU_lrp R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
677 (muladd R600_Reg32:$src0, R600_Reg32:$src1, (MUL (SUB_f32 ONE, R600_Reg32:$src0), R600_Reg32:$src2))
680 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
681 (int_AMDGPU_ssg R600_Reg32:$src),
682 (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
685 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
686 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
687 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
690 /* ---------------------- */
691 /* R600 / R700 Only Instructions */
692 /* ---------------------- */
694 let Predicates = [isR600] in {
696 let Gen = AMDGPUGen.R600 in {
698 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
699 def MULADD_r600 : MULADD_Common<0x10>;
700 def CNDE_r600 : CNDE_Common<0x18>;
701 def CNDGT_r600 : CNDGT_Common<0x19>;
702 def CNDGE_r600 : CNDGE_Common<0x1A>;
703 def DOT4_r600 : DOT4_Common<0x50>;
704 def CUBE_r600 : CUBE_Common<0x52>;
705 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
706 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
707 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
708 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
709 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
710 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
711 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
712 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
713 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
714 def SIN_r600 : SIN_Common<0x6E>;
715 def COS_r600 : COS_Common<0x6F>;
716 def ASHR_r600 : ASHR_Common<0x70>;
717 def LSHR_r600 : LSHR_Common<0x71>;
718 def LSHL_r600 : LSHL_Common<0x72>;
719 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
720 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
721 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
722 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
723 def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
725 } // End AMDGPUGen.R600
727 def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
728 def LRP_r600 : LRP_Common<MULADD_r600>;
729 def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
730 def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
731 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
735 /* ----------------- */
736 /* R700+ Trig helper */
737 /* ----------------- */
740 class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
741 (trig_inst R600_Reg32:$src),
742 (trig_inst (fmul R600_Reg32:$src, (PI))))
746 /* ---------------------- */
747 /* Evergreen Instructions */
748 /* ---------------------- */
751 let Predicates = [isEG] in {
753 let Gen = AMDGPUGen.EG in {
755 def RAT_WRITE_CACHELESS_eg :
756 EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
757 R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
760 /* XXX: Have a separate instruction for non-indexed writes. */
774 def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
775 (ins R600_TReg32_X:$src, i32imm:$buffer_id),
776 "VTX_READ_eg $dst, $src", []>
783 /* If any of these field below need to be calculated at compile time, and
784 * a ins operand for them and move them to the list of operands above. */
786 /* XXX: This instruction is manual encoded, so none of these values are used.
789 bits<5> VC_INST = 0; //VC_INST_FETCH
790 bits<2> FETCH_TYPE = 2;
791 bits<1> FETCH_WHOLE_QUAD = 1;
793 bits<2> SRC_SEL_X = 0;
794 bits<6> MEGA_FETCH_COUNT = 4;
799 bits<3> DST_SEL_X = 0;
800 bits<3> DST_SEL_Y = 7; //Masked
801 bits<3> DST_SEL_Z = 7; //Masked
802 bits<3> DST_SEL_W = 7; //Masked
803 bits<1> USE_CONST_FIELDS = 1; //Masked
804 bits<6> DATA_FORMAT = 0;
805 bits<2> NUM_FORMAT_ALL = 0;
806 bits<1> FORMAT_COMP_ALL = 0;
807 bits<1> SRF_MODE_ALL = 0;
811 let Inst{4-0} = VC_INST;
812 let Inst{6-5} = FETCH_TYPE;
813 let Inst{7} = FETCH_WHOLE_QUAD;
814 let Inst{15-8} = BUFFER_ID;
815 let Inst{22-16} = SRC_GPR;
816 let Inst{23} = SRC_REL;
817 let Inst{25-24} = SRC_SEL_X;
818 let Inst{31-26} = MEGA_FETCH_COUNT;
820 /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you
821 * from statically setting bits > 31. This field will be set by
822 * getMachineValueOp which can set bits > 31.
824 // let Inst{32-38} = DST_GPR;
826 /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */
829 let Inst{39} = DST_REL;
830 let Inst{40} = 0; //Reserved
831 let Inst{43-41} = DST_SEL_X;
832 let Inst{46-44} = DST_SEL_Y;
833 let Inst{49-47} = DST_SEL_Z;
834 let Inst{52-50} = DST_SEL_W;
835 let Inst{53} = USE_CONST_FIELDS;
836 let Inst{59-54} = DATA_FORMAT;
837 let Inst{61-60} = NUM_FORMAT_ALL;
838 let Inst{62} = FORMAT_COMP_ALL;
839 let Inst{63} = SRF_MODE_ALL;
845 } // End AMDGPUGen.EG
846 /* XXX: Need to convert PTR to rat_id */
848 def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
849 (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
850 (f32 R600_Reg32:$value),
852 (f32 ZERO), 0, R600_Reg32:$ptr)>;
855 class VTX_Param_Read_Pattern <ValueType vt> : Pat <
856 (vt (load_param ADDRParam:$mem)),
857 (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>;
859 def : VTX_Param_Read_Pattern <f32>;
860 def : VTX_Param_Read_Pattern <i32>;
862 } // End isEG Predicate
864 /* ------------------------------- */
865 /* Evergreen / Cayman Instructions */
866 /* ------------------------------- */
868 let Predicates = [isEGorCayman] in {
870 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
871 (intr R600_Reg32:$src),
872 (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
875 let Gen = AMDGPUGen.EG_CAYMAN in {
877 def MULADD_eg : MULADD_Common<0x14>;
878 def ASHR_eg : ASHR_Common<0x15>;
879 def LSHR_eg : LSHR_Common<0x16>;
880 def LSHL_eg : LSHL_Common<0x17>;
881 def CNDE_eg : CNDE_Common<0x19>;
882 def CNDGT_eg : CNDGT_Common<0x1A>;
883 def CNDGE_eg : CNDGE_Common<0x1B>;
884 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
885 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>;
886 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
887 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
888 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
889 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
890 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
891 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
892 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
893 def SIN_eg : SIN_Common<0x8D>;
894 def COS_eg : COS_Common<0x8E>;
895 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
896 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
897 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
898 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
899 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
900 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
901 def DOT4_eg : DOT4_Common<0xBE>;
902 def CUBE_eg : CUBE_Common<0xC0>;
904 } // End AMDGPUGen.EG_CAYMAN
906 def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
907 def LRP_eg : LRP_Common<MULADD_eg>;
908 def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
909 def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
910 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
912 def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
913 def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
917 let Predicates = [isCayman] in {
919 let Gen = AMDGPUGen.CAYMAN in {
921 /* XXX: I'm not sure if this opcode is correct. */
922 def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
924 } // End AMDGPUGen.CAYMAN
928 /* Other Instructions */
930 let isCodeGenOnly = 1 in {
932 def SWIZZLE : AMDGPUShaderInst <
933 (outs GPRV4F32:$dst),
934 (ins GPRV4F32:$src0, i32imm:$src1),
935 "SWIZZLE $dst, $src0, $src1",
936 [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
940 def LAST : AMDGPUShaderInst <
947 def GET_CHAN : AMDGPUShaderInst <
948 (outs R600_Reg32:$dst),
949 (ins R600_Reg128:$src0, i32imm:$src1),
950 "GET_CHAN $dst, $src0, $src1",
954 def MULLIT : AMDGPUShaderInst <
955 (outs R600_Reg128:$dst),
956 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
957 "MULLIT $dst, $src0, $src1",
958 [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
961 let usesCustomInserter = 1, isPseudo = 1 in {
963 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
964 (outs R600_TReg32:$dst),
967 [(set R600_TReg32:$dst, (intr))]
970 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
971 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
972 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
974 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
975 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
976 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
978 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
979 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
980 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
982 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
983 int_r600_read_global_size_x>;
984 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
985 int_r600_read_global_size_y>;
986 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
987 int_r600_read_global_size_z>;
989 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
990 int_r600_read_local_size_x>;
991 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
992 int_r600_read_local_size_y>;
993 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
994 int_r600_read_local_size_z>;
996 def R600_LOAD_CONST : AMDGPUShaderInst <
997 (outs R600_Reg32:$dst),
999 "R600_LOAD_CONST $dst, $src0",
1000 [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1003 def LOAD_INPUT : AMDGPUShaderInst <
1004 (outs R600_Reg32:$dst),
1006 "LOAD_INPUT $dst, $src",
1007 [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1010 def RESERVE_REG : AMDGPUShaderInst <
1014 [(int_AMDGPU_reserve_reg imm:$src)]
1017 def STORE_OUTPUT: AMDGPUShaderInst <
1019 (ins R600_Reg32:$src0, i32imm:$src1),
1020 "STORE_OUTPUT $src0, $src1",
1021 [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1024 def TXD: AMDGPUShaderInst <
1025 (outs R600_Reg128:$dst),
1026 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1027 "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1028 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1031 def TXD_SHADOW: AMDGPUShaderInst <
1032 (outs R600_Reg128:$dst),
1033 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1034 "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1035 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1038 } // End usesCustomInserter = 1, isPseudo = 1
1040 } // End isCodeGenOnly = 1
1044 let isPseudo = 1 in {
1046 def LOAD_VTX : AMDGPUShaderInst <
1047 (outs R600_Reg32:$dst),
1050 [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
1056 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1057 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1058 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1059 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1061 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1062 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1063 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1064 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1066 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1067 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1068 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1069 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1071 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1072 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1073 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1074 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1076 } // End isR600toCayman Predicate