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[mesa.git] / src / gallium / drivers / radeon / R600Instructions.td
1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // R600 Tablegen instruction definitions
11 //
12 //===----------------------------------------------------------------------===//
13
14 include "R600Intrinsics.td"
15
16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
17 InstrItinClass itin>
18 : AMDGPUInst <outs, ins, asm, pattern> {
19
20 field bits<32> Inst;
21 bit Trig = 0;
22 bit Op3 = 0;
23
24 let Inst = inst;
25 let Namespace = "AMDIL";
26 let OutOperandList = outs;
27 let InOperandList = ins;
28 let AsmString = asm;
29 let Pattern = pattern;
30 let Itinerary = itin;
31
32 let TSFlags{4} = Trig;
33 let TSFlags{5} = Op3;
34 }
35
36 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
37 AMDGPUInst <outs, ins, asm, pattern>
38 {
39 field bits<64> Inst;
40
41 let Namespace = "AMDIL";
42 }
43
44 def MEMri : Operand<iPTRAny> {
45 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
46 }
47
48 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
49
50 class R600_ALU {
51
52 bits<7> DST_GPR = 0;
53 bits<9> SRC0_SEL = 0;
54 bits<1> SRC0_NEG = 0;
55 bits<9> SRC1_SEL = 0;
56 bits<1> SRC1_NEG = 0;
57 bits<1> CLAMP = 0;
58
59 }
60
61
62 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
63 InstrItinClass itin = AnyALU> :
64 InstR600 <inst,
65 (outs R600_Reg32:$dst),
66 (ins R600_Reg32:$src, variable_ops),
67 !strconcat(opName, " $dst, $src"),
68 pattern,
69 itin
70 >;
71
72 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
73 InstrItinClass itin = AnyALU> :
74 InstR600 <inst,
75 (outs R600_Reg32:$dst),
76 (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
77 !strconcat(opName, " $dst, $src0, $src1"),
78 pattern,
79 itin
80 >;
81
82 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
83 InstrItinClass itin = AnyALU> :
84 InstR600 <inst,
85 (outs R600_Reg32:$dst),
86 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
87 !strconcat(opName, " $dst, $src0, $src1, $src2"),
88 pattern,
89 itin>{
90
91 let Op3 = 1;
92 }
93
94 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
95 InstrItinClass itin = VecALU> :
96 InstR600 <inst,
97 (outs R600_Reg32:$dst),
98 ins,
99 asm,
100 pattern,
101 itin
102
103 >;
104
105 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
106 InstrItinClass itin = AnyALU> :
107 InstR600 <inst,
108 (outs R600_Reg128:$dst),
109 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
110 !strconcat(opName, "$dst, $src0, $src1, $src2"),
111 pattern,
112 itin
113 >;
114
115 def TEX_SHADOW : PatLeaf<
116 (imm),
117 [{uint32_t TType = (uint32_t)N->getZExtValue();
118 return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
119 }]
120 >;
121
122 def FP_ZERO : PatLeaf <
123 (fpimm),
124 [{return N->getValueAPF().isZero();}]
125 >;
126
127 def FP_ONE : PatLeaf <
128 (fpimm),
129 [{return N->isExactlyValue(1.0);}]
130 >;
131
132 def COND_EQ : PatLeaf <
133 (cond),
134 [{switch(N->get()){{default: return false;
135 case ISD::SETOEQ: case ISD::SETUEQ:
136 case ISD::SETEQ: return true;}}}]
137 >;
138
139 def COND_NE : PatLeaf <
140 (cond),
141 [{switch(N->get()){{default: return false;
142 case ISD::SETONE: case ISD::SETUNE:
143 case ISD::SETNE: return true;}}}]
144 >;
145 def COND_GT : PatLeaf <
146 (cond),
147 [{switch(N->get()){{default: return false;
148 case ISD::SETOGT: case ISD::SETUGT:
149 case ISD::SETGT: return true;}}}]
150 >;
151
152 def COND_GE : PatLeaf <
153 (cond),
154 [{switch(N->get()){{default: return false;
155 case ISD::SETOGE: case ISD::SETUGE:
156 case ISD::SETGE: return true;}}}]
157 >;
158
159 def COND_LT : PatLeaf <
160 (cond),
161 [{switch(N->get()){{default: return false;
162 case ISD::SETOLT: case ISD::SETULT:
163 case ISD::SETLT: return true;}}}]
164 >;
165
166 def COND_LE : PatLeaf <
167 (cond),
168 [{switch(N->get()){{default: return false;
169 case ISD::SETOLE: case ISD::SETULE:
170 case ISD::SETLE: return true;}}}]
171 >;
172
173 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
174 string asm> :
175 InstR600ISA <outs, ins, asm, []>
176 {
177 bits<7> RW_GPR;
178 bits<7> INDEX_GPR;
179 bits<4> RAT_ID;
180
181 bits<2> RIM;
182 bits<2> TYPE;
183 bits<1> RW_REL;
184 bits<2> ELEM_SIZE;
185
186 bits<12> ARRAY_SIZE;
187 bits<4> COMP_MASK;
188 bits<4> BURST_COUNT;
189 bits<1> VPM;
190 bits<1> EOP;
191 bits<1> MARK;
192 bits<1> BARRIER;
193
194 /* CF_ALLOC_EXPORT_WORD0_RAT */
195 let Inst{3-0} = RAT_ID;
196 let Inst{9-4} = rat_inst;
197 let Inst{10} = 0; /* Reserved */
198 let Inst{12-11} = RIM;
199 let Inst{14-13} = TYPE;
200 let Inst{21-15} = RW_GPR;
201 let Inst{22} = RW_REL;
202 let Inst{29-23} = INDEX_GPR;
203 let Inst{31-30} = ELEM_SIZE;
204
205 /* CF_ALLOC_EXPORT_WORD1_BUF */
206 let Inst{43-32} = ARRAY_SIZE;
207 let Inst{47-44} = COMP_MASK;
208 let Inst{51-48} = BURST_COUNT;
209 let Inst{52} = VPM;
210 let Inst{53} = EOP;
211 let Inst{61-54} = cf_inst;
212 let Inst{62} = MARK;
213 let Inst{63} = BARRIER;
214 }
215
216 /*
217 def store_global : PatFrag<(ops node:$value, node:$ptr),
218 (store node:$value, node:$ptr),
219 [{
220 const Value *Src;
221 const PointerType *Type;
222 if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
223 PT = dyn_cast<PointerType>(Src->getType()))) {
224 return PT->getAddressSpace() == 1;
225 }
226 return false;
227 }]>;
228
229 */
230
231 def load_param : PatFrag<(ops node:$ptr),
232 (load node:$ptr),
233 [{
234 return true;
235 const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
236 if (Src) {
237 PointerType * PT = dyn_cast<PointerType>(Src->getType());
238 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
239 }
240 return false;
241 }]>;
242
243 //class EG_CF <bits<32> inst, string asm> :
244 // InstR600 <inst, (outs), (ins), asm, []>;
245
246 /* XXX: We will use this when we emit the real ISA.
247 bits<24> ADDR = 0;
248 bits<3> JTS = 0;
249
250 bits<3> PC = 0;
251 bits<5> CF_CONS = 0;
252 bits<2> COND = 0;
253 bits<6> COUNT = 0;
254 bits<1> VPM = 0;
255 bits<1> EOP = 0;
256 bits<8> CF_INST = 0;
257 bits<1> WQM = 0;
258 bits<1> B = 0;
259
260 let Inst{23-0} = ADDR;
261 let Inst{26-24} = JTS;
262 let Inst{34-32} = PC;
263 let Inst{39-35} = CF_CONST;
264 let Inst{41-40} = COND;
265 let Inst{47-42} = COUNT;
266 let Inst{52} = VPM;
267 let Inst{53} = EOP;
268 let Inst{61-54} = CF_INST;
269 let Inst{62} = WQM;
270 let Inst{63} = B;
271 //}
272 */
273 def isR600 : Predicate<"Subtarget.device()"
274 "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
275 def isEG : Predicate<"Subtarget.device()"
276 "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
277 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
278 def isCayman : Predicate<"Subtarget.device()"
279 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
280 def isEGorCayman : Predicate<"Subtarget.device()"
281 "->getGeneration() == AMDILDeviceInfo::HD5XXX"
282 "|| Subtarget.device()->getGeneration() =="
283 "AMDILDeviceInfo::HD6XXX">;
284
285 def isR600toCayman : Predicate<
286 "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
287
288
289 let Predicates = [isR600toCayman] in {
290
291 /* ------------------------------------------- */
292 /* Common Instructions R600, R700, Evergreen, Cayman */
293 /* ------------------------------------------- */
294 let Gen = AMDGPUGen.R600_CAYMAN in {
295
296 def ADD : R600_2OP <
297 0x0, "ADD",
298 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
299 >;
300
301 // Non-IEEE MUL: 0 * anything = 0
302 def MUL : R600_2OP <
303 0x1, "MUL NON-IEEE",
304 [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
305 >;
306
307 def MUL_IEEE : R600_2OP <
308 0x2, "MUL_IEEE",
309 [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
310 >;
311
312 def MAX : R600_2OP <
313 0x3, "MAX",
314 [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
315 >;
316
317 def MIN : R600_2OP <
318 0x4, "MIN",
319 [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
320 >;
321
322 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
323 * so some of the instruction names don't match the asm string.
324 * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
325 */
326
327 def SETE : R600_2OP <
328 0x08, "SETE",
329 [(set R600_Reg32:$dst,
330 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
331 COND_EQ))]
332 >;
333 //let AMDILOp = AMDILInst.FEQ;
334
335 def SGT : R600_2OP <
336 0x09, "SETGT",
337 [(set R600_Reg32:$dst,
338 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
339 COND_GT))]
340 >;
341
342 def SGE : R600_2OP <
343 0xA, "SETGE",
344 [(set R600_Reg32:$dst,
345 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
346 COND_GE))]
347 >;
348 //let AMDILOp = AMDILInst.FGE;
349
350 def SNE : R600_2OP <
351 0xB, "SETNE",
352 [(set R600_Reg32:$dst,
353 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
354 COND_NE))]
355 >;
356
357 // let AMDILOp = AMDILInst.FNE;
358
359 def FRACT : R600_1OP <
360 0x10, "FRACT",
361 [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
362 >;
363
364 def TRUNC : R600_1OP <
365 0x11, "TRUNC",
366 [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
367 >;
368
369 def CEIL : R600_1OP <
370 0x12, "CEIL",
371 [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
372 >;
373
374 def RNDNE : R600_1OP <
375 0x13, "RNDNE",
376 [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
377 >;
378
379 def FLOOR : R600_1OP <
380 0x14, "FLOOR",
381 [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
382 >;
383
384 def MOV : R600_1OP <0x19, "MOV", []>;
385
386 def KILLGT : R600_2OP <
387 0x2D, "KILLGT",
388 []
389 >;
390
391 def AND_INT : R600_2OP <
392 0x30, "AND_INT",
393 [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
394 >;
395
396 def OR_INT : R600_2OP <
397 0x31, "OR_INT",
398 [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
399 >;
400
401 def XOR_INT : R600_2OP <
402 0x32, "XOR_INT",
403 [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
404 >;
405
406 def NOT_INT : R600_1OP <
407 0x33, "NOT_INT",
408 [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
409 >;
410
411 def ADD_INT : R600_2OP <
412 0x34, "ADD_INT",
413 [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
414 >;
415
416 def SUB_INT : R600_2OP <
417 0x35, "SUB_INT",
418 [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
419 >;
420
421 def MAX_INT : R600_2OP <
422 0x36, "MAX_INT",
423 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
424
425 def MIN_INT : R600_2OP <
426 0x37, "MIN_INT",
427 [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
428
429 def MAX_UINT : R600_2OP <
430 0x38, "MAX_UINT",
431 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
432 >;
433
434 def MIN_UINT : R600_2OP <
435 0x39, "MIN_UINT",
436 [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
437 >;
438
439 def SETE_INT : R600_2OP <
440 0x3A, "SETE_INT",
441 [(set (i32 R600_Reg32:$dst),
442 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
443 >;
444
445 // let AMDILOp = AMDILInst.IEQ;
446
447 def SETGT_INT : R600_2OP <
448 0x3B, "SGT_INT",
449 [(set (i32 R600_Reg32:$dst),
450 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
451 >;
452
453 def SETGE_INT : R600_2OP <
454 0x3C, "SETGE_INT",
455 [(set (i32 R600_Reg32:$dst),
456 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
457 >;
458 // let AMDILOp = AMDILInst.IGE;
459
460
461 def SETNE_INT : R600_2OP <
462 0x3D, "SETNE_INT",
463 [(set (i32 R600_Reg32:$dst),
464 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
465 >;
466 //let AMDILOp = AMDILInst.INE;
467
468
469 def SETGT_UINT : R600_2OP <
470 0x3E, "SETGT_UINT",
471 [(set (i32 R600_Reg32:$dst),
472 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
473 >;
474
475 // let AMDILOp = AMDILInst.UGT;
476
477 def SETGE_UINT : R600_2OP <
478 0x3F, "SETGE_UINT",
479 [(set (i32 R600_Reg32:$dst),
480 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
481 >;
482 // let AMDILOp = AMDILInst.UGE;
483
484 def CNDE_INT : R600_3OP <
485 0x1C, "CNDE_INT",
486 [(set (i32 R600_Reg32:$dst),
487 (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
488 >;
489
490 /* Texture instructions */
491
492
493 def TEX_LD : R600_TEX <
494 0x03, "TEX_LD",
495 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
496 > {
497 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
498 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
499 }
500
501 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
502 0x04, "TEX_GET_TEXTURE_RESINFO",
503 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
504 >;
505
506 def TEX_GET_GRADIENTS_H : R600_TEX <
507 0x07, "TEX_GET_GRADIENTS_H",
508 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
509 >;
510
511 def TEX_GET_GRADIENTS_V : R600_TEX <
512 0x08, "TEX_GET_GRADIENTS_V",
513 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
514 >;
515
516 def TEX_SET_GRADIENTS_H : R600_TEX <
517 0x0B, "TEX_SET_GRADIENTS_H",
518 []
519 >;
520
521 def TEX_SET_GRADIENTS_V : R600_TEX <
522 0x0C, "TEX_SET_GRADIENTS_V",
523 []
524 >;
525
526 def TEX_SAMPLE : R600_TEX <
527 0x10, "TEX_SAMPLE",
528 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
529 >;
530
531 def TEX_SAMPLE_C : R600_TEX <
532 0x18, "TEX_SAMPLE_C",
533 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
534 >;
535
536 def TEX_SAMPLE_L : R600_TEX <
537 0x11, "TEX_SAMPLE_L",
538 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
539 >;
540
541 def TEX_SAMPLE_C_L : R600_TEX <
542 0x19, "TEX_SAMPLE_C_L",
543 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
544 >;
545
546 def TEX_SAMPLE_LB : R600_TEX <
547 0x12, "TEX_SAMPLE_LB",
548 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
549 >;
550
551 def TEX_SAMPLE_C_LB : R600_TEX <
552 0x1A, "TEX_SAMPLE_C_LB",
553 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
554 >;
555
556 def TEX_SAMPLE_G : R600_TEX <
557 0x14, "TEX_SAMPLE_G",
558 []
559 >;
560
561 def TEX_SAMPLE_C_G : R600_TEX <
562 0x1C, "TEX_SAMPLE_C_G",
563 []
564 >;
565
566 } // End Gen R600_CAYMAN
567
568 def KILP : Pat <
569 (int_AMDGPU_kilp),
570 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
571 >;
572
573 def KIL : Pat <
574 (int_AMDGPU_kill R600_Reg32:$src0),
575 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
576 >;
577
578 /* Helper classes for common instructions */
579
580 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
581 inst, "MUL_LIT",
582 []
583 >;
584
585 class MULADD_Common <bits<32> inst> : R600_3OP <
586 inst, "MULADD",
587 [(set (f32 R600_Reg32:$dst),
588 (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
589 >;
590
591 class CNDE_Common <bits<32> inst> : R600_3OP <
592 inst, "CNDE",
593 [(set (f32 R600_Reg32:$dst),
594 (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
595 >;
596
597 class CNDGT_Common <bits<32> inst> : R600_3OP <
598 inst, "CNDGT",
599 []
600 >;
601
602 class CNDGE_Common <bits<32> inst> : R600_3OP <
603 inst, "CNDGE",
604 [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
605 >;
606
607 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
608 inst,
609 (ins R600_Reg128:$src0, R600_Reg128:$src1),
610 "DOT4 $dst $src0, $src1",
611 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
612 >;
613
614 class CUBE_Common <bits<32> inst> : InstR600 <
615 inst,
616 (outs R600_Reg128:$dst),
617 (ins R600_Reg128:$src),
618 "CUBE $dst $src",
619 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
620 VecALU
621 >;
622
623 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
624 inst, "EXP_IEEE",
625 [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
626 >;
627
628 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
629 inst, "FLT_TO_INT",
630 [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))]
631 >;
632
633 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
634 inst, "INT_TO_FLT",
635 [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
636 >;
637
638 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
639 inst, "LOG_CLAMPED",
640 []
641 >;
642
643 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
644 inst, "LOG_IEEE",
645 []> {
646 let AMDILOp = AMDILInst.LOG_f32;
647 }
648
649 class LSHL_Common <bits<32> inst> : R600_2OP <
650 inst, "LSHL $dst, $src0, $src1",
651 [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
652 >;
653
654 class LSHR_Common <bits<32> inst> : R600_2OP <
655 inst, "LSHR $dst, $src0, $src1",
656 [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
657 >;
658
659 class ASHR_Common <bits<32> inst> : R600_2OP <
660 inst, "ASHR $dst, $src0, $src1",
661 [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
662 >;
663
664 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
665 inst, "MULHI_INT $dst, $src0, $src1",
666 [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
667 >;
668
669 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
670 inst, "MULHI $dst, $src0, $src1",
671 []
672 >;
673
674 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
675 inst, "MULLO_INT $dst, $src0, $src1",
676 [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
677 >;
678
679 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
680 inst, "MULLO_UINT $dst, $src0, $src1",
681 []
682 >;
683
684 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
685 inst, "RECIP_CLAMPED",
686 []
687 >;
688
689 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
690 inst, "RECIP_IEEE",
691 [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
692 let AMDILOp = AMDILInst.RSQ_f32;
693 }
694
695 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
696 inst, "RECIP_INT $dst, $src",
697 []
698 >;
699
700 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
701 inst, "RECIPSQRT_CLAMPED",
702 [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
703 >;
704
705 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
706 inst, "RECIPSQRT_IEEE",
707 []
708 >;
709
710 class SIN_Common <bits<32> inst> : R600_1OP <
711 inst, "SIN",
712 []>{
713 let AMDILOp = AMDILInst.SIN_f32;
714 let Trig = 1;
715 }
716
717 class COS_Common <bits<32> inst> : R600_1OP <
718 inst, "COS",
719 []> {
720 let AMDILOp = AMDILInst.COS_f32;
721 let Trig = 1;
722 }
723
724 /* Helper patterns for complex intrinsics */
725 /* -------------------------------------- */
726
727 class DIV_Common <InstR600 recip_ieee> : Pat<
728 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
729 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
730 >;
731
732 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
733 (int_AMDGPU_ssg R600_Reg32:$src),
734 (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
735 >;
736
737 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
738 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
739 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
740 >;
741
742 /* ---------------------- */
743 /* R600 / R700 Only Instructions */
744 /* ---------------------- */
745
746 let Predicates = [isR600] in {
747
748 let Gen = AMDGPUGen.R600 in {
749
750 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
751 def MULADD_r600 : MULADD_Common<0x10>;
752 def CNDE_r600 : CNDE_Common<0x18>;
753 def CNDGT_r600 : CNDGT_Common<0x19>;
754 def CNDGE_r600 : CNDGE_Common<0x1A>;
755 def DOT4_r600 : DOT4_Common<0x50>;
756 def CUBE_r600 : CUBE_Common<0x52>;
757 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
758 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
759 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
760 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
761 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
762 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
763 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
764 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
765 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
766 def SIN_r600 : SIN_Common<0x6E>;
767 def COS_r600 : COS_Common<0x6F>;
768 def ASHR_r600 : ASHR_Common<0x70>;
769 def LSHR_r600 : LSHR_Common<0x71>;
770 def LSHL_r600 : LSHL_Common<0x72>;
771 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
772 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
773 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
774 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
775 def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
776
777 } // End AMDGPUGen.R600
778
779 def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
780 def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
781 def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
782 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
783
784 }
785
786 /* ----------------- */
787 /* R700+ Trig helper */
788 /* ----------------- */
789
790 /*
791 class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
792 (trig_inst R600_Reg32:$src),
793 (trig_inst (fmul R600_Reg32:$src, (PI))))
794 >;
795 */
796
797 /* ---------------------- */
798 /* Evergreen Instructions */
799 /* ---------------------- */
800
801
802 let Predicates = [isEG] in {
803
804 let Gen = AMDGPUGen.EG in {
805
806 def RAT_WRITE_CACHELESS_eg :
807 EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
808 R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
809 {
810 let RIM = 0;
811 /* XXX: Have a separate instruction for non-indexed writes. */
812 let TYPE = 1;
813 let RW_REL = 0;
814 let ELEM_SIZE = 0;
815
816 let ARRAY_SIZE = 0;
817 let COMP_MASK = 1;
818 let BURST_COUNT = 0;
819 let VPM = 0;
820 let EOP = 0;
821 let MARK = 0;
822 let BARRIER = 1;
823 }
824
825 def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
826 (ins R600_TReg32_X:$src, i32imm:$buffer_id),
827 "VTX_READ_eg $dst, $src", []>
828 {
829 /*
830 bits<7> DST_GPR;
831 bits<7> SRC_GPR;
832 bits<8> BUFFER_ID;
833 */
834 /* If any of these field below need to be calculated at compile time, and
835 * a ins operand for them and move them to the list of operands above. */
836
837 /* XXX: This instruction is manual encoded, so none of these values are used.
838 */
839 /*
840 bits<5> VC_INST = 0; //VC_INST_FETCH
841 bits<2> FETCH_TYPE = 2;
842 bits<1> FETCH_WHOLE_QUAD = 1;
843 bits<1> SRC_REL = 0;
844 bits<2> SRC_SEL_X = 0;
845 bits<6> MEGA_FETCH_COUNT = 4;
846 */
847 /*
848
849 bits<1> DST_REL = 0;
850 bits<3> DST_SEL_X = 0;
851 bits<3> DST_SEL_Y = 7; //Masked
852 bits<3> DST_SEL_Z = 7; //Masked
853 bits<3> DST_SEL_W = 7; //Masked
854 bits<1> USE_CONST_FIELDS = 1; //Masked
855 bits<6> DATA_FORMAT = 0;
856 bits<2> NUM_FORMAT_ALL = 0;
857 bits<1> FORMAT_COMP_ALL = 0;
858 bits<1> SRF_MODE_ALL = 0;
859 */
860
861 /*
862 let Inst{4-0} = VC_INST;
863 let Inst{6-5} = FETCH_TYPE;
864 let Inst{7} = FETCH_WHOLE_QUAD;
865 let Inst{15-8} = BUFFER_ID;
866 let Inst{22-16} = SRC_GPR;
867 let Inst{23} = SRC_REL;
868 let Inst{25-24} = SRC_SEL_X;
869 let Inst{31-26} = MEGA_FETCH_COUNT;
870 */
871 /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you
872 * from statically setting bits > 31. This field will be set by
873 * getMachineValueOp which can set bits > 31.
874 */
875 // let Inst{32-38} = DST_GPR;
876
877 /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */
878
879 /*
880 let Inst{39} = DST_REL;
881 let Inst{40} = 0; //Reserved
882 let Inst{43-41} = DST_SEL_X;
883 let Inst{46-44} = DST_SEL_Y;
884 let Inst{49-47} = DST_SEL_Z;
885 let Inst{52-50} = DST_SEL_W;
886 let Inst{53} = USE_CONST_FIELDS;
887 let Inst{59-54} = DATA_FORMAT;
888 let Inst{61-60} = NUM_FORMAT_ALL;
889 let Inst{62} = FORMAT_COMP_ALL;
890 let Inst{63} = SRF_MODE_ALL;
891 */
892 }
893
894
895
896 } // End AMDGPUGen.EG
897 /* XXX: Need to convert PTR to rat_id */
898 /*
899 def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
900 (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
901 (f32 R600_Reg32:$value),
902 sel_x),
903 (f32 ZERO), 0, R600_Reg32:$ptr)>;
904 */
905
906 class VTX_Param_Read_Pattern <ValueType vt> : Pat <
907 (vt (load_param ADDRParam:$mem)),
908 (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>;
909
910 def : VTX_Param_Read_Pattern <f32>;
911 def : VTX_Param_Read_Pattern <i32>;
912
913 } // End isEG Predicate
914
915 /* ------------------------------- */
916 /* Evergreen / Cayman Instructions */
917 /* ------------------------------- */
918
919 let Predicates = [isEGorCayman] in {
920
921 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
922 (intr R600_Reg32:$src),
923 (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
924 >;
925
926 let Gen = AMDGPUGen.EG_CAYMAN in {
927
928 def MULADD_eg : MULADD_Common<0x14>;
929 def ASHR_eg : ASHR_Common<0x15>;
930 def LSHR_eg : LSHR_Common<0x16>;
931 def LSHL_eg : LSHL_Common<0x17>;
932 def CNDE_eg : CNDE_Common<0x19>;
933 def CNDGT_eg : CNDGT_Common<0x1A>;
934 def CNDGE_eg : CNDGE_Common<0x1B>;
935 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
936 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>;
937 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
938 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
939 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
940 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
941 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
942 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
943 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
944 def SIN_eg : SIN_Common<0x8D>;
945 def COS_eg : COS_Common<0x8E>;
946 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
947 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
948 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
949 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
950 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
951 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
952 def DOT4_eg : DOT4_Common<0xBE>;
953 def CUBE_eg : CUBE_Common<0xC0>;
954
955 } // End AMDGPUGen.EG_CAYMAN
956
957 def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
958 def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
959 def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
960 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
961
962 def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
963 def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
964
965 }
966
967 let Predicates = [isCayman] in {
968
969 let Gen = AMDGPUGen.CAYMAN in {
970
971 /* XXX: I'm not sure if this opcode is correct. */
972 def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
973
974 } // End AMDGPUGen.CAYMAN
975
976 } // End isCayman
977
978 /* Other Instructions */
979
980 let isCodeGenOnly = 1 in {
981 /*
982 def SWIZZLE : AMDGPUShaderInst <
983 (outs GPRV4F32:$dst),
984 (ins GPRV4F32:$src0, i32imm:$src1),
985 "SWIZZLE $dst, $src0, $src1",
986 [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
987 >;
988 */
989
990 def LAST : AMDGPUShaderInst <
991 (outs),
992 (ins),
993 "LAST",
994 []
995 >;
996
997 def GET_CHAN : AMDGPUShaderInst <
998 (outs R600_Reg32:$dst),
999 (ins R600_Reg128:$src0, i32imm:$src1),
1000 "GET_CHAN $dst, $src0, $src1",
1001 []
1002 >;
1003
1004 def MULLIT : AMDGPUShaderInst <
1005 (outs R600_Reg128:$dst),
1006 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
1007 "MULLIT $dst, $src0, $src1",
1008 [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
1009 >;
1010
1011 let usesCustomInserter = 1, isPseudo = 1 in {
1012
1013 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
1014 (outs R600_TReg32:$dst),
1015 (ins),
1016 asm,
1017 [(set R600_TReg32:$dst, (intr))]
1018 >;
1019
1020 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
1021 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
1022 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
1023
1024 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
1025 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
1026 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
1027
1028 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
1029 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
1030 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
1031
1032 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
1033 int_r600_read_global_size_x>;
1034 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
1035 int_r600_read_global_size_y>;
1036 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
1037 int_r600_read_global_size_z>;
1038
1039 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
1040 int_r600_read_local_size_x>;
1041 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
1042 int_r600_read_local_size_y>;
1043 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
1044 int_r600_read_local_size_z>;
1045
1046 def R600_LOAD_CONST : AMDGPUShaderInst <
1047 (outs R600_Reg32:$dst),
1048 (ins i32imm:$src0),
1049 "R600_LOAD_CONST $dst, $src0",
1050 [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1051 >;
1052
1053 def LOAD_INPUT : AMDGPUShaderInst <
1054 (outs R600_Reg32:$dst),
1055 (ins i32imm:$src),
1056 "LOAD_INPUT $dst, $src",
1057 [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1058 >;
1059
1060 def RESERVE_REG : AMDGPUShaderInst <
1061 (outs),
1062 (ins i32imm:$src),
1063 "RESERVE_REG $src",
1064 [(int_AMDGPU_reserve_reg imm:$src)]
1065 >;
1066
1067 def STORE_OUTPUT: AMDGPUShaderInst <
1068 (outs),
1069 (ins R600_Reg32:$src0, i32imm:$src1),
1070 "STORE_OUTPUT $src0, $src1",
1071 [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1072 >;
1073
1074 def TXD: AMDGPUShaderInst <
1075 (outs R600_Reg128:$dst),
1076 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1077 "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1078 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1079 >;
1080
1081 def TXD_SHADOW: AMDGPUShaderInst <
1082 (outs R600_Reg128:$dst),
1083 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1084 "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1085 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1086 >;
1087
1088 } // End usesCustomInserter = 1, isPseudo = 1
1089
1090 } // End isCodeGenOnly = 1
1091
1092
1093
1094 let isPseudo = 1 in {
1095
1096 def LOAD_VTX : AMDGPUShaderInst <
1097 (outs R600_Reg32:$dst),
1098 (ins MEMri:$mem),
1099 "LOAD_VTX",
1100 [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
1101 >;
1102
1103
1104 } //End isPseudo
1105
1106 //===----------------------------------------------------------------------===//
1107 // ISel Patterns
1108 //===----------------------------------------------------------------------===//
1109
1110 // SGT Reverse args
1111 def : Pat <
1112 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1113 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1114 >;
1115
1116 // SGE Reverse args
1117 def : Pat <
1118 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1119 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1120 >;
1121
1122 // SETGT_INT reverse args
1123 def : Pat <
1124 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1125 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1126 >;
1127
1128 // SETGE_INT reverse args
1129 def : Pat <
1130 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1131 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1132 >;
1133
1134 // SETGT_UINT reverse args
1135 def : Pat <
1136 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1137 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1138 >;
1139
1140 // SETGE_UINT reverse args
1141 def : Pat <
1142 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1143 (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1144 >;
1145
1146 // The next two patterns are special cases for handling 'true if ordered' and
1147 // 'true if unordered' conditionals. The assumption here is that the behavior of
1148 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1149 // described here:
1150 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1151 // We assume that SETE returns false when one of the operands is NAN and
1152 // SNE returns true when on of the operands is NAN
1153
1154 //SETE - 'true if ordered'
1155 def : Pat <
1156 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1157 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1158 >;
1159
1160 //SNE - 'true if unordered'
1161 def : Pat <
1162 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1163 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1164 >;
1165
1166 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1167 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1168 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1169 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1170
1171 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1172 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1173 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1174 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1175
1176 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1177 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1178 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1179 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1180
1181 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1182 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1183 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1184 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1185
1186 } // End isR600toCayman Predicate