src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Tablegen instruction definitions
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<32> Inst;
  21         bit Trig = 0;
  22   bit Op3 = 0;
  23
  24   let Inst = inst;
  25   let Namespace = "AMDIL";
  26   let OutOperandList = outs;
  27   let InOperandList = ins;
  28   let AsmString = asm;
  29   let Pattern = pattern;
  30   let Itinerary = itin;
  31
  32   let TSFlags{4} = Trig;
  33   let TSFlags{5} = Op3;
  34 }
  35
  36 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  37     AMDGPUInst <outs, ins, asm, pattern>
  38 {
  39   field bits<64> Inst;
  40
  41   let Namespace = "AMDIL";
  42 }
  43
  44 def MEMri : Operand<iPTRAny> {
  45   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  46 }
  47
  48 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  49
  50 class R600_ALU {
  51
  52   bits<7> DST_GPR = 0;
  53   bits<9> SRC0_SEL = 0;
  54   bits<1> SRC0_NEG = 0;
  55   bits<9> SRC1_SEL = 0;
  56   bits<1> SRC1_NEG = 0;
  57   bits<1> CLAMP = 0;
  58
  59 }
  60
  61
  62 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
  63                 InstrItinClass itin = AnyALU> :
  64   InstR600 <inst,
  65           (outs R600_Reg32:$dst),
  66           (ins R600_Reg32:$src, variable_ops),
  67           !strconcat(opName, " $dst, $src"),
  68           pattern,
  69           itin
  70   >;
  71
  72 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
  73                 InstrItinClass itin = AnyALU> :
  74   InstR600 <inst,
  75           (outs R600_Reg32:$dst),
  76           (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
  77           !strconcat(opName, " $dst, $src0, $src1"),
  78           pattern,
  79           itin
  80   >;
  81
  82 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
  83                 InstrItinClass itin = AnyALU> :
  84   InstR600 <inst,
  85           (outs R600_Reg32:$dst),
  86           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
  87           !strconcat(opName, " $dst, $src0, $src1, $src2"),
  88           pattern,
  89           itin>{
  90
  91     let Op3 = 1;
  92   }
  93
  94 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
  95                       InstrItinClass itin = VecALU> :
  96   InstR600 <inst,
  97           (outs R600_Reg32:$dst),
  98           ins,
  99           asm,
 100           pattern,
 101           itin
 102
 103   >;
 104
 105 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
 106                 InstrItinClass itin = AnyALU> :
 107   InstR600 <inst,
 108           (outs R600_Reg128:$dst),
 109           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 110           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 111           pattern,
 112           itin
 113   >;
 114
 115 def TEX_SHADOW : PatLeaf<
 116   (imm),
 117   [{uint32_t TType = (uint32_t)N->getZExtValue();
 118     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 119   }]
 120 >;
 121
 122 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
 123                  string asm> :
 124     InstR600ISA <outs, ins, asm, []>
 125 {
 126   bits<7>  RW_GPR;
 127   bits<7>  INDEX_GPR;
 128   bits<4>  RAT_ID;
 129
 130   bits<2>  RIM;
 131   bits<2>  TYPE;
 132   bits<1>  RW_REL;
 133   bits<2>  ELEM_SIZE;
 134
 135   bits<12> ARRAY_SIZE;
 136   bits<4>  COMP_MASK;
 137   bits<4>  BURST_COUNT;
 138   bits<1>  VPM;
 139   bits<1>  EOP;
 140   bits<1>  MARK;
 141   bits<1>  BARRIER;
 142
 143   /* CF_ALLOC_EXPORT_WORD0_RAT */
 144   let Inst{3-0}   = RAT_ID;
 145   let Inst{9-4}   = rat_inst;
 146   let Inst{10}    = 0; /* Reserved */
 147   let Inst{12-11} = RIM;
 148   let Inst{14-13} = TYPE;
 149   let Inst{21-15} = RW_GPR;
 150   let Inst{22}    = RW_REL;
 151   let Inst{29-23} = INDEX_GPR;
 152   let Inst{31-30} = ELEM_SIZE;
 153
 154   /* CF_ALLOC_EXPORT_WORD1_BUF */
 155   let Inst{43-32} = ARRAY_SIZE;
 156   let Inst{47-44} = COMP_MASK;
 157   let Inst{51-48} = BURST_COUNT;
 158   let Inst{52}    = VPM;
 159   let Inst{53}    = EOP;
 160   let Inst{61-54} = cf_inst;
 161   let Inst{62}    = MARK;
 162   let Inst{63}    = BARRIER;
 163 }
 164
 165 /*
 166 def store_global : PatFrag<(ops node:$value, node:$ptr),
 167                            (store node:$value, node:$ptr),
 168                            [{
 169                             const Value *Src;
 170                             const PointerType *Type;
 171                             if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
 172                                  PT = dyn_cast<PointerType>(Src->getType()))) {
 173                               return PT->getAddressSpace() == 1;
 174                             }
 175                             return false;
 176                            }]>;
 177
 178 */
 179
 180 def load_param : PatFrag<(ops node:$ptr),
 181                          (load node:$ptr),
 182                           [{
 183                            return true;
 184                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 185                            if (Src) {
 186                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 187                                 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
 188                            }
 189                            return false;
 190                           }]>;
 191
 192 //class EG_CF <bits<32> inst, string asm> :
 193 //    InstR600 <inst, (outs), (ins), asm, []>;
 194
 195 /* XXX: We will use this when we emit the real ISA.
 196   bits<24> ADDR = 0;
 197   bits<3> JTS = 0;
 198
 199   bits<3> PC = 0;
 200   bits<5> CF_CONS = 0;
 201   bits<2> COND = 0;
 202   bits<6> COUNT = 0;
 203   bits<1> VPM = 0;
 204   bits<1> EOP = 0;
 205   bits<8> CF_INST = 0;
 206   bits<1> WQM = 0;
 207   bits<1> B = 0;
 208
 209   let Inst{23-0} = ADDR;
 210   let Inst{26-24} = JTS;
 211   let Inst{34-32} = PC;
 212   let Inst{39-35} = CF_CONST;
 213   let Inst{41-40} = COND;
 214   let Inst{47-42} = COUNT;
 215   let Inst{52} = VPM;
 216   let Inst{53} = EOP;
 217   let Inst{61-54} = CF_INST;
 218   let Inst{62} = WQM;
 219   let Inst{63} = B;
 220 //}
 221 */
 222 def isR600 : Predicate<"Subtarget.device()"
 223                             "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
 224 def isEG : Predicate<"Subtarget.device()"
 225                             "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
 226                             "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 227 def isCayman : Predicate<"Subtarget.device()"
 228                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 229 def isEGorCayman : Predicate<"Subtarget.device()"
 230                             "->getGeneration() == AMDILDeviceInfo::HD5XXX"
 231                             "|| Subtarget.device()->getGeneration() =="
 232                             "AMDILDeviceInfo::HD6XXX">;
 233
 234 def isR600toCayman : Predicate<
 235                      "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
 236
 237
 238 let Predicates = [isR600toCayman] in {
 239
 240 /* ------------------------------------------- */
 241 /* Common Instructions R600, R700, Evergreen, Cayman */
 242 /* ------------------------------------------- */
 243 let Gen = AMDGPUGen.R600_CAYMAN  in {
 244
 245 def ADD : R600_2OP <
 246   0x0, "ADD",
 247   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
 248 >;
 249
 250 // Non-IEEE MUL: 0 * anything = 0
 251 def MUL : R600_2OP <
 252   0x1, "MUL NON-IEEE",
 253   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 254 >;
 255
 256 def MUL_IEEE : R600_2OP <
 257   0x2, "MUL_IEEE",
 258   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]> {
 259   let AMDILOp = AMDILInst.MUL_IEEE_f32;
 260 }
 261
 262 def MAX : R600_2OP <
 263   0x3, "MAX",
 264   [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
 265 >;
 266
 267 def MIN : R600_2OP <
 268   0x4, "MIN",
 269   [(set R600_Reg32:$dst, (int_AMDIL_min R600_Reg32:$src0, R600_Reg32:$src1))]> {
 270   let AMDILOp = AMDILInst.MIN_f32;
 271 }
 272
 273 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 274  * so some of the instruction names don't match the asm string.
 275  * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 276  */
 277
 278 def SETE : R600_2OP <
 279   0x08, "SETE",
 280   [(set R600_Reg32:$dst, (int_AMDGPU_seq R600_Reg32:$src0, R600_Reg32:$src1))]> {
 281   let AMDILOp = AMDILInst.FEQ;
 282 }
 283
 284 def SGT : R600_2OP <
 285   0x09, "SETGT",
 286   [(set R600_Reg32:$dst, (int_AMDGPU_sgt R600_Reg32:$src0, R600_Reg32:$src1))]
 287 >;
 288
 289 def SGE : R600_2OP <
 290   0xA, "SETGE",
 291   [(set R600_Reg32:$dst, (int_AMDGPU_sge R600_Reg32:$src0, R600_Reg32:$src1))]> {
 292   let AMDILOp = AMDILInst.FGE;
 293 }
 294
 295 def SNE : R600_2OP <
 296   0xB, "SETNE",
 297   [(set R600_Reg32:$dst, (int_AMDGPU_sne R600_Reg32:$src0, R600_Reg32:$src1))]> {
 298   let AMDILOp = AMDILInst.FNE;
 299 }
 300
 301 def FRACT : R600_1OP <
 302   0x10, "FRACT",
 303   []> {
 304   let AMDILOp = AMDILInst.FRAC_f32;
 305 }
 306
 307 def TRUNC : R600_1OP <
 308   0x11, "TRUNC",
 309   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 310 >;
 311
 312 def CEIL : R600_1OP <
 313   0x12, "CEIL",
 314   [(set R600_Reg32:$dst, (int_AMDIL_round_posinf R600_Reg32:$src))]> {
 315   let AMDILOp = AMDILInst.ROUND_POSINF_f32;
 316 }
 317
 318 def RNDNE : R600_1OP <
 319   0x13, "RNDNE",
 320   [(set R600_Reg32:$dst, (int_AMDIL_round_nearest R600_Reg32:$src))]> {
 321   let AMDILOp = AMDILInst.ROUND_NEAREST_f32;
 322 }
 323
 324 def FLOOR : R600_1OP <
 325   0x14, "FLOOR",
 326   [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
 327 >;
 328
 329 def MOV : R600_1OP <0x19, "MOV", []>;
 330
 331 def KILLGT : R600_2OP <
 332   0x2D, "KILLGT",
 333   []
 334 >;
 335
 336 def AND_INT : R600_2OP <
 337   0x30, "AND_INT",
 338   []> {
 339   let AMDILOp = AMDILInst.AND_i32;
 340 }
 341
 342 def OR_INT : R600_2OP <
 343   0x31, "OR_INT",
 344   []>{
 345   let AMDILOp = AMDILInst.BINARY_OR_i32;
 346 }
 347
 348 def XOR_INT : R600_2OP <
 349   0x32, "XOR_INT",
 350   []
 351 >;
 352
 353 def NOT_INT : R600_1OP <
 354   0x33, "NOT_INT",
 355   []>{
 356   let AMDILOp = AMDILInst.BINARY_NOT_i32;
 357 }
 358
 359 def ADD_INT : R600_2OP <
 360   0x34, "ADD_INT",
 361   []>{
 362   let AMDILOp = AMDILInst.ADD_i32;
 363 }
 364
 365 def SUB_INT : R600_2OP <
 366         0x35, "SUB_INT",
 367         [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
 368 >;
 369
 370 def MAX_INT : R600_2OP <
 371   0x36, "MAX_INT",
 372   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 373
 374 def MIN_INT : R600_2OP <
 375   0x37, "MIN_INT",
 376   [(set R600_Reg32:$dst, (int_AMDGPU_imin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 377
 378 def MAX_UINT : R600_2OP <
 379   0x38, "MAX_UINT",
 380   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 381
 382 def MIN_UINT : R600_2OP <
 383   0x39, "MIN_UINT",
 384   [(set R600_Reg32:$dst, (int_AMDGPU_umin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 385
 386
 387 def SETE_INT : R600_2OP <
 388   0x3A, "SETE_INT",
 389   []>{
 390   let AMDILOp = AMDILInst.IEQ;
 391 }
 392
 393 def SETGT_INT : R600_2OP <
 394   0x3B, "SGT_INT",
 395   []
 396 >;
 397
 398 def SETGE_INT : R600_2OP <
 399         0x3C, "SETGE_INT",
 400         []>{
 401   let AMDILOp = AMDILInst.IGE;
 402 }
 403
 404 def SETNE_INT : R600_2OP <
 405   0x3D, "SETNE_INT",
 406   []>{
 407   let AMDILOp = AMDILInst.INE;
 408 }
 409
 410 def SETGT_UINT : R600_2OP <
 411   0x3E, "SETGT_UINT",
 412   []>{
 413   let AMDILOp = AMDILInst.UGT;
 414 }
 415
 416 def SETGE_UINT : R600_2OP <
 417   0x3F, "SETGE_UINT",
 418   []>{
 419   let AMDILOp = AMDILInst.UGE;
 420 }
 421
 422 def CNDE_INT : R600_3OP <
 423         0x1C, "CNDE_INT",
 424   [(set (i32 R600_Reg32:$dst),
 425    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 426 >;
 427
 428 /* Texture instructions */
 429
 430
 431 def TEX_LD : R600_TEX <
 432   0x03, "TEX_LD",
 433   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
 434 > {
 435 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
 436 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
 437 }
 438
 439 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 440   0x04, "TEX_GET_TEXTURE_RESINFO",
 441   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 442 >;
 443
 444 def TEX_GET_GRADIENTS_H : R600_TEX <
 445   0x07, "TEX_GET_GRADIENTS_H",
 446   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 447 >;
 448
 449 def TEX_GET_GRADIENTS_V : R600_TEX <
 450   0x08, "TEX_GET_GRADIENTS_V",
 451   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 452 >;
 453
 454 def TEX_SET_GRADIENTS_H : R600_TEX <
 455   0x0B, "TEX_SET_GRADIENTS_H",
 456   []
 457 >;
 458
 459 def TEX_SET_GRADIENTS_V : R600_TEX <
 460   0x0C, "TEX_SET_GRADIENTS_V",
 461   []
 462 >;
 463
 464 def TEX_SAMPLE : R600_TEX <
 465   0x10, "TEX_SAMPLE",
 466   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 467 >;
 468
 469 def TEX_SAMPLE_C : R600_TEX <
 470   0x18, "TEX_SAMPLE_C",
 471   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 472 >;
 473
 474 def TEX_SAMPLE_L : R600_TEX <
 475   0x11, "TEX_SAMPLE_L",
 476   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 477 >;
 478
 479 def TEX_SAMPLE_C_L : R600_TEX <
 480   0x19, "TEX_SAMPLE_C_L",
 481   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 482 >;
 483
 484 def TEX_SAMPLE_LB : R600_TEX <
 485   0x12, "TEX_SAMPLE_LB",
 486   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 487 >;
 488
 489 def TEX_SAMPLE_C_LB : R600_TEX <
 490   0x1A, "TEX_SAMPLE_C_LB",
 491   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 492 >;
 493
 494 def TEX_SAMPLE_G : R600_TEX <
 495   0x14, "TEX_SAMPLE_G",
 496   []
 497 >;
 498
 499 def TEX_SAMPLE_C_G : R600_TEX <
 500   0x1C, "TEX_SAMPLE_C_G",
 501   []
 502 >;
 503
 504 } // End Gen R600_CAYMAN
 505
 506 def KILP : Pat <
 507   (int_AMDGPU_kilp),
 508   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
 509 >;
 510
 511 def KIL : Pat <
 512   (int_AMDGPU_kill R600_Reg32:$src0),
 513   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
 514 >;
 515
 516 /* Helper classes for common instructions */
 517
 518 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
 519   inst, "MUL_LIT",
 520   []
 521 >;
 522
 523 class MULADD_Common <bits<32> inst> : R600_3OP <
 524   inst, "MULADD",
 525   []> {
 526   let AMDILOp = AMDILInst.MAD_f32;
 527 }
 528
 529 class CNDE_Common <bits<32> inst> : R600_3OP <
 530   inst, "CNDE",
 531   [(set (f32 R600_Reg32:$dst),
 532    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 533 >;
 534
 535 class CNDGT_Common <bits<32> inst> : R600_3OP <
 536   inst, "CNDGT",
 537   []
 538 >;
 539
 540 class CNDGE_Common <bits<32> inst> : R600_3OP <
 541   inst, "CNDGE",
 542   [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 543 >;
 544
 545 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
 546   inst,
 547   (ins R600_Reg128:$src0, R600_Reg128:$src1),
 548   "DOT4 $dst $src0, $src1",
 549   [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 550 >;
 551
 552 class CUBE_Common <bits<32> inst> : InstR600 <
 553   inst,
 554   (outs R600_Reg128:$dst),
 555   (ins R600_Reg128:$src),
 556   "CUBE $dst $src",
 557   [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 558   VecALU
 559 >;
 560
 561 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
 562   inst, "EXP_IEEE",
 563   []> {
 564   let AMDILOp = AMDILInst.EXP_f32;
 565 }
 566
 567 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
 568   inst, "FLT_TO_INT", []> {
 569   let AMDILOp = AMDILInst.FTOI;
 570 }
 571
 572 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 573   inst, "INT_TO_FLT", []> {
 574   let AMDILOp = AMDILInst.ITOF;
 575 }
 576
 577 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 578   inst, "LOG_CLAMPED",
 579   []
 580 >;
 581
 582 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
 583   inst, "LOG_IEEE",
 584   []> {
 585   let AMDILOp = AMDILInst.LOG_f32;
 586 }
 587
 588 class LSHL_Common <bits<32> inst> : R600_2OP <
 589   inst, "LSHL $dst, $src0, $src1",
 590   [] >{
 591   let AMDILOp = AMDILInst.SHL_i32;
 592 }
 593
 594 class LSHR_Common <bits<32> inst> : R600_2OP <
 595   inst, "LSHR $dst, $src0, $src1",
 596   [] >{
 597   let AMDILOp = AMDILInst.USHR_i32;
 598 }
 599
 600 class ASHR_Common <bits<32> inst> : R600_2OP <
 601   inst, "ASHR $dst, $src0, $src1",
 602   [] >{
 603   let AMDILOp = AMDILInst.SHR_i32;
 604 }
 605
 606 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
 607   inst, "MULHI_INT $dst, $src0, $src1",
 608   [] >{
 609   let AMDILOp = AMDILInst.SMULHI_i32;
 610 }
 611
 612 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
 613         inst, "MULHI $dst, $src0, $src1",
 614         []
 615 >;
 616
 617 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
 618   inst, "MULLO_INT $dst, $src0, $src1",
 619   [] >{
 620   let AMDILOp = AMDILInst.SMUL_i32;
 621 }
 622
 623 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
 624   inst, "MULLO_UINT $dst, $src0, $src1",
 625   []
 626 >;
 627
 628 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 629   inst, "RECIP_CLAMPED",
 630   []
 631 >;
 632
 633 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
 634   inst, "RECIP_IEEE",
 635   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
 636   let AMDILOp = AMDILInst.RSQ_f32;
 637 }
 638
 639 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
 640   inst, "RECIP_INT $dst, $src",
 641   []
 642 >;
 643
 644 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
 645   inst, "RECIPSQRT_CLAMPED",
 646   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 647 >;
 648
 649 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 650   inst, "RECIPSQRT_IEEE",
 651   []
 652 >;
 653
 654 class SIN_Common <bits<32> inst> : R600_1OP <
 655   inst, "SIN",
 656   []>{
 657   let AMDILOp = AMDILInst.SIN_f32;
 658   let Trig = 1;
 659 }
 660
 661 class COS_Common <bits<32> inst> : R600_1OP <
 662   inst, "COS",
 663   []> {
 664   let AMDILOp = AMDILInst.COS_f32;
 665   let Trig = 1;
 666 }
 667
 668 /* Helper patterns for complex intrinsics */
 669 /* -------------------------------------- */
 670
 671 class DIV_Common <InstR600 recip_ieee> : Pat<
 672   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 673   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 674 >;
 675
 676 class LRP_Common <InstR600 muladd> : Pat <
 677   (int_AMDGPU_lrp R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
 678   (muladd R600_Reg32:$src0, R600_Reg32:$src1, (MUL (SUB_f32 ONE, R600_Reg32:$src0), R600_Reg32:$src2))
 679 >;
 680
 681 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 682   (int_AMDGPU_ssg R600_Reg32:$src),
 683   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 684 >;
 685
 686 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 687   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 688   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 689 >;
 690
 691 /* ---------------------- */
 692 /* R600 / R700 Only Instructions */
 693 /* ---------------------- */
 694
 695 let Predicates = [isR600] in {
 696
 697 let Gen = AMDGPUGen.R600 in {
 698
 699   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 700   def MULADD_r600 : MULADD_Common<0x10>;
 701   def CNDE_r600 : CNDE_Common<0x18>;
 702   def CNDGT_r600 : CNDGT_Common<0x19>;
 703   def CNDGE_r600 : CNDGE_Common<0x1A>;
 704   def DOT4_r600 : DOT4_Common<0x50>;
 705   def CUBE_r600 : CUBE_Common<0x52>;
 706   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 707   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 708   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 709   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 710   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 711   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 712   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 713   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 714   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 715   def SIN_r600 : SIN_Common<0x6E>;
 716   def COS_r600 : COS_Common<0x6F>;
 717   def ASHR_r600 : ASHR_Common<0x70>;
 718   def LSHR_r600 : LSHR_Common<0x71>;
 719   def LSHL_r600 : LSHL_Common<0x72>;
 720   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 721   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 722   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 723   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 724   def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
 725
 726 } // End AMDGPUGen.R600
 727
 728   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 729   def LRP_r600 : LRP_Common<MULADD_r600>;
 730   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 731   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 732   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 733
 734 }
 735
 736 /* ----------------- */
 737 /* R700+ Trig helper */
 738 /* ----------------- */
 739
 740 /*
 741 class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
 742   (trig_inst R600_Reg32:$src),
 743   (trig_inst (fmul R600_Reg32:$src, (PI))))
 744 >;
 745 */
 746
 747 /* ---------------------- */
 748 /* Evergreen Instructions */
 749 /* ---------------------- */
 750
 751
 752 let Predicates = [isEG] in {
 753
 754 let Gen = AMDGPUGen.EG in {
 755
 756 def RAT_WRITE_CACHELESS_eg :
 757     EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
 758                                    R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
 759 {
 760   let RIM         = 0;
 761   /* XXX: Have a separate instruction for non-indexed writes. */
 762   let TYPE        = 1;
 763   let RW_REL      = 0;
 764   let ELEM_SIZE   = 0;
 765
 766   let ARRAY_SIZE  = 0;
 767   let COMP_MASK   = 1;
 768   let BURST_COUNT = 0;
 769   let VPM         = 0;
 770   let EOP         = 0;
 771   let MARK        = 0;
 772   let BARRIER     = 1;
 773 }
 774
 775 def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
 776                                 (ins R600_TReg32_X:$src, i32imm:$buffer_id),
 777                                 "VTX_READ_eg $dst, $src", []>
 778 {
 779 /*
 780   bits<7> DST_GPR;
 781   bits<7> SRC_GPR;
 782   bits<8> BUFFER_ID;
 783 */
 784   /* If any of these field below need to be calculated at compile time, and
 785    * a ins operand for them and move them to the list of operands above. */
 786
 787   /* XXX: This instruction is manual encoded, so none of these values are used.
 788    */
 789 /*
 790   bits<5> VC_INST          = 0; //VC_INST_FETCH
 791   bits<2> FETCH_TYPE       = 2;
 792   bits<1> FETCH_WHOLE_QUAD = 1;
 793   bits<1> SRC_REL          = 0;
 794   bits<2> SRC_SEL_X        = 0;
 795   bits<6> MEGA_FETCH_COUNT = 4;
 796 */
 797 /*
 798
 799   bits<1> DST_REL          = 0;
 800   bits<3> DST_SEL_X        = 0;
 801   bits<3> DST_SEL_Y        = 7; //Masked
 802   bits<3> DST_SEL_Z        = 7; //Masked
 803   bits<3> DST_SEL_W        = 7; //Masked
 804   bits<1> USE_CONST_FIELDS = 1; //Masked
 805   bits<6> DATA_FORMAT      = 0;
 806   bits<2> NUM_FORMAT_ALL   = 0;
 807   bits<1> FORMAT_COMP_ALL  = 0;
 808   bits<1> SRF_MODE_ALL     = 0;
 809 */
 810
 811 /*
 812   let Inst{4-0}   = VC_INST;
 813   let Inst{6-5}   = FETCH_TYPE;
 814   let Inst{7}     = FETCH_WHOLE_QUAD;
 815   let Inst{15-8}  = BUFFER_ID;
 816   let Inst{22-16} = SRC_GPR;
 817   let Inst{23}    = SRC_REL;
 818   let Inst{25-24} = SRC_SEL_X;
 819   let Inst{31-26} = MEGA_FETCH_COUNT;
 820 */
 821   /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you
 822    * from statically setting bits > 31.  This field will be set by
 823    * getMachineValueOp which can set bits > 31.
 824    */
 825 //  let Inst{32-38} = DST_GPR;
 826
 827   /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */
 828
 829 /*
 830   let Inst{39}    = DST_REL;
 831   let Inst{40}    = 0; //Reserved
 832   let Inst{43-41} = DST_SEL_X;
 833   let Inst{46-44} = DST_SEL_Y;
 834   let Inst{49-47} = DST_SEL_Z;
 835   let Inst{52-50} = DST_SEL_W;
 836   let Inst{53}    = USE_CONST_FIELDS;
 837   let Inst{59-54} = DATA_FORMAT;
 838   let Inst{61-60} = NUM_FORMAT_ALL;
 839   let Inst{62}    = FORMAT_COMP_ALL;
 840   let Inst{63}    = SRF_MODE_ALL;
 841 */
 842 }
 843
 844
 845
 846 } // End AMDGPUGen.EG
 847 /* XXX: Need to convert PTR to rat_id */
 848 /*
 849 def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
 850            (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
 851                                                   (f32 R600_Reg32:$value),
 852                                                    sel_x),
 853                                     (f32 ZERO), 0, R600_Reg32:$ptr)>;
 854 */
 855
 856 class VTX_Param_Read_Pattern <ValueType vt> : Pat <
 857     (vt (load_param ADDRParam:$mem)),
 858     (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>;
 859
 860 def : VTX_Param_Read_Pattern <f32>;
 861 def : VTX_Param_Read_Pattern <i32>;
 862
 863 } // End isEG Predicate
 864
 865 /* ------------------------------- */
 866 /* Evergreen / Cayman Instructions */
 867 /* ------------------------------- */
 868
 869 let Predicates = [isEGorCayman] in {
 870
 871 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
 872   (intr R600_Reg32:$src),
 873   (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
 874 >;
 875
 876 let Gen = AMDGPUGen.EG_CAYMAN in {
 877
 878   def MULADD_eg : MULADD_Common<0x14>;
 879   def ASHR_eg : ASHR_Common<0x15>;
 880   def LSHR_eg : LSHR_Common<0x16>;
 881   def LSHL_eg : LSHL_Common<0x17>;
 882   def CNDE_eg : CNDE_Common<0x19>;
 883   def CNDGT_eg : CNDGT_Common<0x1A>;
 884   def CNDGE_eg : CNDGE_Common<0x1B>;
 885   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 886   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>;
 887   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 888   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 889   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 890   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 891   def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 892   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 893   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 894   def SIN_eg : SIN_Common<0x8D>;
 895   def COS_eg : COS_Common<0x8E>;
 896   def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 897   def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 898   def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 899   def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 900   def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 901   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
 902   def DOT4_eg : DOT4_Common<0xBE>;
 903   def CUBE_eg : CUBE_Common<0xC0>;
 904
 905 } // End AMDGPUGen.EG_CAYMAN
 906
 907   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
 908   def LRP_eg : LRP_Common<MULADD_eg>;
 909   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
 910   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
 911   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 912
 913   def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
 914   def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
 915
 916 }
 917
 918 let Predicates = [isCayman] in {
 919
 920 let Gen = AMDGPUGen.CAYMAN in {
 921
 922   /* XXX: I'm not sure if this opcode is correct. */
 923   def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
 924
 925 } // End AMDGPUGen.CAYMAN
 926
 927 } // End isCayman
 928
 929 /* Other Instructions */
 930
 931 let isCodeGenOnly = 1 in {
 932 /*
 933   def SWIZZLE : AMDGPUShaderInst <
 934     (outs GPRV4F32:$dst),
 935     (ins GPRV4F32:$src0, i32imm:$src1),
 936     "SWIZZLE $dst, $src0, $src1",
 937     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
 938   >;
 939 */
 940
 941   def LAST : AMDGPUShaderInst <
 942     (outs),
 943     (ins),
 944     "LAST",
 945     []
 946   >;
 947
 948   def GET_CHAN : AMDGPUShaderInst <
 949     (outs R600_Reg32:$dst),
 950     (ins R600_Reg128:$src0, i32imm:$src1),
 951     "GET_CHAN $dst, $src0, $src1",
 952     []
 953   >;
 954
 955   def MULLIT : AMDGPUShaderInst <
 956     (outs R600_Reg128:$dst),
 957     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
 958     "MULLIT $dst, $src0, $src1",
 959     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 960   >;
 961
 962 let usesCustomInserter = 1, isPseudo = 1 in {
 963
 964 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
 965   (outs R600_TReg32:$dst),
 966   (ins),
 967   asm,
 968   [(set R600_TReg32:$dst, (intr))]
 969 >;
 970
 971 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
 972 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
 973 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
 974
 975 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
 976 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
 977 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
 978
 979 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
 980 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
 981 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
 982
 983 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
 984                                      int_r600_read_global_size_x>;
 985 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
 986                                      int_r600_read_global_size_y>;
 987 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
 988                                      int_r600_read_global_size_z>;
 989
 990 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
 991                                     int_r600_read_local_size_x>;
 992 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
 993                                     int_r600_read_local_size_y>;
 994 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
 995                                     int_r600_read_local_size_z>;
 996
 997 def R600_LOAD_CONST : AMDGPUShaderInst <
 998   (outs R600_Reg32:$dst),
 999   (ins i32imm:$src0),
1000   "R600_LOAD_CONST $dst, $src0",
1001   [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1002 >;
1003
1004 def LOAD_INPUT : AMDGPUShaderInst <
1005   (outs R600_Reg32:$dst),
1006   (ins i32imm:$src),
1007   "LOAD_INPUT $dst, $src",
1008   [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1009 >;
1010
1011 def RESERVE_REG : AMDGPUShaderInst <
1012   (outs),
1013   (ins i32imm:$src),
1014   "RESERVE_REG $src",
1015   [(int_AMDGPU_reserve_reg imm:$src)]
1016 >;
1017
1018 def STORE_OUTPUT: AMDGPUShaderInst <
1019   (outs),
1020   (ins R600_Reg32:$src0, i32imm:$src1),
1021   "STORE_OUTPUT $src0, $src1",
1022   [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1023 >;
1024
1025 def TXD: AMDGPUShaderInst <
1026   (outs R600_Reg128:$dst),
1027   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1028   "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1029   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1030 >;
1031
1032 def TXD_SHADOW: AMDGPUShaderInst <
1033   (outs R600_Reg128:$dst),
1034   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1035   "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1036   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1037 >;
1038
1039 } // End usesCustomInserter = 1, isPseudo = 1
1040
1041 } // End isCodeGenOnly = 1
1042
1043
1044
1045 let isPseudo = 1 in {
1046
1047 def LOAD_VTX : AMDGPUShaderInst <
1048     (outs R600_Reg32:$dst),
1049     (ins MEMri:$mem),
1050     "LOAD_VTX",
1051     [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
1052 >;
1053
1054
1055 } //End isPseudo
1056
1057 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1058 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1059 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1060 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1061
1062 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1063 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1064 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1065 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1066
1067 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1068 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1069 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1070 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1071
1072 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1073 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1074 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1075 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1076
1077 } // End isR600toCayman Predicate