src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Tablegen instruction definitions
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<32> Inst;
  21   bit Trig = 0;
  22   bit Op3 = 0;
  23   bit isVector = 0;
  24
  25   let Inst = inst;
  26   let Namespace = "AMDIL";
  27   let OutOperandList = outs;
  28   let InOperandList = ins;
  29   let AsmString = asm;
  30   let Pattern = pattern;
  31   let Itinerary = itin;
  32
  33   let TSFlags{4} = Trig;
  34   let TSFlags{5} = Op3;
  35
  36   // Vector instructions are instructions that must fill all slots in an
  37   // instruction group
  38   let TSFlags{6} = isVector;
  39 }
  40
  41 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  42     AMDGPUInst <outs, ins, asm, pattern>
  43 {
  44   field bits<64> Inst;
  45
  46   let Namespace = "AMDIL";
  47 }
  48
  49 def MEMxi : Operand<iPTR> {
  50   let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
  51 }
  52
  53 def MEMrr : Operand<iPTR> {
  54   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  55 }
  56
  57 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  58 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
  59 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
  60
  61 class R600_ALU {
  62
  63   bits<7> DST_GPR = 0;
  64   bits<9> SRC0_SEL = 0;
  65   bits<1> SRC0_NEG = 0;
  66   bits<9> SRC1_SEL = 0;
  67   bits<1> SRC1_NEG = 0;
  68   bits<1> CLAMP = 0;
  69
  70 }
  71
  72
  73 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
  74                 InstrItinClass itin = AnyALU> :
  75   InstR600 <inst,
  76           (outs R600_Reg32:$dst),
  77           (ins R600_Reg32:$src, variable_ops),
  78           !strconcat(opName, " $dst, $src"),
  79           pattern,
  80           itin
  81   >;
  82
  83 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
  84                 InstrItinClass itin = AnyALU> :
  85   InstR600 <inst,
  86           (outs R600_Reg32:$dst),
  87           (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
  88           !strconcat(opName, " $dst, $src0, $src1"),
  89           pattern,
  90           itin
  91   >;
  92
  93 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
  94                 InstrItinClass itin = AnyALU> :
  95   InstR600 <inst,
  96           (outs R600_Reg32:$dst),
  97           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
  98           !strconcat(opName, " $dst, $src0, $src1, $src2"),
  99           pattern,
 100           itin>{
 101
 102     let Op3 = 1;
 103   }
 104
 105 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
 106                       InstrItinClass itin = VecALU> :
 107   InstR600 <inst,
 108           (outs R600_Reg32:$dst),
 109           ins,
 110           asm,
 111           pattern,
 112           itin
 113
 114   >;
 115
 116 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
 117                 InstrItinClass itin = AnyALU> :
 118   InstR600 <inst,
 119           (outs R600_Reg128:$dst),
 120           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 121           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 122           pattern,
 123           itin
 124   >;
 125
 126 def TEX_SHADOW : PatLeaf<
 127   (imm),
 128   [{uint32_t TType = (uint32_t)N->getZExtValue();
 129     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 130   }]
 131 >;
 132
 133 def COND_EQ : PatLeaf <
 134   (cond),
 135   [{switch(N->get()){{default: return false;
 136                      case ISD::SETOEQ: case ISD::SETUEQ:
 137                      case ISD::SETEQ: return true;}}}]
 138 >;
 139
 140 def COND_NE : PatLeaf <
 141   (cond),
 142   [{switch(N->get()){{default: return false;
 143                      case ISD::SETONE: case ISD::SETUNE:
 144                      case ISD::SETNE: return true;}}}]
 145 >;
 146 def COND_GT : PatLeaf <
 147   (cond),
 148   [{switch(N->get()){{default: return false;
 149                      case ISD::SETOGT: case ISD::SETUGT:
 150                      case ISD::SETGT: return true;}}}]
 151 >;
 152
 153 def COND_GE : PatLeaf <
 154   (cond),
 155   [{switch(N->get()){{default: return false;
 156                      case ISD::SETOGE: case ISD::SETUGE:
 157                      case ISD::SETGE: return true;}}}]
 158 >;
 159
 160 def COND_LT : PatLeaf <
 161   (cond),
 162   [{switch(N->get()){{default: return false;
 163                      case ISD::SETOLT: case ISD::SETULT:
 164                      case ISD::SETLT: return true;}}}]
 165 >;
 166
 167 def COND_LE : PatLeaf <
 168   (cond),
 169   [{switch(N->get()){{default: return false;
 170                      case ISD::SETOLE: case ISD::SETULE:
 171                      case ISD::SETLE: return true;}}}]
 172 >;
 173
 174 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
 175                  dag ins, string asm, list<dag> pattern> :
 176     InstR600ISA <outs, ins, asm, pattern>
 177 {
 178   bits<7>  RW_GPR;
 179   bits<7>  INDEX_GPR;
 180
 181   bits<2>  RIM;
 182   bits<2>  TYPE;
 183   bits<1>  RW_REL;
 184   bits<2>  ELEM_SIZE;
 185
 186   bits<12> ARRAY_SIZE;
 187   bits<4>  COMP_MASK;
 188   bits<4>  BURST_COUNT;
 189   bits<1>  VPM;
 190   bits<1>  EOP;
 191   bits<1>  MARK;
 192   bits<1>  BARRIER;
 193
 194   /* CF_ALLOC_EXPORT_WORD0_RAT */
 195   let Inst{3-0}   = rat_id;
 196   let Inst{9-4}   = rat_inst;
 197   let Inst{10}    = 0; /* Reserved */
 198   let Inst{12-11} = RIM;
 199   let Inst{14-13} = TYPE;
 200   let Inst{21-15} = RW_GPR;
 201   let Inst{22}    = RW_REL;
 202   let Inst{29-23} = INDEX_GPR;
 203   let Inst{31-30} = ELEM_SIZE;
 204
 205   /* CF_ALLOC_EXPORT_WORD1_BUF */
 206   let Inst{43-32} = ARRAY_SIZE;
 207   let Inst{47-44} = COMP_MASK;
 208   let Inst{51-48} = BURST_COUNT;
 209   let Inst{52}    = VPM;
 210   let Inst{53}    = EOP;
 211   let Inst{61-54} = cf_inst;
 212   let Inst{62}    = MARK;
 213   let Inst{63}    = BARRIER;
 214 }
 215
 216 /*
 217 def store_global : PatFrag<(ops node:$value, node:$ptr),
 218                            (store node:$value, node:$ptr),
 219                            [{
 220                             const Value *Src;
 221                             const PointerType *Type;
 222                             if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
 223                                  PT = dyn_cast<PointerType>(Src->getType()))) {
 224                               return PT->getAddressSpace() == 1;
 225                             }
 226                             return false;
 227                            }]>;
 228
 229 */
 230
 231 def load_param : PatFrag<(ops node:$ptr),
 232                          (load node:$ptr),
 233                           [{
 234                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 235                            if (Src) {
 236                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 237                                 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
 238                            }
 239                            return false;
 240                           }]>;
 241
 242 //class EG_CF <bits<32> inst, string asm> :
 243 //    InstR600 <inst, (outs), (ins), asm, []>;
 244
 245 /* XXX: We will use this when we emit the real ISA.
 246   bits<24> ADDR = 0;
 247   bits<3> JTS = 0;
 248
 249   bits<3> PC = 0;
 250   bits<5> CF_CONS = 0;
 251   bits<2> COND = 0;
 252   bits<6> COUNT = 0;
 253   bits<1> VPM = 0;
 254   bits<1> EOP = 0;
 255   bits<8> CF_INST = 0;
 256   bits<1> WQM = 0;
 257   bits<1> B = 0;
 258
 259   let Inst{23-0} = ADDR;
 260   let Inst{26-24} = JTS;
 261   let Inst{34-32} = PC;
 262   let Inst{39-35} = CF_CONST;
 263   let Inst{41-40} = COND;
 264   let Inst{47-42} = COUNT;
 265   let Inst{52} = VPM;
 266   let Inst{53} = EOP;
 267   let Inst{61-54} = CF_INST;
 268   let Inst{62} = WQM;
 269   let Inst{63} = B;
 270 //}
 271 */
 272 def isR600 : Predicate<"Subtarget.device()"
 273                             "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
 274 def isEG : Predicate<"Subtarget.device()"
 275                             "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
 276                             "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 277 def isCayman : Predicate<"Subtarget.device()"
 278                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 279 def isEGorCayman : Predicate<"Subtarget.device()"
 280                             "->getGeneration() == AMDILDeviceInfo::HD5XXX"
 281                             "|| Subtarget.device()->getGeneration() =="
 282                             "AMDILDeviceInfo::HD6XXX">;
 283
 284 def isR600toCayman : Predicate<
 285                      "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
 286
 287
 288 let Predicates = [isR600toCayman] in {
 289
 290 /* ------------------------------------------- */
 291 /* Common Instructions R600, R700, Evergreen, Cayman */
 292 /* ------------------------------------------- */
 293 def ADD : R600_2OP <
 294   0x0, "ADD",
 295   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
 296 >;
 297
 298 // Non-IEEE MUL: 0 * anything = 0
 299 def MUL : R600_2OP <
 300   0x1, "MUL NON-IEEE",
 301   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 302 >;
 303
 304 def MUL_IEEE : R600_2OP <
 305   0x2, "MUL_IEEE",
 306   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
 307 >;
 308
 309 def MAX : R600_2OP <
 310   0x3, "MAX",
 311   [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
 312 >;
 313
 314 def MIN : R600_2OP <
 315   0x4, "MIN",
 316   [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
 317 >;
 318
 319 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 320  * so some of the instruction names don't match the asm string.
 321  * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 322  */
 323
 324 def SETE : R600_2OP <
 325   0x08, "SETE",
 326   [(set R600_Reg32:$dst,
 327    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 328              COND_EQ))]
 329 >;
 330
 331 def SGT : R600_2OP <
 332   0x09, "SETGT",
 333   [(set R600_Reg32:$dst,
 334    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 335               COND_GT))]
 336 >;
 337
 338 def SGE : R600_2OP <
 339   0xA, "SETGE",
 340   [(set R600_Reg32:$dst,
 341    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 342               COND_GE))]
 343 >;
 344
 345 def SNE : R600_2OP <
 346   0xB, "SETNE",
 347   [(set R600_Reg32:$dst,
 348    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 349     COND_NE))]
 350 >;
 351
 352 def FRACT : R600_1OP <
 353   0x10, "FRACT",
 354   [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
 355 >;
 356
 357 def TRUNC : R600_1OP <
 358   0x11, "TRUNC",
 359   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 360 >;
 361
 362 def CEIL : R600_1OP <
 363   0x12, "CEIL",
 364   [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
 365 >;
 366
 367 def RNDNE : R600_1OP <
 368   0x13, "RNDNE",
 369   [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
 370 >;
 371
 372 def FLOOR : R600_1OP <
 373   0x14, "FLOOR",
 374   [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
 375 >;
 376
 377 def MOV : R600_1OP <0x19, "MOV", []>;
 378
 379 class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
 380   (outs R600_Reg32:$dst),
 381   (ins R600_Reg32:$alu_literal, immType:$imm),
 382   "MOV_IMM $dst, $imm",
 383   [], AnyALU
 384 >;
 385
 386 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
 387 def : Pat <
 388   (imm:$val),
 389   (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
 390 >;
 391
 392 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
 393 def : Pat <
 394   (fpimm:$val),
 395   (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
 396 >;
 397
 398 def KILLGT : R600_2OP <
 399   0x2D, "KILLGT",
 400   []
 401 >;
 402
 403 def AND_INT : R600_2OP <
 404   0x30, "AND_INT",
 405   [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
 406 >;
 407
 408 def OR_INT : R600_2OP <
 409   0x31, "OR_INT",
 410   [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
 411 >;
 412
 413 def XOR_INT : R600_2OP <
 414   0x32, "XOR_INT",
 415   [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
 416 >;
 417
 418 def NOT_INT : R600_1OP <
 419   0x33, "NOT_INT",
 420   [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
 421 >;
 422
 423 def ADD_INT : R600_2OP <
 424   0x34, "ADD_INT",
 425   [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
 426 >;
 427
 428 def SUB_INT : R600_2OP <
 429         0x35, "SUB_INT",
 430         [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
 431 >;
 432
 433 def MAX_INT : R600_2OP <
 434   0x36, "MAX_INT",
 435   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 436
 437 def MIN_INT : R600_2OP <
 438   0x37, "MIN_INT",
 439   [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 440
 441 def MAX_UINT : R600_2OP <
 442   0x38, "MAX_UINT",
 443   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
 444 >;
 445
 446 def MIN_UINT : R600_2OP <
 447   0x39, "MIN_UINT",
 448   [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
 449 >;
 450
 451 def SETE_INT : R600_2OP <
 452   0x3A, "SETE_INT",
 453   [(set (i32 R600_Reg32:$dst),
 454    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
 455 >;
 456
 457 def SETGT_INT : R600_2OP <
 458   0x3B, "SGT_INT",
 459   [(set (i32 R600_Reg32:$dst),
 460    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
 461 >;
 462
 463 def SETGE_INT : R600_2OP <
 464         0x3C, "SETGE_INT",
 465         [(set (i32 R600_Reg32:$dst),
 466    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
 467 >;
 468
 469 def SETNE_INT : R600_2OP <
 470   0x3D, "SETNE_INT",
 471   [(set (i32 R600_Reg32:$dst),
 472    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
 473 >;
 474
 475 def SETGT_UINT : R600_2OP <
 476   0x3E, "SETGT_UINT",
 477   [(set (i32 R600_Reg32:$dst),
 478    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
 479 >;
 480
 481 def SETGE_UINT : R600_2OP <
 482   0x3F, "SETGE_UINT",
 483   [(set (i32 R600_Reg32:$dst),
 484     (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
 485 >;
 486
 487 def CNDE_INT : R600_3OP <
 488         0x1C, "CNDE_INT",
 489   [(set (i32 R600_Reg32:$dst),
 490    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 491 >;
 492
 493 /* Texture instructions */
 494
 495
 496 def TEX_LD : R600_TEX <
 497   0x03, "TEX_LD",
 498   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
 499 > {
 500 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
 501 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
 502 }
 503
 504 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 505   0x04, "TEX_GET_TEXTURE_RESINFO",
 506   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 507 >;
 508
 509 def TEX_GET_GRADIENTS_H : R600_TEX <
 510   0x07, "TEX_GET_GRADIENTS_H",
 511   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 512 >;
 513
 514 def TEX_GET_GRADIENTS_V : R600_TEX <
 515   0x08, "TEX_GET_GRADIENTS_V",
 516   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 517 >;
 518
 519 def TEX_SET_GRADIENTS_H : R600_TEX <
 520   0x0B, "TEX_SET_GRADIENTS_H",
 521   []
 522 >;
 523
 524 def TEX_SET_GRADIENTS_V : R600_TEX <
 525   0x0C, "TEX_SET_GRADIENTS_V",
 526   []
 527 >;
 528
 529 def TEX_SAMPLE : R600_TEX <
 530   0x10, "TEX_SAMPLE",
 531   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 532 >;
 533
 534 def TEX_SAMPLE_C : R600_TEX <
 535   0x18, "TEX_SAMPLE_C",
 536   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 537 >;
 538
 539 def TEX_SAMPLE_L : R600_TEX <
 540   0x11, "TEX_SAMPLE_L",
 541   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 542 >;
 543
 544 def TEX_SAMPLE_C_L : R600_TEX <
 545   0x19, "TEX_SAMPLE_C_L",
 546   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 547 >;
 548
 549 def TEX_SAMPLE_LB : R600_TEX <
 550   0x12, "TEX_SAMPLE_LB",
 551   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 552 >;
 553
 554 def TEX_SAMPLE_C_LB : R600_TEX <
 555   0x1A, "TEX_SAMPLE_C_LB",
 556   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 557 >;
 558
 559 def TEX_SAMPLE_G : R600_TEX <
 560   0x14, "TEX_SAMPLE_G",
 561   []
 562 >;
 563
 564 def TEX_SAMPLE_C_G : R600_TEX <
 565   0x1C, "TEX_SAMPLE_C_G",
 566   []
 567 >;
 568
 569 /* Helper classes for common instructions */
 570
 571 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
 572   inst, "MUL_LIT",
 573   []
 574 >;
 575
 576 class MULADD_Common <bits<32> inst> : R600_3OP <
 577   inst, "MULADD",
 578   [(set (f32 R600_Reg32:$dst),
 579    (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 580 >;
 581
 582 class CNDE_Common <bits<32> inst> : R600_3OP <
 583   inst, "CNDE",
 584   [(set (f32 R600_Reg32:$dst),
 585    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 586 >;
 587
 588 class CNDGT_Common <bits<32> inst> : R600_3OP <
 589   inst, "CNDGT",
 590   []
 591 >;
 592
 593 class CNDGE_Common <bits<32> inst> : R600_3OP <
 594   inst, "CNDGE",
 595   [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 596 >;
 597
 598 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
 599   inst,
 600   (ins R600_Reg128:$src0, R600_Reg128:$src1),
 601   "DOT4 $dst $src0, $src1",
 602   [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 603 >;
 604
 605 class CUBE_Common <bits<32> inst> : InstR600 <
 606   inst,
 607   (outs R600_Reg128:$dst),
 608   (ins R600_Reg128:$src),
 609   "CUBE $dst $src",
 610   [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 611   VecALU
 612 >;
 613
 614 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
 615   inst, "EXP_IEEE",
 616   [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
 617 >;
 618
 619 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
 620   inst, "FLT_TO_INT",
 621   [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))]
 622 >;
 623
 624 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 625   inst, "INT_TO_FLT",
 626   [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
 627 >;
 628
 629 class FLT_TO_UINT_Common <bits<32> inst> : R600_1OP <
 630   inst, "FLT_TO_UINT",
 631   [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))]
 632 >;
 633
 634 class UINT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 635   inst, "UINT_TO_FLT",
 636   [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))]
 637 >;
 638
 639 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 640   inst, "LOG_CLAMPED",
 641   []
 642 >;
 643
 644 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
 645   inst, "LOG_IEEE",
 646   [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
 647 >;
 648
 649 class LSHL_Common <bits<32> inst> : R600_2OP <
 650   inst, "LSHL $dst, $src0, $src1",
 651   [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
 652 >;
 653
 654 class LSHR_Common <bits<32> inst> : R600_2OP <
 655   inst, "LSHR $dst, $src0, $src1",
 656   [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
 657 >;
 658
 659 class ASHR_Common <bits<32> inst> : R600_2OP <
 660   inst, "ASHR $dst, $src0, $src1",
 661   [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
 662 >;
 663
 664 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
 665   inst, "MULHI_INT $dst, $src0, $src1",
 666   [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
 667 >;
 668
 669 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
 670   inst, "MULHI $dst, $src0, $src1",
 671   [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
 672 >;
 673
 674 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
 675   inst, "MULLO_INT $dst, $src0, $src1",
 676   [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
 677 >;
 678
 679 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
 680   inst, "MULLO_UINT $dst, $src0, $src1",
 681   []
 682 >;
 683
 684 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 685   inst, "RECIP_CLAMPED",
 686   []
 687 >;
 688
 689 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
 690   inst, "RECIP_IEEE",
 691   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
 692 >;
 693
 694 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
 695   inst, "RECIP_INT $dst, $src",
 696   [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))]
 697 >;
 698
 699 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
 700   inst, "RECIPSQRT_CLAMPED",
 701   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 702 >;
 703
 704 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 705   inst, "RECIPSQRT_IEEE",
 706   []
 707 >;
 708
 709 class SIN_Common <bits<32> inst> : R600_1OP <
 710   inst, "SIN",
 711   [(set R600_Reg32:$dst, (int_AMDIL_sin R600_Reg32:$src))]>{
 712   let Trig = 1;
 713 }
 714
 715 class COS_Common <bits<32> inst> : R600_1OP <
 716   inst, "COS",
 717   [(set R600_Reg32:$dst, (int_AMDIL_cos R600_Reg32:$src))]> {
 718   let Trig = 1;
 719 }
 720
 721 /* Helper patterns for complex intrinsics */
 722 /* -------------------------------------- */
 723
 724 class DIV_Common <InstR600 recip_ieee> : Pat<
 725   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 726   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 727 >;
 728
 729 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 730   (int_AMDGPU_ssg R600_Reg32:$src),
 731   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 732 >;
 733
 734 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 735   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 736   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 737 >;
 738
 739 /* ---------------------- */
 740 /* R600 / R700 Only Instructions */
 741 /* ---------------------- */
 742
 743 let Predicates = [isR600] in {
 744
 745   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 746   def MULADD_r600 : MULADD_Common<0x10>;
 747   def CNDE_r600 : CNDE_Common<0x18>;
 748   def CNDGT_r600 : CNDGT_Common<0x19>;
 749   def CNDGE_r600 : CNDGE_Common<0x1A>;
 750   def DOT4_r600 : DOT4_Common<0x50>;
 751   def CUBE_r600 : CUBE_Common<0x52>;
 752   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 753   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 754   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 755   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 756   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 757   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 758   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 759   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 760   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 761   def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
 762   def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
 763   def SIN_r600 : SIN_Common<0x6E>;
 764   def COS_r600 : COS_Common<0x6F>;
 765   def ASHR_r600 : ASHR_Common<0x70>;
 766   def LSHR_r600 : LSHR_Common<0x71>;
 767   def LSHL_r600 : LSHL_Common<0x72>;
 768   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 769   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 770   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 771   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 772   def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
 773
 774   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 775   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 776   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 777   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 778
 779 }
 780
 781 /* ----------------- */
 782 /* R700+ Trig helper */
 783 /* ----------------- */
 784
 785 /*
 786 class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
 787   (trig_inst R600_Reg32:$src),
 788   (trig_inst (fmul R600_Reg32:$src, (PI))))
 789 >;
 790 */
 791
 792 //===----------------------------------------------------------------------===//
 793 // Evergreen Only instructions
 794 //===----------------------------------------------------------------------===//
 795
 796 let Predicates = [isEG] in {
 797
 798 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 799
 800 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 801 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 802 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 803 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 804 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 805
 806 } // End Predicates = [isEG]
 807
 808 /* ------------------------------- */
 809 /* Evergreen / Cayman Instructions */
 810 /* ------------------------------- */
 811
 812 let Predicates = [isEGorCayman] in {
 813
 814 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
 815   (intr R600_Reg32:$src),
 816   (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
 817 >;
 818
 819   def MULADD_eg : MULADD_Common<0x14>;
 820   def ASHR_eg : ASHR_Common<0x15>;
 821   def LSHR_eg : LSHR_Common<0x16>;
 822   def LSHL_eg : LSHL_Common<0x17>;
 823   def CNDE_eg : CNDE_Common<0x19>;
 824   def CNDGT_eg : CNDGT_Common<0x1A>;
 825   def CNDGE_eg : CNDGE_Common<0x1B>;
 826   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 827   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 828   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 829   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 830   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 831   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 832   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 833   def SIN_eg : SIN_Common<0x8D>;
 834   def COS_eg : COS_Common<0x8E>;
 835   def DOT4_eg : DOT4_Common<0xBE>;
 836   def CUBE_eg : CUBE_Common<0xC0>;
 837
 838   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
 839   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
 840   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
 841   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 842
 843   def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
 844   def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
 845
 846   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
 847     let Pattern = [];
 848   }
 849
 850   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
 851
 852   def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
 853     let Pattern = [];
 854   }
 855
 856   def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
 857
 858   def : Pat<(fp_to_sint R600_Reg32:$src),
 859     (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
 860
 861   def : Pat<(fp_to_uint R600_Reg32:$src),
 862     (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
 863
 864 //===----------------------------------------------------------------------===//
 865 // Memory read/write instructions
 866 //===----------------------------------------------------------------------===//
 867
 868 let usesCustomInserter = 1 in {
 869
 870 def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
 871   (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
 872   "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr",
 873   [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]>
 874 {
 875   let RIM         = 0;
 876   /* XXX: Have a separate instruction for non-indexed writes. */
 877   let TYPE        = 1;
 878   let RW_REL      = 0;
 879   let ELEM_SIZE   = 0;
 880
 881   let ARRAY_SIZE  = 0;
 882   let COMP_MASK   = 1;
 883   let BURST_COUNT = 0;
 884   let VPM         = 0;
 885   let EOP         = 0;
 886   let MARK        = 0;
 887   let BARRIER     = 1;
 888 }
 889
 890 } // End usesCustomInserter = 1
 891
 892 class VTX_READ_eg <int buffer_id, list<dag> pattern> : InstR600ISA <
 893   (outs R600_TReg32_X:$dst),
 894   (ins MEMxi:$ptr),
 895   "VTX_READ_eg $dst, $ptr",
 896   pattern
 897 >;
 898
 899 def VTX_READ_PARAM_eg : VTX_READ_eg <0,
 900   [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
 901 >;
 902
 903 def VTX_READ_GLOBAL_eg : VTX_READ_eg <1,
 904   [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
 905 >;
 906
 907 }
 908
 909 let Predicates = [isCayman] in {
 910
 911 let isVector = 1 in {
 912
 913 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
 914
 915 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
 916 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
 917 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
 918 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
 919
 920 } // End isVector = 1
 921
 922 // RECIP_UINT emulation for Cayman
 923 def : Pat <
 924   (AMDGPUurecip R600_Reg32:$src0),
 925   (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
 926                             (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000)))
 927 >;
 928
 929 } // End isCayman
 930
 931 /* Other Instructions */
 932
 933 let isCodeGenOnly = 1 in {
 934 /*
 935   def SWIZZLE : AMDGPUShaderInst <
 936     (outs GPRV4F32:$dst),
 937     (ins GPRV4F32:$src0, i32imm:$src1),
 938     "SWIZZLE $dst, $src0, $src1",
 939     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
 940   >;
 941 */
 942
 943   def LAST : AMDGPUShaderInst <
 944     (outs),
 945     (ins),
 946     "LAST",
 947     []
 948   >;
 949
 950   def GET_CHAN : AMDGPUShaderInst <
 951     (outs R600_Reg32:$dst),
 952     (ins R600_Reg128:$src0, i32imm:$src1),
 953     "GET_CHAN $dst, $src0, $src1",
 954     []
 955   >;
 956
 957   def MULLIT : AMDGPUShaderInst <
 958     (outs R600_Reg128:$dst),
 959     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
 960     "MULLIT $dst, $src0, $src1",
 961     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 962   >;
 963
 964 let usesCustomInserter = 1, isPseudo = 1 in {
 965
 966 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
 967   (outs R600_TReg32:$dst),
 968   (ins),
 969   asm,
 970   [(set R600_TReg32:$dst, (intr))]
 971 >;
 972
 973 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
 974 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
 975 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
 976
 977 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
 978 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
 979 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
 980
 981 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
 982 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
 983 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
 984
 985 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
 986                                      int_r600_read_global_size_x>;
 987 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
 988                                      int_r600_read_global_size_y>;
 989 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
 990                                      int_r600_read_global_size_z>;
 991
 992 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
 993                                     int_r600_read_local_size_x>;
 994 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
 995                                     int_r600_read_local_size_y>;
 996 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
 997                                     int_r600_read_local_size_z>;
 998
 999 def R600_LOAD_CONST : AMDGPUShaderInst <
1000   (outs R600_Reg32:$dst),
1001   (ins i32imm:$src0),
1002   "R600_LOAD_CONST $dst, $src0",
1003   [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1004 >;
1005
1006 def LOAD_INPUT : AMDGPUShaderInst <
1007   (outs R600_Reg32:$dst),
1008   (ins i32imm:$src),
1009   "LOAD_INPUT $dst, $src",
1010   [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1011 >;
1012
1013 def RESERVE_REG : AMDGPUShaderInst <
1014   (outs),
1015   (ins i32imm:$src),
1016   "RESERVE_REG $src",
1017   [(int_AMDGPU_reserve_reg imm:$src)]
1018 >;
1019
1020 def STORE_OUTPUT: AMDGPUShaderInst <
1021   (outs),
1022   (ins R600_Reg32:$src0, i32imm:$src1),
1023   "STORE_OUTPUT $src0, $src1",
1024   [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1025 >;
1026
1027 def TXD: AMDGPUShaderInst <
1028   (outs R600_Reg128:$dst),
1029   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1030   "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1031   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1032 >;
1033
1034 def TXD_SHADOW: AMDGPUShaderInst <
1035   (outs R600_Reg128:$dst),
1036   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1037   "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1038   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1039 >;
1040
1041 } // End usesCustomInserter = 1, isPseudo = 1
1042
1043 } // End isCodeGenOnly = 1
1044
1045 def CLAMP_R600 :  CLAMP <R600_Reg32>;
1046 def FABS_R600 : FABS<R600_Reg32>;
1047 def FNEG_R600 : FNEG<R600_Reg32>;
1048
1049 let usesCustomInserter = 1 in {
1050
1051 def MASK_WRITE : AMDGPUShaderInst <
1052     (outs),
1053     (ins R600_Reg32:$src),
1054     "MASK_WRITE $src",
1055     []
1056 >;
1057
1058 } // End usesCustomInserter = 1
1059
1060 //===----------------------------------------------------------------------===//
1061 // ISel Patterns
1062 //===----------------------------------------------------------------------===//
1063
1064 // KIL Patterns
1065 def KILP : Pat <
1066   (int_AMDGPU_kilp),
1067   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1068 >;
1069
1070 def KIL : Pat <
1071   (int_AMDGPU_kill R600_Reg32:$src0),
1072   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
1073 >;
1074
1075 // SGT Reverse args
1076 def : Pat <
1077   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1078   (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1079 >;
1080
1081 // SGE Reverse args
1082 def : Pat <
1083   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1084   (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1085 >;
1086
1087 // SETGT_INT reverse args
1088 def : Pat <
1089   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1090   (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1091 >;
1092
1093 // SETGE_INT reverse args
1094 def : Pat <
1095   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1096   (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1097 >;
1098
1099 // SETGT_UINT reverse args
1100 def : Pat <
1101   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1102   (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1103 >;
1104
1105 // SETGE_UINT reverse args
1106 def : Pat <
1107   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1108   (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1109 >;
1110
1111 // The next two patterns are special cases for handling 'true if ordered' and
1112 // 'true if unordered' conditionals.  The assumption here is that the behavior of
1113 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1114 // described here:
1115 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1116 // We assume that  SETE returns false when one of the operands is NAN and
1117 // SNE returns true when on of the operands is NAN
1118
1119 //SETE - 'true if ordered'
1120 def : Pat <
1121   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1122   (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1123 >;
1124
1125 //SNE - 'true if unordered'
1126 def : Pat <
1127   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1128   (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1129 >;
1130
1131 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1132 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1133 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1134 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1135
1136 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1137 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1138 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1139 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1140
1141 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1142 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1143 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1144 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1145
1146 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1147 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1148 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1149 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1150
1151 def : Vector_Build <v4f32, R600_Reg32>;
1152 def : Vector_Build <v4i32, R600_Reg32>;
1153
1154 // bitconvert patterns
1155
1156 def : BitConvert <i32, f32, R600_Reg32>;
1157 def : BitConvert <f32, i32, R600_Reg32>;
1158
1159 } // End isR600toCayman Predicate