src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Tablegen instruction definitions
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<32> Inst;
  21   bit Trig = 0;
  22   bit Op3 = 0;
  23   bit isVector = 0;
  24
  25   let Inst = inst;
  26   let Namespace = "AMDGPU";
  27   let OutOperandList = outs;
  28   let InOperandList = ins;
  29   let AsmString = asm;
  30   let Pattern = pattern;
  31   let Itinerary = itin;
  32
  33   let TSFlags{4} = Trig;
  34   let TSFlags{5} = Op3;
  35
  36   // Vector instructions are instructions that must fill all slots in an
  37   // instruction group
  38   let TSFlags{6} = isVector;
  39 }
  40
  41 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  42     AMDGPUInst <outs, ins, asm, pattern>
  43 {
  44   field bits<64> Inst;
  45
  46   let Namespace = "AMDGPU";
  47 }
  48
  49 def MEMxi : Operand<iPTR> {
  50   let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
  51 }
  52
  53 def MEMrr : Operand<iPTR> {
  54   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  55 }
  56
  57 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  58 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
  59 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
  60
  61 class R600_ALU {
  62
  63   bits<7> DST_GPR = 0;
  64   bits<9> SRC0_SEL = 0;
  65   bits<1> SRC0_NEG = 0;
  66   bits<9> SRC1_SEL = 0;
  67   bits<1> SRC1_NEG = 0;
  68   bits<1> CLAMP = 0;
  69
  70 }
  71
  72 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
  73                                      (ops PRED_SEL_OFF)>;
  74
  75
  76 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
  77                 InstrItinClass itin = AnyALU> :
  78   InstR600 <inst,
  79           (outs R600_Reg32:$dst),
  80           (ins R600_Reg32:$src, R600_Pred:$p, variable_ops),
  81           !strconcat(opName, " $dst, $src ($p)"),
  82           pattern,
  83           itin
  84   >;
  85
  86 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
  87                 InstrItinClass itin = AnyALU> :
  88   InstR600 <inst,
  89           (outs R600_Reg32:$dst),
  90           (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops),
  91           !strconcat(opName, " $dst, $src0, $src1"),
  92           pattern,
  93           itin
  94   >;
  95
  96 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
  97                 InstrItinClass itin = AnyALU> :
  98   InstR600 <inst,
  99           (outs R600_Reg32:$dst),
 100           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops),
 101           !strconcat(opName, " $dst, $src0, $src1, $src2"),
 102           pattern,
 103           itin>{
 104
 105     let Op3 = 1;
 106   }
 107
 108
 109
 110 def PRED_X : AMDGPUInst <(outs R600_Predicate_Bit:$dst),
 111            (ins R600_Reg32:$src0, i32imm:$src1),
 112            "PRED $dst, $src0, $src1",
 113            []>
 114 {
 115   let DisableEncoding = "$src0";
 116   field bits<32> Inst;
 117   bits<32> src1;
 118
 119   let Inst = src1;
 120 }
 121
 122
 123
 124 let isTerminator = 1, isBranch = 1 in {
 125 def JUMP : InstR600 <0x10,
 126           (outs),
 127           (ins brtarget:$target, R600_Pred:$p),
 128           "JUMP $target ($p)",
 129           [], AnyALU
 130   >;
 131 }
 132
 133 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
 134                       InstrItinClass itin = VecALU> :
 135   InstR600 <inst,
 136           (outs R600_Reg32:$dst),
 137           ins,
 138           asm,
 139           pattern,
 140           itin
 141
 142   >;
 143
 144 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
 145                 InstrItinClass itin = AnyALU> :
 146   InstR600 <inst,
 147           (outs R600_Reg128:$dst),
 148           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 149           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 150           pattern,
 151           itin
 152   >;
 153
 154 def TEX_SHADOW : PatLeaf<
 155   (imm),
 156   [{uint32_t TType = (uint32_t)N->getZExtValue();
 157     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 158   }]
 159 >;
 160
 161 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
 162                  dag ins, string asm, list<dag> pattern> :
 163     InstR600ISA <outs, ins, asm, pattern>
 164 {
 165   bits<7>  RW_GPR;
 166   bits<7>  INDEX_GPR;
 167
 168   bits<2>  RIM;
 169   bits<2>  TYPE;
 170   bits<1>  RW_REL;
 171   bits<2>  ELEM_SIZE;
 172
 173   bits<12> ARRAY_SIZE;
 174   bits<4>  COMP_MASK;
 175   bits<4>  BURST_COUNT;
 176   bits<1>  VPM;
 177   bits<1>  EOP;
 178   bits<1>  MARK;
 179   bits<1>  BARRIER;
 180
 181   /* CF_ALLOC_EXPORT_WORD0_RAT */
 182   let Inst{3-0}   = rat_id;
 183   let Inst{9-4}   = rat_inst;
 184   let Inst{10}    = 0; /* Reserved */
 185   let Inst{12-11} = RIM;
 186   let Inst{14-13} = TYPE;
 187   let Inst{21-15} = RW_GPR;
 188   let Inst{22}    = RW_REL;
 189   let Inst{29-23} = INDEX_GPR;
 190   let Inst{31-30} = ELEM_SIZE;
 191
 192   /* CF_ALLOC_EXPORT_WORD1_BUF */
 193   let Inst{43-32} = ARRAY_SIZE;
 194   let Inst{47-44} = COMP_MASK;
 195   let Inst{51-48} = BURST_COUNT;
 196   let Inst{52}    = VPM;
 197   let Inst{53}    = EOP;
 198   let Inst{61-54} = cf_inst;
 199   let Inst{62}    = MARK;
 200   let Inst{63}    = BARRIER;
 201 }
 202
 203 /*
 204 def store_global : PatFrag<(ops node:$value, node:$ptr),
 205                            (store node:$value, node:$ptr),
 206                            [{
 207                             const Value *Src;
 208                             const PointerType *Type;
 209                             if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
 210                                  PT = dyn_cast<PointerType>(Src->getType()))) {
 211                               return PT->getAddressSpace() == 1;
 212                             }
 213                             return false;
 214                            }]>;
 215
 216 */
 217
 218 def load_param : PatFrag<(ops node:$ptr),
 219                          (load node:$ptr),
 220                           [{
 221                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 222                            if (Src) {
 223                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 224                                 return PT && PT->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS;
 225                            }
 226                            return false;
 227                           }]>;
 228
 229 //class EG_CF <bits<32> inst, string asm> :
 230 //    InstR600 <inst, (outs), (ins), asm, []>;
 231
 232 /* XXX: We will use this when we emit the real ISA.
 233   bits<24> ADDR = 0;
 234   bits<3> JTS = 0;
 235
 236   bits<3> PC = 0;
 237   bits<5> CF_CONS = 0;
 238   bits<2> COND = 0;
 239   bits<6> COUNT = 0;
 240   bits<1> VPM = 0;
 241   bits<1> EOP = 0;
 242   bits<8> CF_INST = 0;
 243   bits<1> WQM = 0;
 244   bits<1> B = 0;
 245
 246   let Inst{23-0} = ADDR;
 247   let Inst{26-24} = JTS;
 248   let Inst{34-32} = PC;
 249   let Inst{39-35} = CF_CONST;
 250   let Inst{41-40} = COND;
 251   let Inst{47-42} = COUNT;
 252   let Inst{52} = VPM;
 253   let Inst{53} = EOP;
 254   let Inst{61-54} = CF_INST;
 255   let Inst{62} = WQM;
 256   let Inst{63} = B;
 257 //}
 258 */
 259 def isR600 : Predicate<"Subtarget.device()"
 260                             "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
 261 def isR700 : Predicate<"Subtarget.device()"
 262                             "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
 263                             "Subtarget.device()->getDeviceFlag()"
 264                             ">= OCL_DEVICE_RV710">;
 265 def isEG : Predicate<"Subtarget.device()"
 266                             "->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
 267                             "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 268 def isCayman : Predicate<"Subtarget.device()"
 269                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 270 def isEGorCayman : Predicate<"Subtarget.device()"
 271                             "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
 272                             "|| Subtarget.device()->getGeneration() =="
 273                             "AMDGPUDeviceInfo::HD6XXX">;
 274
 275 def isR600toCayman : Predicate<
 276                      "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
 277
 278
 279 let Predicates = [isR600toCayman] in {
 280
 281 /* ------------------------------------------- */
 282 /* Common Instructions R600, R700, Evergreen, Cayman */
 283 /* ------------------------------------------- */
 284 def ADD : R600_2OP <
 285   0x0, "ADD",
 286   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
 287 >;
 288
 289 // Non-IEEE MUL: 0 * anything = 0
 290 def MUL : R600_2OP <
 291   0x1, "MUL NON-IEEE",
 292   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 293 >;
 294
 295 def MUL_IEEE : R600_2OP <
 296   0x2, "MUL_IEEE",
 297   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
 298 >;
 299
 300 def MAX : R600_2OP <
 301   0x3, "MAX",
 302   [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
 303 >;
 304
 305 def MIN : R600_2OP <
 306   0x4, "MIN",
 307   [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
 308 >;
 309
 310 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 311  * so some of the instruction names don't match the asm string.
 312  * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 313  */
 314
 315 def SETE : R600_2OP <
 316   0x08, "SETE",
 317   [(set R600_Reg32:$dst,
 318    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 319              COND_EQ))]
 320 >;
 321
 322 def SGT : R600_2OP <
 323   0x09, "SETGT",
 324   [(set R600_Reg32:$dst,
 325    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 326               COND_GT))]
 327 >;
 328
 329 def SGE : R600_2OP <
 330   0xA, "SETGE",
 331   [(set R600_Reg32:$dst,
 332    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 333               COND_GE))]
 334 >;
 335
 336 def SNE : R600_2OP <
 337   0xB, "SETNE",
 338   [(set R600_Reg32:$dst,
 339    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 340     COND_NE))]
 341 >;
 342
 343 def FRACT : R600_1OP <
 344   0x10, "FRACT",
 345   [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
 346 >;
 347
 348 def TRUNC : R600_1OP <
 349   0x11, "TRUNC",
 350   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 351 >;
 352
 353 def CEIL : R600_1OP <
 354   0x12, "CEIL",
 355   [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
 356 >;
 357
 358 def RNDNE : R600_1OP <
 359   0x13, "RNDNE",
 360   [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
 361 >;
 362
 363 def FLOOR : R600_1OP <
 364   0x14, "FLOOR",
 365   [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
 366 >;
 367
 368 def MOV : R600_1OP <0x19, "MOV", []>;
 369
 370 class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
 371   (outs R600_Reg32:$dst),
 372   (ins R600_Reg32:$alu_literal, R600_Pred:$p, immType:$imm),
 373   "MOV_IMM $dst, $imm",
 374   [], AnyALU
 375 >;
 376
 377 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
 378 def : Pat <
 379   (imm:$val),
 380   (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
 381 >;
 382
 383 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
 384 def : Pat <
 385   (fpimm:$val),
 386   (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
 387 >;
 388
 389 def KILLGT : R600_2OP <
 390   0x2D, "KILLGT",
 391   []
 392 >;
 393
 394 def AND_INT : R600_2OP <
 395   0x30, "AND_INT",
 396   [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
 397 >;
 398
 399 def OR_INT : R600_2OP <
 400   0x31, "OR_INT",
 401   [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
 402 >;
 403
 404 def XOR_INT : R600_2OP <
 405   0x32, "XOR_INT",
 406   [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
 407 >;
 408
 409 def NOT_INT : R600_1OP <
 410   0x33, "NOT_INT",
 411   [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
 412 >;
 413
 414 def ADD_INT : R600_2OP <
 415   0x34, "ADD_INT",
 416   [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
 417 >;
 418
 419 def SUB_INT : R600_2OP <
 420         0x35, "SUB_INT",
 421         [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
 422 >;
 423
 424 def MAX_INT : R600_2OP <
 425   0x36, "MAX_INT",
 426   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 427
 428 def MIN_INT : R600_2OP <
 429   0x37, "MIN_INT",
 430   [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 431
 432 def MAX_UINT : R600_2OP <
 433   0x38, "MAX_UINT",
 434   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
 435 >;
 436
 437 def MIN_UINT : R600_2OP <
 438   0x39, "MIN_UINT",
 439   [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
 440 >;
 441
 442 def SETE_INT : R600_2OP <
 443   0x3A, "SETE_INT",
 444   [(set (i32 R600_Reg32:$dst),
 445    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
 446 >;
 447
 448 def SETGT_INT : R600_2OP <
 449   0x3B, "SGT_INT",
 450   [(set (i32 R600_Reg32:$dst),
 451    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
 452 >;
 453
 454 def SETGE_INT : R600_2OP <
 455         0x3C, "SETGE_INT",
 456         [(set (i32 R600_Reg32:$dst),
 457    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
 458 >;
 459
 460 def SETNE_INT : R600_2OP <
 461   0x3D, "SETNE_INT",
 462   [(set (i32 R600_Reg32:$dst),
 463    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
 464 >;
 465
 466 def SETGT_UINT : R600_2OP <
 467   0x3E, "SETGT_UINT",
 468   [(set (i32 R600_Reg32:$dst),
 469    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
 470 >;
 471
 472 def SETGE_UINT : R600_2OP <
 473   0x3F, "SETGE_UINT",
 474   [(set (i32 R600_Reg32:$dst),
 475     (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
 476 >;
 477
 478 def CNDE_INT : R600_3OP <
 479         0x1C, "CNDE_INT",
 480   [(set (i32 R600_Reg32:$dst),
 481    (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 482 >;
 483
 484 /* Texture instructions */
 485
 486
 487 def TEX_LD : R600_TEX <
 488   0x03, "TEX_LD",
 489   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
 490 > {
 491 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
 492 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
 493 }
 494
 495 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 496   0x04, "TEX_GET_TEXTURE_RESINFO",
 497   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 498 >;
 499
 500 def TEX_GET_GRADIENTS_H : R600_TEX <
 501   0x07, "TEX_GET_GRADIENTS_H",
 502   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 503 >;
 504
 505 def TEX_GET_GRADIENTS_V : R600_TEX <
 506   0x08, "TEX_GET_GRADIENTS_V",
 507   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 508 >;
 509
 510 def TEX_SET_GRADIENTS_H : R600_TEX <
 511   0x0B, "TEX_SET_GRADIENTS_H",
 512   []
 513 >;
 514
 515 def TEX_SET_GRADIENTS_V : R600_TEX <
 516   0x0C, "TEX_SET_GRADIENTS_V",
 517   []
 518 >;
 519
 520 def TEX_SAMPLE : R600_TEX <
 521   0x10, "TEX_SAMPLE",
 522   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 523 >;
 524
 525 def TEX_SAMPLE_C : R600_TEX <
 526   0x18, "TEX_SAMPLE_C",
 527   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 528 >;
 529
 530 def TEX_SAMPLE_L : R600_TEX <
 531   0x11, "TEX_SAMPLE_L",
 532   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 533 >;
 534
 535 def TEX_SAMPLE_C_L : R600_TEX <
 536   0x19, "TEX_SAMPLE_C_L",
 537   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 538 >;
 539
 540 def TEX_SAMPLE_LB : R600_TEX <
 541   0x12, "TEX_SAMPLE_LB",
 542   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 543 >;
 544
 545 def TEX_SAMPLE_C_LB : R600_TEX <
 546   0x1A, "TEX_SAMPLE_C_LB",
 547   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 548 >;
 549
 550 def TEX_SAMPLE_G : R600_TEX <
 551   0x14, "TEX_SAMPLE_G",
 552   []
 553 >;
 554
 555 def TEX_SAMPLE_C_G : R600_TEX <
 556   0x1C, "TEX_SAMPLE_C_G",
 557   []
 558 >;
 559
 560 /* Helper classes for common instructions */
 561
 562 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
 563   inst, "MUL_LIT",
 564   []
 565 >;
 566
 567 class MULADD_Common <bits<32> inst> : R600_3OP <
 568   inst, "MULADD",
 569   [(set (f32 R600_Reg32:$dst),
 570    (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 571 >;
 572
 573 class CNDE_Common <bits<32> inst> : R600_3OP <
 574   inst, "CNDE",
 575   [(set (f32 R600_Reg32:$dst),
 576    (select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)))]
 577 >;
 578
 579 class CNDGT_Common <bits<32> inst> : R600_3OP <
 580   inst, "CNDGT",
 581   []
 582 >;
 583
 584 class CNDGE_Common <bits<32> inst> : R600_3OP <
 585   inst, "CNDGE",
 586   [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 587 >;
 588
 589 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
 590   inst,
 591   (ins R600_Reg128:$src0, R600_Reg128:$src1),
 592   "DOT4 $dst $src0, $src1",
 593   [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 594 >;
 595
 596 class CUBE_Common <bits<32> inst> : InstR600 <
 597   inst,
 598   (outs R600_Reg128:$dst),
 599   (ins R600_Reg128:$src),
 600   "CUBE $dst $src",
 601   [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 602   VecALU
 603 >;
 604
 605 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
 606   inst, "EXP_IEEE",
 607   [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
 608 >;
 609
 610 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
 611   inst, "FLT_TO_INT",
 612   [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))]
 613 >;
 614
 615 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 616   inst, "INT_TO_FLT",
 617   [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
 618 >;
 619
 620 class FLT_TO_UINT_Common <bits<32> inst> : R600_1OP <
 621   inst, "FLT_TO_UINT",
 622   [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))]
 623 >;
 624
 625 class UINT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 626   inst, "UINT_TO_FLT",
 627   [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))]
 628 >;
 629
 630 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 631   inst, "LOG_CLAMPED",
 632   []
 633 >;
 634
 635 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
 636   inst, "LOG_IEEE",
 637   [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
 638 >;
 639
 640 class LSHL_Common <bits<32> inst> : R600_2OP <
 641   inst, "LSHL $dst, $src0, $src1",
 642   [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
 643 >;
 644
 645 class LSHR_Common <bits<32> inst> : R600_2OP <
 646   inst, "LSHR $dst, $src0, $src1",
 647   [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
 648 >;
 649
 650 class ASHR_Common <bits<32> inst> : R600_2OP <
 651   inst, "ASHR $dst, $src0, $src1",
 652   [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
 653 >;
 654
 655 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
 656   inst, "MULHI_INT $dst, $src0, $src1",
 657   [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
 658 >;
 659
 660 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
 661   inst, "MULHI $dst, $src0, $src1",
 662   [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
 663 >;
 664
 665 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
 666   inst, "MULLO_INT $dst, $src0, $src1",
 667   [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
 668 >;
 669
 670 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
 671   inst, "MULLO_UINT $dst, $src0, $src1",
 672   []
 673 >;
 674
 675 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 676   inst, "RECIP_CLAMPED",
 677   []
 678 >;
 679
 680 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
 681   inst, "RECIP_IEEE",
 682   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
 683 >;
 684
 685 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
 686   inst, "RECIP_INT $dst, $src",
 687   [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))]
 688 >;
 689
 690 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
 691   inst, "RECIPSQRT_CLAMPED",
 692   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 693 >;
 694
 695 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 696   inst, "RECIPSQRT_IEEE",
 697   []
 698 >;
 699
 700 class SIN_Common <bits<32> inst> : R600_1OP <
 701   inst, "SIN", []>{
 702   let Trig = 1;
 703 }
 704
 705 class COS_Common <bits<32> inst> : R600_1OP <
 706   inst, "COS", []> {
 707   let Trig = 1;
 708 }
 709
 710 /* Helper patterns for complex intrinsics */
 711 /* -------------------------------------- */
 712
 713 class DIV_Common <InstR600 recip_ieee> : Pat<
 714   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 715   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 716 >;
 717
 718 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 719   (int_AMDGPU_ssg R600_Reg32:$src),
 720   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 721 >;
 722
 723 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 724   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 725   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 726 >;
 727
 728 /* ---------------------- */
 729 /* R600 / R700 Only Instructions */
 730 /* ---------------------- */
 731
 732 let Predicates = [isR600] in {
 733
 734   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 735   def MULADD_r600 : MULADD_Common<0x10>;
 736   def CNDE_r600 : CNDE_Common<0x18>;
 737   def CNDGT_r600 : CNDGT_Common<0x19>;
 738   def CNDGE_r600 : CNDGE_Common<0x1A>;
 739   def DOT4_r600 : DOT4_Common<0x50>;
 740   def CUBE_r600 : CUBE_Common<0x52>;
 741   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 742   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 743   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 744   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 745   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 746   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 747   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 748   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 749   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 750   def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
 751   def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
 752   def SIN_r600 : SIN_Common<0x6E>;
 753   def COS_r600 : COS_Common<0x6F>;
 754   def ASHR_r600 : ASHR_Common<0x70>;
 755   def LSHR_r600 : LSHR_Common<0x71>;
 756   def LSHL_r600 : LSHL_Common<0x72>;
 757   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 758   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 759   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 760   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 761   def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
 762
 763   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 764   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 765   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 766   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 767
 768 }
 769
 770 // Helper pattern for normalizing inputs to triginomic instructions for R700+
 771 // cards.
 772 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
 773   (intr R600_Reg32:$src),
 774   (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
 775 >;
 776
 777 //===----------------------------------------------------------------------===//
 778 // R700 Only instructions
 779 //===----------------------------------------------------------------------===//
 780
 781 let Predicates = [isR700] in {
 782   def SIN_r700 : SIN_Common<0x6E>;
 783   def COS_r700 : COS_Common<0x6F>;
 784
 785   // R700 normalizes inputs to SIN/COS the same as EG
 786   def : TRIG_eg <SIN_r700, int_AMDGPU_sin>;
 787   def : TRIG_eg <COS_r700, int_AMDGPU_cos>;
 788 }
 789
 790 //===----------------------------------------------------------------------===//
 791 // Evergreen Only instructions
 792 //===----------------------------------------------------------------------===//
 793
 794 let Predicates = [isEG] in {
 795
 796 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 797
 798 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 799 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 800 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 801 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 802 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 803
 804 } // End Predicates = [isEG]
 805
 806 /* ------------------------------- */
 807 /* Evergreen / Cayman Instructions */
 808 /* ------------------------------- */
 809
 810 let Predicates = [isEGorCayman] in {
 811
 812   // BFE_UINT - bit_extract, an optimization for mask and shift
 813   // Src0 = Input
 814   // Src1 = Offset
 815   // Src2 = Width
 816   //
 817   // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
 818   //
 819   // Example Usage:
 820   // (Offset, Width)
 821   //
 822   // (0, 8)           = (Input << 24) >> 24  = (Input &  0xff)       >> 0
 823   // (8, 8)           = (Input << 16) >> 24  = (Input &  0xffff)     >> 8
 824   // (16,8)           = (Input <<  8) >> 24  = (Input &  0xffffff)   >> 16
 825   // (24,8)           = (Input <<  0) >> 24  = (Input &  0xffffffff) >> 24
 826   def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
 827     [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
 828                                                       R600_Reg32:$src1,
 829                                                       R600_Reg32:$src2))],
 830     VecALU
 831   >;
 832
 833   def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
 834     [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
 835                                           R600_Reg32:$src2))],
 836     VecALU
 837   >;
 838
 839   def MULADD_eg : MULADD_Common<0x14>;
 840   def ASHR_eg : ASHR_Common<0x15>;
 841   def LSHR_eg : LSHR_Common<0x16>;
 842   def LSHL_eg : LSHL_Common<0x17>;
 843   def CNDE_eg : CNDE_Common<0x19>;
 844   def CNDGT_eg : CNDGT_Common<0x1A>;
 845   def CNDGE_eg : CNDGE_Common<0x1B>;
 846   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 847   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 848   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 849   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 850   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 851   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 852   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 853   def SIN_eg : SIN_Common<0x8D>;
 854   def COS_eg : COS_Common<0x8E>;
 855   def DOT4_eg : DOT4_Common<0xBE>;
 856   def CUBE_eg : CUBE_Common<0xC0>;
 857
 858   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
 859   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
 860   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
 861   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 862
 863   def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
 864   def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
 865
 866   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
 867     let Pattern = [];
 868   }
 869
 870   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
 871
 872   def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
 873     let Pattern = [];
 874   }
 875
 876   def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
 877
 878   def : Pat<(fp_to_sint R600_Reg32:$src),
 879     (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
 880
 881   def : Pat<(fp_to_uint R600_Reg32:$src),
 882     (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
 883
 884 //===----------------------------------------------------------------------===//
 885 // Memory read/write instructions
 886 //===----------------------------------------------------------------------===//
 887
 888 let usesCustomInserter = 1 in {
 889
 890 def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
 891   (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
 892   "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr",
 893   [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]>
 894 {
 895   let RIM         = 0;
 896   /* XXX: Have a separate instruction for non-indexed writes. */
 897   let TYPE        = 1;
 898   let RW_REL      = 0;
 899   let ELEM_SIZE   = 0;
 900
 901   let ARRAY_SIZE  = 0;
 902   let COMP_MASK   = 1;
 903   let BURST_COUNT = 0;
 904   let VPM         = 0;
 905   let EOP         = 0;
 906   let MARK        = 0;
 907   let BARRIER     = 1;
 908 }
 909
 910 } // End usesCustomInserter = 1
 911
 912 // Floating point global_store
 913 def : Pat <
 914   (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
 915   (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr)
 916 >;
 917
 918 class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>
 919     : InstR600ISA <outs, (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr", pattern> {
 920
 921   // Operands
 922   bits<7> DST_GPR;
 923   bits<7> SRC_GPR;
 924
 925   // Static fields
 926   bits<5> VC_INST = 0;
 927   bits<2> FETCH_TYPE = 2;
 928   bits<1> FETCH_WHOLE_QUAD = 0;
 929   bits<8> BUFFER_ID = buffer_id;
 930   bits<1> SRC_REL = 0;
 931   // XXX: We can infer this field based on the SRC_GPR.  This would allow us
 932   // to store vertex addresses in any channel, not just X.
 933   bits<2> SRC_SEL_X = 0;
 934   bits<6> MEGA_FETCH_COUNT;
 935   bits<1> DST_REL = 0;
 936   bits<3> DST_SEL_X;
 937   bits<3> DST_SEL_Y;
 938   bits<3> DST_SEL_Z;
 939   bits<3> DST_SEL_W;
 940   // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
 941   // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
 942   // however, based on my testing if USE_CONST_FIELDS is set, then all
 943   // these fields need to be set to 0.
 944   bits<1> USE_CONST_FIELDS = 0;
 945   bits<6> DATA_FORMAT;
 946   bits<2> NUM_FORMAT_ALL = 1;
 947   bits<1> FORMAT_COMP_ALL = 0;
 948   bits<1> SRF_MODE_ALL = 0;
 949
 950   // LLVM can only encode 64-bit instructions, so these fields are manually
 951   // encoded in R600CodeEmitter
 952   //
 953   // bits<16> OFFSET;
 954   // bits<2>  ENDIAN_SWAP = 0;
 955   // bits<1>  CONST_BUF_NO_STRIDE = 0;
 956   // bits<1>  MEGA_FETCH = 0;
 957   // bits<1>  ALT_CONST = 0;
 958   // bits<2>  BUFFER_INDEX_MODE = 0;
 959
 960   // VTX_WORD0
 961   let Inst{4-0}   = VC_INST;
 962   let Inst{6-5}   = FETCH_TYPE;
 963   let Inst{7}     = FETCH_WHOLE_QUAD;
 964   let Inst{15-8}  = BUFFER_ID;
 965   let Inst{22-16} = SRC_GPR;
 966   let Inst{23}    = SRC_REL;
 967   let Inst{25-24} = SRC_SEL_X;
 968   let Inst{31-26} = MEGA_FETCH_COUNT;
 969
 970   // VTX_WORD1_GPR
 971   let Inst{38-32} = DST_GPR;
 972   let Inst{39}    = DST_REL;
 973   let Inst{40}    = 0; // Reserved
 974   let Inst{43-41} = DST_SEL_X;
 975   let Inst{46-44} = DST_SEL_Y;
 976   let Inst{49-47} = DST_SEL_Z;
 977   let Inst{52-50} = DST_SEL_W;
 978   let Inst{53}    = USE_CONST_FIELDS;
 979   let Inst{59-54} = DATA_FORMAT;
 980   let Inst{61-60} = NUM_FORMAT_ALL;
 981   let Inst{62}    = FORMAT_COMP_ALL;
 982   let Inst{63}    = SRF_MODE_ALL;
 983
 984   // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
 985   // is done in R600CodeEmitter
 986   //
 987   // Inst{79-64} = OFFSET;
 988   // Inst{81-80} = ENDIAN_SWAP;
 989   // Inst{82}    = CONST_BUF_NO_STRIDE;
 990   // Inst{83}    = MEGA_FETCH;
 991   // Inst{84}    = ALT_CONST;
 992   // Inst{86-85} = BUFFER_INDEX_MODE;
 993   // Inst{95-86} = 0; Reserved
 994
 995   // VTX_WORD3 (Padding)
 996   //
 997   // Inst{127-96} = 0;
 998 }
 999
1000 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1001     : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
1002
1003   let MEGA_FETCH_COUNT = 4;
1004   let DST_SEL_X        = 0;
1005   let DST_SEL_Y        = 7;   // Masked
1006   let DST_SEL_Z        = 7;   // Masked
1007   let DST_SEL_W        = 7;   // Masked
1008   let DATA_FORMAT      = 0xD; // COLOR_32
1009
1010   // This is not really necessary, but there were some GPU hangs that appeared
1011   // to be caused by ALU instructions in the next instruction group that wrote
1012   // to the $ptr registers of the VTX_READ.
1013   // e.g.
1014   // %T3_X<def> = VTX_READ_PARAM_i32_eg %T2_X<kill>, 24
1015   // %T2_X<def> = MOV %ZERO
1016   //Adding this constraint prevents this from happening.
1017   let Constraints = "$ptr.ptr = $dst";
1018 }
1019
1020 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1021     : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> {
1022
1023   let MEGA_FETCH_COUNT = 16;
1024   let DST_SEL_X        =  0;
1025   let DST_SEL_Y        =  1;
1026   let DST_SEL_Z        =  2;
1027   let DST_SEL_W        =  3;
1028   let DATA_FORMAT      =  0x22; // COLOR_32_32_32_32
1029
1030   // XXX: Need to force VTX_READ_128 instructions to write to the same register
1031   // that holds its buffer address to avoid potential hangs.  We can't use
1032   // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1033   // registers are different sizes.
1034 }
1035
1036 //===----------------------------------------------------------------------===//
1037 // VTX Read from parameter memory space
1038 //===----------------------------------------------------------------------===//
1039
1040 class VTX_READ_PARAM_32_eg <ValueType vt> : VTX_READ_32_eg <0,
1041   [(set (vt R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1042 >;
1043
1044 def VTX_READ_PARAM_i32_eg : VTX_READ_PARAM_32_eg<i32>;
1045 def VTX_READ_PARAM_f32_eg : VTX_READ_PARAM_32_eg<f32>;
1046
1047
1048 //===----------------------------------------------------------------------===//
1049 // VTX Read from global memory space
1050 //===----------------------------------------------------------------------===//
1051
1052 // 32-bit reads
1053
1054 class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1,
1055   [(set (vt R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1056 >;
1057
1058 def VTX_READ_GLOBAL_i32_eg : VTX_READ_GLOBAL_eg<i32>;
1059 def VTX_READ_GLOBAL_f32_eg : VTX_READ_GLOBAL_eg<f32>;
1060
1061 // 128-bit reads
1062
1063 class VTX_READ_GLOBAL_128_eg <ValueType vt> : VTX_READ_128_eg <1,
1064   [(set (vt R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1065 >;
1066
1067 def VTX_READ_GLOBAL_v4i32_eg : VTX_READ_GLOBAL_128_eg<v4i32>;
1068 def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>;
1069
1070 }
1071
1072 let Predicates = [isCayman] in {
1073
1074 let isVector = 1 in {
1075
1076 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1077
1078 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1079 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1080 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1081 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1082
1083 } // End isVector = 1
1084
1085 // RECIP_UINT emulation for Cayman
1086 def : Pat <
1087   (AMDGPUurecip R600_Reg32:$src0),
1088   (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1089                             (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000)))
1090 >;
1091
1092 } // End isCayman
1093
1094 /* Other Instructions */
1095
1096 let isCodeGenOnly = 1 in {
1097 /*
1098   def SWIZZLE : AMDGPUShaderInst <
1099     (outs GPRV4F32:$dst),
1100     (ins GPRV4F32:$src0, i32imm:$src1),
1101     "SWIZZLE $dst, $src0, $src1",
1102     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
1103   >;
1104 */
1105
1106   def LAST : AMDGPUShaderInst <
1107     (outs),
1108     (ins),
1109     "LAST",
1110     []
1111   >;
1112
1113   def GET_CHAN : AMDGPUShaderInst <
1114     (outs R600_Reg32:$dst),
1115     (ins R600_Reg128:$src0, i32imm:$src1),
1116     "GET_CHAN $dst, $src0, $src1",
1117     []
1118   >;
1119
1120   def MULLIT : AMDGPUShaderInst <
1121     (outs R600_Reg128:$dst),
1122     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
1123     "MULLIT $dst, $src0, $src1",
1124     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
1125   >;
1126
1127 let usesCustomInserter = 1, isPseudo = 1 in {
1128
1129 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
1130   (outs R600_TReg32:$dst),
1131   (ins),
1132   asm,
1133   [(set R600_TReg32:$dst, (intr))]
1134 >;
1135
1136 def R600_LOAD_CONST : AMDGPUShaderInst <
1137   (outs R600_Reg32:$dst),
1138   (ins i32imm:$src0),
1139   "R600_LOAD_CONST $dst, $src0",
1140   [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1141 >;
1142
1143 def RESERVE_REG : AMDGPUShaderInst <
1144   (outs),
1145   (ins i32imm:$src),
1146   "RESERVE_REG $src",
1147   [(int_AMDGPU_reserve_reg imm:$src)]
1148 >;
1149
1150 def TXD: AMDGPUShaderInst <
1151   (outs R600_Reg128:$dst),
1152   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1153   "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1154   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1155 >;
1156
1157 def TXD_SHADOW: AMDGPUShaderInst <
1158   (outs R600_Reg128:$dst),
1159   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1160   "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1161   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1162 >;
1163
1164 } // End usesCustomInserter = 1, isPseudo = 1
1165
1166 } // End isCodeGenOnly = 1
1167
1168 def CLAMP_R600 :  CLAMP <R600_Reg32>;
1169 def FABS_R600 : FABS<R600_Reg32>;
1170 def FNEG_R600 : FNEG<R600_Reg32>;
1171
1172 let usesCustomInserter = 1 in {
1173
1174 def MASK_WRITE : AMDGPUShaderInst <
1175     (outs),
1176     (ins R600_Reg32:$src),
1177     "MASK_WRITE $src",
1178     []
1179 >;
1180
1181 } // End usesCustomInserter = 1
1182
1183 //===----------------------------------------------------------------------===//
1184 // ISel Patterns
1185 //===----------------------------------------------------------------------===//
1186
1187 // KIL Patterns
1188 def KILP : Pat <
1189   (int_AMDGPU_kilp),
1190   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1191 >;
1192
1193 def KIL : Pat <
1194   (int_AMDGPU_kill R600_Reg32:$src0),
1195   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
1196 >;
1197
1198 // SGT Reverse args
1199 def : Pat <
1200   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1201   (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1202 >;
1203
1204 // SGE Reverse args
1205 def : Pat <
1206   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1207   (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1208 >;
1209
1210 // SETGT_INT reverse args
1211 def : Pat <
1212   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1213   (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1214 >;
1215
1216 // SETGE_INT reverse args
1217 def : Pat <
1218   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1219   (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1220 >;
1221
1222 // SETGT_UINT reverse args
1223 def : Pat <
1224   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1225   (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1226 >;
1227
1228 // SETGE_UINT reverse args
1229 def : Pat <
1230   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1231   (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1232 >;
1233
1234 // The next two patterns are special cases for handling 'true if ordered' and
1235 // 'true if unordered' conditionals.  The assumption here is that the behavior of
1236 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1237 // described here:
1238 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1239 // We assume that  SETE returns false when one of the operands is NAN and
1240 // SNE returns true when on of the operands is NAN
1241
1242 //SETE - 'true if ordered'
1243 def : Pat <
1244   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1245   (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1246 >;
1247
1248 //SNE - 'true if unordered'
1249 def : Pat <
1250   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1251   (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1252 >;
1253
1254 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1255 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1256 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1257 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1258
1259 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1260 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1261 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1262 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1263
1264 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1265 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1266 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1267 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1268
1269 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1270 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1271 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1272 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1273
1274 def : Vector_Build <v4f32, R600_Reg32>;
1275 def : Vector_Build <v4i32, R600_Reg32>;
1276
1277 // bitconvert patterns
1278
1279 def : BitConvert <i32, f32, R600_Reg32>;
1280 def : BitConvert <f32, i32, R600_Reg32>;
1281 def : BitConvert <v4f32, v4i32, R600_Reg128>;
1282
1283 } // End isR600toCayman Predicate