src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Tablegen instruction definitions
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<32> Inst;
  21   bit Trig = 0;
  22   bit Op3 = 0;
  23   bit isVector = 0;
  24
  25   let Inst = inst;
  26   let Namespace = "AMDIL";
  27   let OutOperandList = outs;
  28   let InOperandList = ins;
  29   let AsmString = asm;
  30   let Pattern = pattern;
  31   let Itinerary = itin;
  32
  33   let TSFlags{4} = Trig;
  34   let TSFlags{5} = Op3;
  35
  36   // Vector instructions are instructions that must fill all slots in an
  37   // instruction group
  38   let TSFlags{6} = isVector;
  39 }
  40
  41 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  42     AMDGPUInst <outs, ins, asm, pattern>
  43 {
  44   field bits<64> Inst;
  45
  46   let Namespace = "AMDIL";
  47 }
  48
  49 def MEMxi : Operand<iPTR> {
  50   let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
  51 }
  52
  53 def MEMrr : Operand<iPTR> {
  54   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  55 }
  56
  57 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  58 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
  59 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
  60
  61 class R600_ALU {
  62
  63   bits<7> DST_GPR = 0;
  64   bits<9> SRC0_SEL = 0;
  65   bits<1> SRC0_NEG = 0;
  66   bits<9> SRC1_SEL = 0;
  67   bits<1> SRC1_NEG = 0;
  68   bits<1> CLAMP = 0;
  69
  70 }
  71
  72
  73 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
  74                 InstrItinClass itin = AnyALU> :
  75   InstR600 <inst,
  76           (outs R600_Reg32:$dst),
  77           (ins R600_Reg32:$src, variable_ops),
  78           !strconcat(opName, " $dst, $src"),
  79           pattern,
  80           itin
  81   >;
  82
  83 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
  84                 InstrItinClass itin = AnyALU> :
  85   InstR600 <inst,
  86           (outs R600_Reg32:$dst),
  87           (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
  88           !strconcat(opName, " $dst, $src0, $src1"),
  89           pattern,
  90           itin
  91   >;
  92
  93 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
  94                 InstrItinClass itin = AnyALU> :
  95   InstR600 <inst,
  96           (outs R600_Reg32:$dst),
  97           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
  98           !strconcat(opName, " $dst, $src0, $src1, $src2"),
  99           pattern,
 100           itin>{
 101
 102     let Op3 = 1;
 103   }
 104
 105 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
 106                       InstrItinClass itin = VecALU> :
 107   InstR600 <inst,
 108           (outs R600_Reg32:$dst),
 109           ins,
 110           asm,
 111           pattern,
 112           itin
 113
 114   >;
 115
 116 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
 117                 InstrItinClass itin = AnyALU> :
 118   InstR600 <inst,
 119           (outs R600_Reg128:$dst),
 120           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 121           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 122           pattern,
 123           itin
 124   >;
 125
 126 def TEX_SHADOW : PatLeaf<
 127   (imm),
 128   [{uint32_t TType = (uint32_t)N->getZExtValue();
 129     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 130   }]
 131 >;
 132
 133 def COND_EQ : PatLeaf <
 134   (cond),
 135   [{switch(N->get()){{default: return false;
 136                      case ISD::SETOEQ: case ISD::SETUEQ:
 137                      case ISD::SETEQ: return true;}}}]
 138 >;
 139
 140 def COND_NE : PatLeaf <
 141   (cond),
 142   [{switch(N->get()){{default: return false;
 143                      case ISD::SETONE: case ISD::SETUNE:
 144                      case ISD::SETNE: return true;}}}]
 145 >;
 146 def COND_GT : PatLeaf <
 147   (cond),
 148   [{switch(N->get()){{default: return false;
 149                      case ISD::SETOGT: case ISD::SETUGT:
 150                      case ISD::SETGT: return true;}}}]
 151 >;
 152
 153 def COND_GE : PatLeaf <
 154   (cond),
 155   [{switch(N->get()){{default: return false;
 156                      case ISD::SETOGE: case ISD::SETUGE:
 157                      case ISD::SETGE: return true;}}}]
 158 >;
 159
 160 def COND_LT : PatLeaf <
 161   (cond),
 162   [{switch(N->get()){{default: return false;
 163                      case ISD::SETOLT: case ISD::SETULT:
 164                      case ISD::SETLT: return true;}}}]
 165 >;
 166
 167 def COND_LE : PatLeaf <
 168   (cond),
 169   [{switch(N->get()){{default: return false;
 170                      case ISD::SETOLE: case ISD::SETULE:
 171                      case ISD::SETLE: return true;}}}]
 172 >;
 173
 174 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
 175                  dag ins, string asm, list<dag> pattern> :
 176     InstR600ISA <outs, ins, asm, pattern>
 177 {
 178   bits<7>  RW_GPR;
 179   bits<7>  INDEX_GPR;
 180
 181   bits<2>  RIM;
 182   bits<2>  TYPE;
 183   bits<1>  RW_REL;
 184   bits<2>  ELEM_SIZE;
 185
 186   bits<12> ARRAY_SIZE;
 187   bits<4>  COMP_MASK;
 188   bits<4>  BURST_COUNT;
 189   bits<1>  VPM;
 190   bits<1>  EOP;
 191   bits<1>  MARK;
 192   bits<1>  BARRIER;
 193
 194   /* CF_ALLOC_EXPORT_WORD0_RAT */
 195   let Inst{3-0}   = rat_id;
 196   let Inst{9-4}   = rat_inst;
 197   let Inst{10}    = 0; /* Reserved */
 198   let Inst{12-11} = RIM;
 199   let Inst{14-13} = TYPE;
 200   let Inst{21-15} = RW_GPR;
 201   let Inst{22}    = RW_REL;
 202   let Inst{29-23} = INDEX_GPR;
 203   let Inst{31-30} = ELEM_SIZE;
 204
 205   /* CF_ALLOC_EXPORT_WORD1_BUF */
 206   let Inst{43-32} = ARRAY_SIZE;
 207   let Inst{47-44} = COMP_MASK;
 208   let Inst{51-48} = BURST_COUNT;
 209   let Inst{52}    = VPM;
 210   let Inst{53}    = EOP;
 211   let Inst{61-54} = cf_inst;
 212   let Inst{62}    = MARK;
 213   let Inst{63}    = BARRIER;
 214 }
 215
 216 /*
 217 def store_global : PatFrag<(ops node:$value, node:$ptr),
 218                            (store node:$value, node:$ptr),
 219                            [{
 220                             const Value *Src;
 221                             const PointerType *Type;
 222                             if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
 223                                  PT = dyn_cast<PointerType>(Src->getType()))) {
 224                               return PT->getAddressSpace() == 1;
 225                             }
 226                             return false;
 227                            }]>;
 228
 229 */
 230
 231 def load_param : PatFrag<(ops node:$ptr),
 232                          (load node:$ptr),
 233                           [{
 234                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 235                            if (Src) {
 236                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 237                                 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
 238                            }
 239                            return false;
 240                           }]>;
 241
 242 //class EG_CF <bits<32> inst, string asm> :
 243 //    InstR600 <inst, (outs), (ins), asm, []>;
 244
 245 /* XXX: We will use this when we emit the real ISA.
 246   bits<24> ADDR = 0;
 247   bits<3> JTS = 0;
 248
 249   bits<3> PC = 0;
 250   bits<5> CF_CONS = 0;
 251   bits<2> COND = 0;
 252   bits<6> COUNT = 0;
 253   bits<1> VPM = 0;
 254   bits<1> EOP = 0;
 255   bits<8> CF_INST = 0;
 256   bits<1> WQM = 0;
 257   bits<1> B = 0;
 258
 259   let Inst{23-0} = ADDR;
 260   let Inst{26-24} = JTS;
 261   let Inst{34-32} = PC;
 262   let Inst{39-35} = CF_CONST;
 263   let Inst{41-40} = COND;
 264   let Inst{47-42} = COUNT;
 265   let Inst{52} = VPM;
 266   let Inst{53} = EOP;
 267   let Inst{61-54} = CF_INST;
 268   let Inst{62} = WQM;
 269   let Inst{63} = B;
 270 //}
 271 */
 272 def isR600 : Predicate<"Subtarget.device()"
 273                             "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
 274 def isR700 : Predicate<"Subtarget.device()"
 275                             "->getGeneration() == AMDILDeviceInfo::HD4XXX &&"
 276                             "Subtarget.device()->getDeviceFlag()"
 277                             ">= OCL_DEVICE_RV710">;
 278 def isEG : Predicate<"Subtarget.device()"
 279                             "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
 280                             "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 281 def isCayman : Predicate<"Subtarget.device()"
 282                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 283 def isEGorCayman : Predicate<"Subtarget.device()"
 284                             "->getGeneration() == AMDILDeviceInfo::HD5XXX"
 285                             "|| Subtarget.device()->getGeneration() =="
 286                             "AMDILDeviceInfo::HD6XXX">;
 287
 288 def isR600toCayman : Predicate<
 289                      "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
 290
 291
 292 let Predicates = [isR600toCayman] in {
 293
 294 /* ------------------------------------------- */
 295 /* Common Instructions R600, R700, Evergreen, Cayman */
 296 /* ------------------------------------------- */
 297 def ADD : R600_2OP <
 298   0x0, "ADD",
 299   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
 300 >;
 301
 302 // Non-IEEE MUL: 0 * anything = 0
 303 def MUL : R600_2OP <
 304   0x1, "MUL NON-IEEE",
 305   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 306 >;
 307
 308 def MUL_IEEE : R600_2OP <
 309   0x2, "MUL_IEEE",
 310   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
 311 >;
 312
 313 def MAX : R600_2OP <
 314   0x3, "MAX",
 315   [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
 316 >;
 317
 318 def MIN : R600_2OP <
 319   0x4, "MIN",
 320   [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
 321 >;
 322
 323 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 324  * so some of the instruction names don't match the asm string.
 325  * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 326  */
 327
 328 def SETE : R600_2OP <
 329   0x08, "SETE",
 330   [(set R600_Reg32:$dst,
 331    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 332              COND_EQ))]
 333 >;
 334
 335 def SGT : R600_2OP <
 336   0x09, "SETGT",
 337   [(set R600_Reg32:$dst,
 338    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 339               COND_GT))]
 340 >;
 341
 342 def SGE : R600_2OP <
 343   0xA, "SETGE",
 344   [(set R600_Reg32:$dst,
 345    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 346               COND_GE))]
 347 >;
 348
 349 def SNE : R600_2OP <
 350   0xB, "SETNE",
 351   [(set R600_Reg32:$dst,
 352    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 353     COND_NE))]
 354 >;
 355
 356 def FRACT : R600_1OP <
 357   0x10, "FRACT",
 358   [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
 359 >;
 360
 361 def TRUNC : R600_1OP <
 362   0x11, "TRUNC",
 363   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 364 >;
 365
 366 def CEIL : R600_1OP <
 367   0x12, "CEIL",
 368   [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
 369 >;
 370
 371 def RNDNE : R600_1OP <
 372   0x13, "RNDNE",
 373   [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
 374 >;
 375
 376 def FLOOR : R600_1OP <
 377   0x14, "FLOOR",
 378   [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
 379 >;
 380
 381 def MOV : R600_1OP <0x19, "MOV", []>;
 382
 383 class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
 384   (outs R600_Reg32:$dst),
 385   (ins R600_Reg32:$alu_literal, immType:$imm),
 386   "MOV_IMM $dst, $imm",
 387   [], AnyALU
 388 >;
 389
 390 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
 391 def : Pat <
 392   (imm:$val),
 393   (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
 394 >;
 395
 396 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
 397 def : Pat <
 398   (fpimm:$val),
 399   (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
 400 >;
 401
 402 def KILLGT : R600_2OP <
 403   0x2D, "KILLGT",
 404   []
 405 >;
 406
 407 def AND_INT : R600_2OP <
 408   0x30, "AND_INT",
 409   [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
 410 >;
 411
 412 def OR_INT : R600_2OP <
 413   0x31, "OR_INT",
 414   [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
 415 >;
 416
 417 def XOR_INT : R600_2OP <
 418   0x32, "XOR_INT",
 419   [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
 420 >;
 421
 422 def NOT_INT : R600_1OP <
 423   0x33, "NOT_INT",
 424   [(set R600_Reg32:$dst, (not R600_Reg32:$src))]
 425 >;
 426
 427 def ADD_INT : R600_2OP <
 428   0x34, "ADD_INT",
 429   [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
 430 >;
 431
 432 def SUB_INT : R600_2OP <
 433         0x35, "SUB_INT",
 434         [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
 435 >;
 436
 437 def MAX_INT : R600_2OP <
 438   0x36, "MAX_INT",
 439   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 440
 441 def MIN_INT : R600_2OP <
 442   0x37, "MIN_INT",
 443   [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 444
 445 def MAX_UINT : R600_2OP <
 446   0x38, "MAX_UINT",
 447   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
 448 >;
 449
 450 def MIN_UINT : R600_2OP <
 451   0x39, "MIN_UINT",
 452   [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
 453 >;
 454
 455 def SETE_INT : R600_2OP <
 456   0x3A, "SETE_INT",
 457   [(set (i32 R600_Reg32:$dst),
 458    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
 459 >;
 460
 461 def SETGT_INT : R600_2OP <
 462   0x3B, "SGT_INT",
 463   [(set (i32 R600_Reg32:$dst),
 464    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
 465 >;
 466
 467 def SETGE_INT : R600_2OP <
 468         0x3C, "SETGE_INT",
 469         [(set (i32 R600_Reg32:$dst),
 470    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
 471 >;
 472
 473 def SETNE_INT : R600_2OP <
 474   0x3D, "SETNE_INT",
 475   [(set (i32 R600_Reg32:$dst),
 476    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
 477 >;
 478
 479 def SETGT_UINT : R600_2OP <
 480   0x3E, "SETGT_UINT",
 481   [(set (i32 R600_Reg32:$dst),
 482    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
 483 >;
 484
 485 def SETGE_UINT : R600_2OP <
 486   0x3F, "SETGE_UINT",
 487   [(set (i32 R600_Reg32:$dst),
 488     (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
 489 >;
 490
 491 def CNDE_INT : R600_3OP <
 492         0x1C, "CNDE_INT",
 493   [(set (i32 R600_Reg32:$dst),
 494    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 495 >;
 496
 497 /* Texture instructions */
 498
 499
 500 def TEX_LD : R600_TEX <
 501   0x03, "TEX_LD",
 502   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
 503 > {
 504 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
 505 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
 506 }
 507
 508 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 509   0x04, "TEX_GET_TEXTURE_RESINFO",
 510   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 511 >;
 512
 513 def TEX_GET_GRADIENTS_H : R600_TEX <
 514   0x07, "TEX_GET_GRADIENTS_H",
 515   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 516 >;
 517
 518 def TEX_GET_GRADIENTS_V : R600_TEX <
 519   0x08, "TEX_GET_GRADIENTS_V",
 520   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 521 >;
 522
 523 def TEX_SET_GRADIENTS_H : R600_TEX <
 524   0x0B, "TEX_SET_GRADIENTS_H",
 525   []
 526 >;
 527
 528 def TEX_SET_GRADIENTS_V : R600_TEX <
 529   0x0C, "TEX_SET_GRADIENTS_V",
 530   []
 531 >;
 532
 533 def TEX_SAMPLE : R600_TEX <
 534   0x10, "TEX_SAMPLE",
 535   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 536 >;
 537
 538 def TEX_SAMPLE_C : R600_TEX <
 539   0x18, "TEX_SAMPLE_C",
 540   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 541 >;
 542
 543 def TEX_SAMPLE_L : R600_TEX <
 544   0x11, "TEX_SAMPLE_L",
 545   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 546 >;
 547
 548 def TEX_SAMPLE_C_L : R600_TEX <
 549   0x19, "TEX_SAMPLE_C_L",
 550   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 551 >;
 552
 553 def TEX_SAMPLE_LB : R600_TEX <
 554   0x12, "TEX_SAMPLE_LB",
 555   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 556 >;
 557
 558 def TEX_SAMPLE_C_LB : R600_TEX <
 559   0x1A, "TEX_SAMPLE_C_LB",
 560   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 561 >;
 562
 563 def TEX_SAMPLE_G : R600_TEX <
 564   0x14, "TEX_SAMPLE_G",
 565   []
 566 >;
 567
 568 def TEX_SAMPLE_C_G : R600_TEX <
 569   0x1C, "TEX_SAMPLE_C_G",
 570   []
 571 >;
 572
 573 /* Helper classes for common instructions */
 574
 575 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
 576   inst, "MUL_LIT",
 577   []
 578 >;
 579
 580 class MULADD_Common <bits<32> inst> : R600_3OP <
 581   inst, "MULADD",
 582   [(set (f32 R600_Reg32:$dst),
 583    (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 584 >;
 585
 586 class CNDE_Common <bits<32> inst> : R600_3OP <
 587   inst, "CNDE",
 588   [(set (f32 R600_Reg32:$dst),
 589    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 590 >;
 591
 592 class CNDGT_Common <bits<32> inst> : R600_3OP <
 593   inst, "CNDGT",
 594   []
 595 >;
 596
 597 class CNDGE_Common <bits<32> inst> : R600_3OP <
 598   inst, "CNDGE",
 599   [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 600 >;
 601
 602 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
 603   inst,
 604   (ins R600_Reg128:$src0, R600_Reg128:$src1),
 605   "DOT4 $dst $src0, $src1",
 606   [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 607 >;
 608
 609 class CUBE_Common <bits<32> inst> : InstR600 <
 610   inst,
 611   (outs R600_Reg128:$dst),
 612   (ins R600_Reg128:$src),
 613   "CUBE $dst $src",
 614   [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 615   VecALU
 616 >;
 617
 618 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
 619   inst, "EXP_IEEE",
 620   [(set R600_Reg32:$dst, (fexp2 R600_Reg32:$src))]
 621 >;
 622
 623 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
 624   inst, "FLT_TO_INT",
 625   [(set R600_Reg32:$dst, (fp_to_sint R600_Reg32:$src))]
 626 >;
 627
 628 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 629   inst, "INT_TO_FLT",
 630   [(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
 631 >;
 632
 633 class FLT_TO_UINT_Common <bits<32> inst> : R600_1OP <
 634   inst, "FLT_TO_UINT",
 635   [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))]
 636 >;
 637
 638 class UINT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 639   inst, "UINT_TO_FLT",
 640   [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))]
 641 >;
 642
 643 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 644   inst, "LOG_CLAMPED",
 645   []
 646 >;
 647
 648 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
 649   inst, "LOG_IEEE",
 650   [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
 651 >;
 652
 653 class LSHL_Common <bits<32> inst> : R600_2OP <
 654   inst, "LSHL $dst, $src0, $src1",
 655   [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
 656 >;
 657
 658 class LSHR_Common <bits<32> inst> : R600_2OP <
 659   inst, "LSHR $dst, $src0, $src1",
 660   [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
 661 >;
 662
 663 class ASHR_Common <bits<32> inst> : R600_2OP <
 664   inst, "ASHR $dst, $src0, $src1",
 665   [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
 666 >;
 667
 668 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
 669   inst, "MULHI_INT $dst, $src0, $src1",
 670   [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
 671 >;
 672
 673 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
 674   inst, "MULHI $dst, $src0, $src1",
 675   [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
 676 >;
 677
 678 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
 679   inst, "MULLO_INT $dst, $src0, $src1",
 680   [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
 681 >;
 682
 683 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
 684   inst, "MULLO_UINT $dst, $src0, $src1",
 685   []
 686 >;
 687
 688 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 689   inst, "RECIP_CLAMPED",
 690   []
 691 >;
 692
 693 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
 694   inst, "RECIP_IEEE",
 695   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
 696 >;
 697
 698 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
 699   inst, "RECIP_INT $dst, $src",
 700   [(set R600_Reg32:$dst, (AMDGPUurecip R600_Reg32:$src))]
 701 >;
 702
 703 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
 704   inst, "RECIPSQRT_CLAMPED",
 705   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 706 >;
 707
 708 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 709   inst, "RECIPSQRT_IEEE",
 710   []
 711 >;
 712
 713 class SIN_Common <bits<32> inst> : R600_1OP <
 714   inst, "SIN", []>{
 715   let Trig = 1;
 716 }
 717
 718 class COS_Common <bits<32> inst> : R600_1OP <
 719   inst, "COS", []> {
 720   let Trig = 1;
 721 }
 722
 723 /* Helper patterns for complex intrinsics */
 724 /* -------------------------------------- */
 725
 726 class DIV_Common <InstR600 recip_ieee> : Pat<
 727   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 728   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 729 >;
 730
 731 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 732   (int_AMDGPU_ssg R600_Reg32:$src),
 733   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 734 >;
 735
 736 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 737   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 738   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 739 >;
 740
 741 /* ---------------------- */
 742 /* R600 / R700 Only Instructions */
 743 /* ---------------------- */
 744
 745 let Predicates = [isR600] in {
 746
 747   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 748   def MULADD_r600 : MULADD_Common<0x10>;
 749   def CNDE_r600 : CNDE_Common<0x18>;
 750   def CNDGT_r600 : CNDGT_Common<0x19>;
 751   def CNDGE_r600 : CNDGE_Common<0x1A>;
 752   def DOT4_r600 : DOT4_Common<0x50>;
 753   def CUBE_r600 : CUBE_Common<0x52>;
 754   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 755   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 756   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 757   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 758   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 759   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 760   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 761   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 762   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 763   def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
 764   def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
 765   def SIN_r600 : SIN_Common<0x6E>;
 766   def COS_r600 : COS_Common<0x6F>;
 767   def ASHR_r600 : ASHR_Common<0x70>;
 768   def LSHR_r600 : LSHR_Common<0x71>;
 769   def LSHL_r600 : LSHL_Common<0x72>;
 770   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 771   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 772   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 773   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 774   def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
 775
 776   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 777   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 778   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 779   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 780
 781 }
 782
 783 // Helper pattern for normalizing inputs to triginomic instructions for R700+
 784 // cards.
 785 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
 786   (intr R600_Reg32:$src),
 787   (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
 788 >;
 789
 790 //===----------------------------------------------------------------------===//
 791 // R700 Only instructions
 792 //===----------------------------------------------------------------------===//
 793
 794 let Predicates = [isR700] in {
 795   def SIN_r700 : SIN_Common<0x6E>;
 796   def COS_r700 : COS_Common<0x6F>;
 797
 798   // R700 normalizes inputs to SIN/COS the same as EG
 799   def : TRIG_eg <SIN_r700, int_AMDGPU_sin>;
 800   def : TRIG_eg <COS_r700, int_AMDGPU_cos>;
 801 }
 802
 803 //===----------------------------------------------------------------------===//
 804 // Evergreen Only instructions
 805 //===----------------------------------------------------------------------===//
 806
 807 let Predicates = [isEG] in {
 808
 809 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 810
 811 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 812 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 813 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 814 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 815 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 816
 817 } // End Predicates = [isEG]
 818
 819 /* ------------------------------- */
 820 /* Evergreen / Cayman Instructions */
 821 /* ------------------------------- */
 822
 823 let Predicates = [isEGorCayman] in {
 824
 825   // BFE_UINT - bit_extract, an optimization for mask and shift
 826   // Src0 = Input
 827   // Src1 = Offset
 828   // Src2 = Width
 829   //
 830   // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
 831   //
 832   // Example Usage:
 833   // (Offset, Width)
 834   //
 835   // (0, 8)           = (Input << 24) >> 24  = (Input &  0xff)       >> 0
 836   // (8, 8)           = (Input << 16) >> 24  = (Input &  0xffff)     >> 8
 837   // (16,8)           = (Input <<  8) >> 24  = (Input &  0xffffff)   >> 16
 838   // (24,8)           = (Input <<  0) >> 24  = (Input &  0xffffffff) >> 24
 839   def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
 840     [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
 841                                                       R600_Reg32:$src1,
 842                                                       R600_Reg32:$src2))],
 843     VecALU
 844   >;
 845
 846   def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
 847     [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
 848                                           R600_Reg32:$src2))],
 849     VecALU
 850   >;
 851
 852   def MULADD_eg : MULADD_Common<0x14>;
 853   def ASHR_eg : ASHR_Common<0x15>;
 854   def LSHR_eg : LSHR_Common<0x16>;
 855   def LSHL_eg : LSHL_Common<0x17>;
 856   def CNDE_eg : CNDE_Common<0x19>;
 857   def CNDGT_eg : CNDGT_Common<0x1A>;
 858   def CNDGE_eg : CNDGE_Common<0x1B>;
 859   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 860   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 861   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 862   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 863   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 864   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 865   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 866   def SIN_eg : SIN_Common<0x8D>;
 867   def COS_eg : COS_Common<0x8E>;
 868   def DOT4_eg : DOT4_Common<0xBE>;
 869   def CUBE_eg : CUBE_Common<0xC0>;
 870
 871   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
 872   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
 873   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
 874   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 875
 876   def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
 877   def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
 878
 879   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
 880     let Pattern = [];
 881   }
 882
 883   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
 884
 885   def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
 886     let Pattern = [];
 887   }
 888
 889   def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
 890
 891   def : Pat<(fp_to_sint R600_Reg32:$src),
 892     (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
 893
 894   def : Pat<(fp_to_uint R600_Reg32:$src),
 895     (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
 896
 897 //===----------------------------------------------------------------------===//
 898 // Memory read/write instructions
 899 //===----------------------------------------------------------------------===//
 900
 901 let usesCustomInserter = 1 in {
 902
 903 def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
 904   (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
 905   "RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr",
 906   [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]>
 907 {
 908   let RIM         = 0;
 909   /* XXX: Have a separate instruction for non-indexed writes. */
 910   let TYPE        = 1;
 911   let RW_REL      = 0;
 912   let ELEM_SIZE   = 0;
 913
 914   let ARRAY_SIZE  = 0;
 915   let COMP_MASK   = 1;
 916   let BURST_COUNT = 0;
 917   let VPM         = 0;
 918   let EOP         = 0;
 919   let MARK        = 0;
 920   let BARRIER     = 1;
 921 }
 922
 923 } // End usesCustomInserter = 1
 924
 925 // Floating point global_store
 926 def : Pat <
 927   (global_store (f32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
 928   (RAT_WRITE_CACHELESS_eg R600_TReg32_X:$val, R600_TReg32_X:$ptr)
 929 >;
 930
 931 class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>
 932     : InstR600ISA <outs, (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr", pattern> {
 933
 934   // Operands
 935   bits<7> DST_GPR;
 936   bits<7> SRC_GPR;
 937
 938   // Static fields
 939   bits<5> VC_INST = 0;
 940   bits<2> FETCH_TYPE = 2;
 941   bits<1> FETCH_WHOLE_QUAD = 0;
 942   bits<8> BUFFER_ID = buffer_id;
 943   bits<1> SRC_REL = 0;
 944   // XXX: We can infer this field based on the SRC_GPR.  This would allow us
 945   // to store vertex addresses in any channel, not just X.
 946   bits<2> SRC_SEL_X = 0;
 947   bits<6> MEGA_FETCH_COUNT;
 948   bits<1> DST_REL = 0;
 949   bits<3> DST_SEL_X;
 950   bits<3> DST_SEL_Y;
 951   bits<3> DST_SEL_Z;
 952   bits<3> DST_SEL_W;
 953   // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
 954   // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
 955   // however, based on my testing if USE_CONST_FIELDS is set, then all
 956   // these fields need to be set to 0.
 957   bits<1> USE_CONST_FIELDS = 0;
 958   bits<6> DATA_FORMAT;
 959   bits<2> NUM_FORMAT_ALL = 1;
 960   bits<1> FORMAT_COMP_ALL = 0;
 961   bits<1> SRF_MODE_ALL = 0;
 962
 963   // LLVM can only encode 64-bit instructions, so these fields are manually
 964   // encoded in R600CodeEmitter
 965   //
 966   // bits<16> OFFSET;
 967   // bits<2>  ENDIAN_SWAP = 0;
 968   // bits<1>  CONST_BUF_NO_STRIDE = 0;
 969   // bits<1>  MEGA_FETCH = 0;
 970   // bits<1>  ALT_CONST = 0;
 971   // bits<2>  BUFFER_INDEX_MODE = 0;
 972
 973   // VTX_WORD0
 974   let Inst{4-0}   = VC_INST;
 975   let Inst{6-5}   = FETCH_TYPE;
 976   let Inst{7}     = FETCH_WHOLE_QUAD;
 977   let Inst{15-8}  = BUFFER_ID;
 978   let Inst{22-16} = SRC_GPR;
 979   let Inst{23}    = SRC_REL;
 980   let Inst{25-24} = SRC_SEL_X;
 981   let Inst{31-26} = MEGA_FETCH_COUNT;
 982
 983   // VTX_WORD1_GPR
 984   let Inst{38-32} = DST_GPR;
 985   let Inst{39}    = DST_REL;
 986   let Inst{40}    = 0; // Reserved
 987   let Inst{43-41} = DST_SEL_X;
 988   let Inst{46-44} = DST_SEL_Y;
 989   let Inst{49-47} = DST_SEL_Z;
 990   let Inst{52-50} = DST_SEL_W;
 991   let Inst{53}    = USE_CONST_FIELDS;
 992   let Inst{59-54} = DATA_FORMAT;
 993   let Inst{61-60} = NUM_FORMAT_ALL;
 994   let Inst{62}    = FORMAT_COMP_ALL;
 995   let Inst{63}    = SRF_MODE_ALL;
 996
 997   // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
 998   // is done in R600CodeEmitter
 999   //
1000   // Inst{79-64} = OFFSET;
1001   // Inst{81-80} = ENDIAN_SWAP;
1002   // Inst{82}    = CONST_BUF_NO_STRIDE;
1003   // Inst{83}    = MEGA_FETCH;
1004   // Inst{84}    = ALT_CONST;
1005   // Inst{86-85} = BUFFER_INDEX_MODE;
1006   // Inst{95-86} = 0; Reserved
1007
1008   // VTX_WORD3 (Padding)
1009   //
1010   // Inst{127-96} = 0;
1011 }
1012
1013 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1014     : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
1015
1016   let MEGA_FETCH_COUNT = 4;
1017   let DST_SEL_X        = 0;
1018   let DST_SEL_Y        = 7;   // Masked
1019   let DST_SEL_Z        = 7;   // Masked
1020   let DST_SEL_W        = 7;   // Masked
1021   let DATA_FORMAT      = 0xD; // COLOR_32
1022 }
1023
1024 def VTX_READ_PARAM_eg : VTX_READ_32_eg <0,
1025   [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1026 >;
1027
1028 def VTX_READ_GLOBAL_eg : VTX_READ_32_eg <1,
1029   [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1030 >;
1031
1032 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1033     : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> {
1034
1035   let MEGA_FETCH_COUNT = 16;
1036   let DST_SEL_X        =  0;
1037   let DST_SEL_Y        =  1;
1038   let DST_SEL_Z        =  2;
1039   let DST_SEL_W        =  3;
1040   let DATA_FORMAT      =  0x22; // COLOR_32_32_32_32
1041 }
1042
1043 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1044   [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1045 >;
1046
1047 }
1048
1049 let Predicates = [isCayman] in {
1050
1051 let isVector = 1 in {
1052
1053 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1054
1055 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1056 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1057 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1058 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1059
1060 } // End isVector = 1
1061
1062 // RECIP_UINT emulation for Cayman
1063 def : Pat <
1064   (AMDGPUurecip R600_Reg32:$src0),
1065   (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1066                             (MOV_IMM_I32 (i32 ALU_LITERAL_X), 0x4f800000)))
1067 >;
1068
1069 } // End isCayman
1070
1071 /* Other Instructions */
1072
1073 let isCodeGenOnly = 1 in {
1074 /*
1075   def SWIZZLE : AMDGPUShaderInst <
1076     (outs GPRV4F32:$dst),
1077     (ins GPRV4F32:$src0, i32imm:$src1),
1078     "SWIZZLE $dst, $src0, $src1",
1079     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
1080   >;
1081 */
1082
1083   def LAST : AMDGPUShaderInst <
1084     (outs),
1085     (ins),
1086     "LAST",
1087     []
1088   >;
1089
1090   def GET_CHAN : AMDGPUShaderInst <
1091     (outs R600_Reg32:$dst),
1092     (ins R600_Reg128:$src0, i32imm:$src1),
1093     "GET_CHAN $dst, $src0, $src1",
1094     []
1095   >;
1096
1097   def MULLIT : AMDGPUShaderInst <
1098     (outs R600_Reg128:$dst),
1099     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
1100     "MULLIT $dst, $src0, $src1",
1101     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
1102   >;
1103
1104 let usesCustomInserter = 1, isPseudo = 1 in {
1105
1106 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
1107   (outs R600_TReg32:$dst),
1108   (ins),
1109   asm,
1110   [(set R600_TReg32:$dst, (intr))]
1111 >;
1112
1113 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
1114 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
1115 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
1116
1117 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
1118 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
1119 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
1120
1121 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
1122 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
1123 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
1124
1125 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
1126                                      int_r600_read_global_size_x>;
1127 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
1128                                      int_r600_read_global_size_y>;
1129 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
1130                                      int_r600_read_global_size_z>;
1131
1132 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
1133                                     int_r600_read_local_size_x>;
1134 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
1135                                     int_r600_read_local_size_y>;
1136 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
1137                                     int_r600_read_local_size_z>;
1138
1139 def R600_LOAD_CONST : AMDGPUShaderInst <
1140   (outs R600_Reg32:$dst),
1141   (ins i32imm:$src0),
1142   "R600_LOAD_CONST $dst, $src0",
1143   [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1144 >;
1145
1146 def LOAD_INPUT : AMDGPUShaderInst <
1147   (outs R600_Reg32:$dst),
1148   (ins i32imm:$src),
1149   "LOAD_INPUT $dst, $src",
1150   [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1151 >;
1152
1153 def RESERVE_REG : AMDGPUShaderInst <
1154   (outs),
1155   (ins i32imm:$src),
1156   "RESERVE_REG $src",
1157   [(int_AMDGPU_reserve_reg imm:$src)]
1158 >;
1159
1160 def STORE_OUTPUT: AMDGPUShaderInst <
1161   (outs),
1162   (ins R600_Reg32:$src0, i32imm:$src1),
1163   "STORE_OUTPUT $src0, $src1",
1164   [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1165 >;
1166
1167 def TXD: AMDGPUShaderInst <
1168   (outs R600_Reg128:$dst),
1169   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1170   "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1171   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1172 >;
1173
1174 def TXD_SHADOW: AMDGPUShaderInst <
1175   (outs R600_Reg128:$dst),
1176   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1177   "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1178   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1179 >;
1180
1181 } // End usesCustomInserter = 1, isPseudo = 1
1182
1183 } // End isCodeGenOnly = 1
1184
1185 def CLAMP_R600 :  CLAMP <R600_Reg32>;
1186 def FABS_R600 : FABS<R600_Reg32>;
1187 def FNEG_R600 : FNEG<R600_Reg32>;
1188
1189 let usesCustomInserter = 1 in {
1190
1191 def MASK_WRITE : AMDGPUShaderInst <
1192     (outs),
1193     (ins R600_Reg32:$src),
1194     "MASK_WRITE $src",
1195     []
1196 >;
1197
1198 } // End usesCustomInserter = 1
1199
1200 //===----------------------------------------------------------------------===//
1201 // ISel Patterns
1202 //===----------------------------------------------------------------------===//
1203
1204 // KIL Patterns
1205 def KILP : Pat <
1206   (int_AMDGPU_kilp),
1207   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1208 >;
1209
1210 def KIL : Pat <
1211   (int_AMDGPU_kill R600_Reg32:$src0),
1212   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
1213 >;
1214
1215 // SGT Reverse args
1216 def : Pat <
1217   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1218   (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1219 >;
1220
1221 // SGE Reverse args
1222 def : Pat <
1223   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1224   (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1225 >;
1226
1227 // SETGT_INT reverse args
1228 def : Pat <
1229   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1230   (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1231 >;
1232
1233 // SETGE_INT reverse args
1234 def : Pat <
1235   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1236   (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1237 >;
1238
1239 // SETGT_UINT reverse args
1240 def : Pat <
1241   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1242   (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1243 >;
1244
1245 // SETGE_UINT reverse args
1246 def : Pat <
1247   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1248   (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1249 >;
1250
1251 // The next two patterns are special cases for handling 'true if ordered' and
1252 // 'true if unordered' conditionals.  The assumption here is that the behavior of
1253 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1254 // described here:
1255 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1256 // We assume that  SETE returns false when one of the operands is NAN and
1257 // SNE returns true when on of the operands is NAN
1258
1259 //SETE - 'true if ordered'
1260 def : Pat <
1261   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1262   (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1263 >;
1264
1265 //SNE - 'true if unordered'
1266 def : Pat <
1267   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1268   (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1269 >;
1270
1271 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1272 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1273 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1274 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1275
1276 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1277 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1278 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1279 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1280
1281 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1282 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1283 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1284 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1285
1286 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1287 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1288 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1289 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1290
1291 def : Vector_Build <v4f32, R600_Reg32>;
1292 def : Vector_Build <v4i32, R600_Reg32>;
1293
1294 // bitconvert patterns
1295
1296 def : BitConvert <i32, f32, R600_Reg32>;
1297 def : BitConvert <f32, i32, R600_Reg32>;
1298 def : BitConvert <v4f32, v4i32, R600_Reg128>;
1299
1300 } // End isR600toCayman Predicate