src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Tablegen instruction definitions
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<32> Inst;
  21         bit Trig = 0;
  22   bit Op3 = 0;
  23
  24   let Inst = inst;
  25   let Namespace = "AMDIL";
  26   let OutOperandList = outs;
  27   let InOperandList = ins;
  28   let AsmString = asm;
  29   let Pattern = pattern;
  30   let Itinerary = itin;
  31
  32   let TSFlags{4} = Trig;
  33   let TSFlags{5} = Op3;
  34 }
  35
  36 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  37     AMDGPUInst <outs, ins, asm, pattern>
  38 {
  39   field bits<64> Inst;
  40
  41   let Namespace = "AMDIL";
  42 }
  43
  44 def MEMri : Operand<iPTRAny> {
  45   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  46 }
  47
  48 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  49
  50 class R600_ALU {
  51
  52   bits<7> DST_GPR = 0;
  53   bits<9> SRC0_SEL = 0;
  54   bits<1> SRC0_NEG = 0;
  55   bits<9> SRC1_SEL = 0;
  56   bits<1> SRC1_NEG = 0;
  57   bits<1> CLAMP = 0;
  58
  59 }
  60
  61
  62 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
  63                 InstrItinClass itin = AnyALU> :
  64   InstR600 <inst,
  65           (outs R600_Reg32:$dst),
  66           (ins R600_Reg32:$src, variable_ops),
  67           !strconcat(opName, " $dst, $src"),
  68           pattern,
  69           itin
  70   >;
  71
  72 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
  73                 InstrItinClass itin = AnyALU> :
  74   InstR600 <inst,
  75           (outs R600_Reg32:$dst),
  76           (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
  77           !strconcat(opName, " $dst, $src0, $src1"),
  78           pattern,
  79           itin
  80   >;
  81
  82 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
  83                 InstrItinClass itin = AnyALU> :
  84   InstR600 <inst,
  85           (outs R600_Reg32:$dst),
  86           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
  87           !strconcat(opName, " $dst, $src0, $src1, $src2"),
  88           pattern,
  89           itin>{
  90
  91     let Op3 = 1;
  92   }
  93
  94 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
  95                       InstrItinClass itin = VecALU> :
  96   InstR600 <inst,
  97           (outs R600_Reg32:$dst),
  98           ins,
  99           asm,
 100           pattern,
 101           itin
 102
 103   >;
 104
 105 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
 106                 InstrItinClass itin = AnyALU> :
 107   InstR600 <inst,
 108           (outs R600_Reg128:$dst),
 109           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 110           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 111           pattern,
 112           itin
 113   >;
 114
 115 def TEX_SHADOW : PatLeaf<
 116   (imm),
 117   [{uint32_t TType = (uint32_t)N->getZExtValue();
 118     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 119   }]
 120 >;
 121
 122 def FP_ZERO : PatLeaf <
 123   (fpimm),
 124   [{return N->getValueAPF().isZero();}]
 125 >;
 126
 127 def FP_ONE : PatLeaf <
 128   (fpimm),
 129   [{return N->isExactlyValue(1.0);}]
 130 >;
 131
 132 def COND_EQ : PatLeaf <
 133   (cond),
 134   [{switch(N->get()){{default: return false;
 135                      case ISD::SETOEQ: case ISD::SETUEQ:
 136                      case ISD::SETEQ: return true;}}}]
 137 >;
 138
 139 def COND_NE : PatLeaf <
 140   (cond),
 141   [{switch(N->get()){{default: return false;
 142                      case ISD::SETONE: case ISD::SETUNE:
 143                      case ISD::SETNE: return true;}}}]
 144 >;
 145 def COND_GT : PatLeaf <
 146   (cond),
 147   [{switch(N->get()){{default: return false;
 148                      case ISD::SETOGT: case ISD::SETUGT:
 149                      case ISD::SETGT: return true;}}}]
 150 >;
 151
 152 def COND_GE : PatLeaf <
 153   (cond),
 154   [{switch(N->get()){{default: return false;
 155                      case ISD::SETOGE: case ISD::SETUGE:
 156                      case ISD::SETGE: return true;}}}]
 157 >;
 158
 159 def COND_LT : PatLeaf <
 160   (cond),
 161   [{switch(N->get()){{default: return false;
 162                      case ISD::SETOLT: case ISD::SETULT:
 163                      case ISD::SETLT: return true;}}}]
 164 >;
 165
 166 def COND_LE : PatLeaf <
 167   (cond),
 168   [{switch(N->get()){{default: return false;
 169                      case ISD::SETOLE: case ISD::SETULE:
 170                      case ISD::SETLE: return true;}}}]
 171 >;
 172
 173 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
 174                  string asm> :
 175     InstR600ISA <outs, ins, asm, []>
 176 {
 177   bits<7>  RW_GPR;
 178   bits<7>  INDEX_GPR;
 179   bits<4>  RAT_ID;
 180
 181   bits<2>  RIM;
 182   bits<2>  TYPE;
 183   bits<1>  RW_REL;
 184   bits<2>  ELEM_SIZE;
 185
 186   bits<12> ARRAY_SIZE;
 187   bits<4>  COMP_MASK;
 188   bits<4>  BURST_COUNT;
 189   bits<1>  VPM;
 190   bits<1>  EOP;
 191   bits<1>  MARK;
 192   bits<1>  BARRIER;
 193
 194   /* CF_ALLOC_EXPORT_WORD0_RAT */
 195   let Inst{3-0}   = RAT_ID;
 196   let Inst{9-4}   = rat_inst;
 197   let Inst{10}    = 0; /* Reserved */
 198   let Inst{12-11} = RIM;
 199   let Inst{14-13} = TYPE;
 200   let Inst{21-15} = RW_GPR;
 201   let Inst{22}    = RW_REL;
 202   let Inst{29-23} = INDEX_GPR;
 203   let Inst{31-30} = ELEM_SIZE;
 204
 205   /* CF_ALLOC_EXPORT_WORD1_BUF */
 206   let Inst{43-32} = ARRAY_SIZE;
 207   let Inst{47-44} = COMP_MASK;
 208   let Inst{51-48} = BURST_COUNT;
 209   let Inst{52}    = VPM;
 210   let Inst{53}    = EOP;
 211   let Inst{61-54} = cf_inst;
 212   let Inst{62}    = MARK;
 213   let Inst{63}    = BARRIER;
 214 }
 215
 216 /*
 217 def store_global : PatFrag<(ops node:$value, node:$ptr),
 218                            (store node:$value, node:$ptr),
 219                            [{
 220                             const Value *Src;
 221                             const PointerType *Type;
 222                             if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
 223                                  PT = dyn_cast<PointerType>(Src->getType()))) {
 224                               return PT->getAddressSpace() == 1;
 225                             }
 226                             return false;
 227                            }]>;
 228
 229 */
 230
 231 def load_param : PatFrag<(ops node:$ptr),
 232                          (load node:$ptr),
 233                           [{
 234                            return true;
 235                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 236                            if (Src) {
 237                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 238                                 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
 239                            }
 240                            return false;
 241                           }]>;
 242
 243 //class EG_CF <bits<32> inst, string asm> :
 244 //    InstR600 <inst, (outs), (ins), asm, []>;
 245
 246 /* XXX: We will use this when we emit the real ISA.
 247   bits<24> ADDR = 0;
 248   bits<3> JTS = 0;
 249
 250   bits<3> PC = 0;
 251   bits<5> CF_CONS = 0;
 252   bits<2> COND = 0;
 253   bits<6> COUNT = 0;
 254   bits<1> VPM = 0;
 255   bits<1> EOP = 0;
 256   bits<8> CF_INST = 0;
 257   bits<1> WQM = 0;
 258   bits<1> B = 0;
 259
 260   let Inst{23-0} = ADDR;
 261   let Inst{26-24} = JTS;
 262   let Inst{34-32} = PC;
 263   let Inst{39-35} = CF_CONST;
 264   let Inst{41-40} = COND;
 265   let Inst{47-42} = COUNT;
 266   let Inst{52} = VPM;
 267   let Inst{53} = EOP;
 268   let Inst{61-54} = CF_INST;
 269   let Inst{62} = WQM;
 270   let Inst{63} = B;
 271 //}
 272 */
 273 def isR600 : Predicate<"Subtarget.device()"
 274                             "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
 275 def isEG : Predicate<"Subtarget.device()"
 276                             "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
 277                             "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 278 def isCayman : Predicate<"Subtarget.device()"
 279                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 280 def isEGorCayman : Predicate<"Subtarget.device()"
 281                             "->getGeneration() == AMDILDeviceInfo::HD5XXX"
 282                             "|| Subtarget.device()->getGeneration() =="
 283                             "AMDILDeviceInfo::HD6XXX">;
 284
 285 def isR600toCayman : Predicate<
 286                      "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
 287
 288
 289 let Predicates = [isR600toCayman] in {
 290
 291 /* ------------------------------------------- */
 292 /* Common Instructions R600, R700, Evergreen, Cayman */
 293 /* ------------------------------------------- */
 294 let Gen = AMDGPUGen.R600_CAYMAN  in {
 295
 296 def ADD : R600_2OP <
 297   0x0, "ADD",
 298   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
 299 >;
 300
 301 // Non-IEEE MUL: 0 * anything = 0
 302 def MUL : R600_2OP <
 303   0x1, "MUL NON-IEEE",
 304   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 305 >;
 306
 307 def MUL_IEEE : R600_2OP <
 308   0x2, "MUL_IEEE",
 309   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
 310 >;
 311
 312 def MAX : R600_2OP <
 313   0x3, "MAX",
 314   [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
 315 >;
 316
 317 def MIN : R600_2OP <
 318   0x4, "MIN",
 319   [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
 320 >;
 321
 322 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 323  * so some of the instruction names don't match the asm string.
 324  * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 325  */
 326
 327 def SETE : R600_2OP <
 328   0x08, "SETE",
 329   [(set R600_Reg32:$dst,
 330    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 331              COND_EQ))]
 332 >;
 333 //let AMDILOp = AMDILInst.FEQ;
 334
 335 def SGT : R600_2OP <
 336   0x09, "SETGT",
 337   [(set R600_Reg32:$dst,
 338    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 339               COND_GT))]
 340 >;
 341
 342 def SGE : R600_2OP <
 343   0xA, "SETGE",
 344   [(set R600_Reg32:$dst,
 345    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 346               COND_GE))]
 347 >;
 348 //let AMDILOp = AMDILInst.FGE;
 349
 350 def SNE : R600_2OP <
 351   0xB, "SETNE",
 352   [(set R600_Reg32:$dst,
 353    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
 354     COND_NE))]
 355 >;
 356
 357 //  let AMDILOp = AMDILInst.FNE;
 358
 359 def FRACT : R600_1OP <
 360   0x10, "FRACT",
 361   [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
 362 >;
 363
 364 def TRUNC : R600_1OP <
 365   0x11, "TRUNC",
 366   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 367 >;
 368
 369 def CEIL : R600_1OP <
 370   0x12, "CEIL",
 371   [(set R600_Reg32:$dst, (int_AMDIL_round_posinf R600_Reg32:$src))]> {
 372   let AMDILOp = AMDILInst.ROUND_POSINF_f32;
 373 }
 374
 375 def RNDNE : R600_1OP <
 376   0x13, "RNDNE",
 377   [(set R600_Reg32:$dst, (int_AMDIL_round_nearest R600_Reg32:$src))]> {
 378   let AMDILOp = AMDILInst.ROUND_NEAREST_f32;
 379 }
 380
 381 def FLOOR : R600_1OP <
 382   0x14, "FLOOR",
 383   [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
 384 >;
 385
 386 def MOV : R600_1OP <0x19, "MOV", []>;
 387
 388 def KILLGT : R600_2OP <
 389   0x2D, "KILLGT",
 390   []
 391 >;
 392
 393 def AND_INT : R600_2OP <
 394   0x30, "AND_INT",
 395   []> {
 396   let AMDILOp = AMDILInst.AND_i32;
 397 }
 398
 399 def OR_INT : R600_2OP <
 400   0x31, "OR_INT",
 401   []>{
 402   let AMDILOp = AMDILInst.BINARY_OR_i32;
 403 }
 404
 405 def XOR_INT : R600_2OP <
 406   0x32, "XOR_INT",
 407   []
 408 >;
 409
 410 def NOT_INT : R600_1OP <
 411   0x33, "NOT_INT",
 412   []>{
 413   let AMDILOp = AMDILInst.BINARY_NOT_i32;
 414 }
 415
 416 def ADD_INT : R600_2OP <
 417   0x34, "ADD_INT",
 418   []>{
 419   let AMDILOp = AMDILInst.ADD_i32;
 420 }
 421
 422 def SUB_INT : R600_2OP <
 423         0x35, "SUB_INT",
 424         [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
 425 >;
 426
 427 def MAX_INT : R600_2OP <
 428   0x36, "MAX_INT",
 429   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 430
 431 def MIN_INT : R600_2OP <
 432   0x37, "MIN_INT",
 433   [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 434
 435 def MAX_UINT : R600_2OP <
 436   0x38, "MAX_UINT",
 437   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
 438 >;
 439
 440 def MIN_UINT : R600_2OP <
 441   0x39, "MIN_UINT",
 442   [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
 443 >;
 444
 445 def SETE_INT : R600_2OP <
 446   0x3A, "SETE_INT",
 447   [(set (i32 R600_Reg32:$dst),
 448    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
 449 >;
 450
 451 //  let AMDILOp = AMDILInst.IEQ;
 452
 453 def SETGT_INT : R600_2OP <
 454   0x3B, "SGT_INT",
 455   [(set (i32 R600_Reg32:$dst),
 456    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
 457 >;
 458
 459 def SETGE_INT : R600_2OP <
 460         0x3C, "SETGE_INT",
 461         [(set (i32 R600_Reg32:$dst),
 462    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
 463 >;
 464 //  let AMDILOp = AMDILInst.IGE;
 465
 466
 467 def SETNE_INT : R600_2OP <
 468   0x3D, "SETNE_INT",
 469   [(set (i32 R600_Reg32:$dst),
 470    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
 471 >;
 472 //let AMDILOp = AMDILInst.INE;
 473
 474
 475 def SETGT_UINT : R600_2OP <
 476   0x3E, "SETGT_UINT",
 477   [(set (i32 R600_Reg32:$dst),
 478    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
 479 >;
 480
 481 //  let AMDILOp = AMDILInst.UGT;
 482
 483 def SETGE_UINT : R600_2OP <
 484   0x3F, "SETGE_UINT",
 485   [(set (i32 R600_Reg32:$dst),
 486     (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
 487 >;
 488 //  let AMDILOp = AMDILInst.UGE;
 489
 490 def CNDE_INT : R600_3OP <
 491         0x1C, "CNDE_INT",
 492   [(set (i32 R600_Reg32:$dst),
 493    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 494 >;
 495
 496 /* Texture instructions */
 497
 498
 499 def TEX_LD : R600_TEX <
 500   0x03, "TEX_LD",
 501   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
 502 > {
 503 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
 504 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
 505 }
 506
 507 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 508   0x04, "TEX_GET_TEXTURE_RESINFO",
 509   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 510 >;
 511
 512 def TEX_GET_GRADIENTS_H : R600_TEX <
 513   0x07, "TEX_GET_GRADIENTS_H",
 514   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 515 >;
 516
 517 def TEX_GET_GRADIENTS_V : R600_TEX <
 518   0x08, "TEX_GET_GRADIENTS_V",
 519   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 520 >;
 521
 522 def TEX_SET_GRADIENTS_H : R600_TEX <
 523   0x0B, "TEX_SET_GRADIENTS_H",
 524   []
 525 >;
 526
 527 def TEX_SET_GRADIENTS_V : R600_TEX <
 528   0x0C, "TEX_SET_GRADIENTS_V",
 529   []
 530 >;
 531
 532 def TEX_SAMPLE : R600_TEX <
 533   0x10, "TEX_SAMPLE",
 534   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 535 >;
 536
 537 def TEX_SAMPLE_C : R600_TEX <
 538   0x18, "TEX_SAMPLE_C",
 539   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 540 >;
 541
 542 def TEX_SAMPLE_L : R600_TEX <
 543   0x11, "TEX_SAMPLE_L",
 544   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 545 >;
 546
 547 def TEX_SAMPLE_C_L : R600_TEX <
 548   0x19, "TEX_SAMPLE_C_L",
 549   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 550 >;
 551
 552 def TEX_SAMPLE_LB : R600_TEX <
 553   0x12, "TEX_SAMPLE_LB",
 554   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 555 >;
 556
 557 def TEX_SAMPLE_C_LB : R600_TEX <
 558   0x1A, "TEX_SAMPLE_C_LB",
 559   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 560 >;
 561
 562 def TEX_SAMPLE_G : R600_TEX <
 563   0x14, "TEX_SAMPLE_G",
 564   []
 565 >;
 566
 567 def TEX_SAMPLE_C_G : R600_TEX <
 568   0x1C, "TEX_SAMPLE_C_G",
 569   []
 570 >;
 571
 572 } // End Gen R600_CAYMAN
 573
 574 def KILP : Pat <
 575   (int_AMDGPU_kilp),
 576   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
 577 >;
 578
 579 def KIL : Pat <
 580   (int_AMDGPU_kill R600_Reg32:$src0),
 581   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
 582 >;
 583
 584 /* Helper classes for common instructions */
 585
 586 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
 587   inst, "MUL_LIT",
 588   []
 589 >;
 590
 591 class MULADD_Common <bits<32> inst> : R600_3OP <
 592   inst, "MULADD",
 593   [(set (f32 R600_Reg32:$dst),
 594    (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 595 >;
 596
 597 class CNDE_Common <bits<32> inst> : R600_3OP <
 598   inst, "CNDE",
 599   [(set (f32 R600_Reg32:$dst),
 600    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 601 >;
 602
 603 class CNDGT_Common <bits<32> inst> : R600_3OP <
 604   inst, "CNDGT",
 605   []
 606 >;
 607
 608 class CNDGE_Common <bits<32> inst> : R600_3OP <
 609   inst, "CNDGE",
 610   [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 611 >;
 612
 613 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
 614   inst,
 615   (ins R600_Reg128:$src0, R600_Reg128:$src1),
 616   "DOT4 $dst $src0, $src1",
 617   [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 618 >;
 619
 620 class CUBE_Common <bits<32> inst> : InstR600 <
 621   inst,
 622   (outs R600_Reg128:$dst),
 623   (ins R600_Reg128:$src),
 624   "CUBE $dst $src",
 625   [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 626   VecALU
 627 >;
 628
 629 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
 630   inst, "EXP_IEEE",
 631   []> {
 632   let AMDILOp = AMDILInst.EXP_f32;
 633 }
 634
 635 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
 636   inst, "FLT_TO_INT", []> {
 637   let AMDILOp = AMDILInst.FTOI;
 638 }
 639
 640 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 641   inst, "INT_TO_FLT", []> {
 642   let AMDILOp = AMDILInst.ITOF;
 643 }
 644
 645 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 646   inst, "LOG_CLAMPED",
 647   []
 648 >;
 649
 650 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
 651   inst, "LOG_IEEE",
 652   []> {
 653   let AMDILOp = AMDILInst.LOG_f32;
 654 }
 655
 656 class LSHL_Common <bits<32> inst> : R600_2OP <
 657   inst, "LSHL $dst, $src0, $src1",
 658   [] >{
 659   let AMDILOp = AMDILInst.SHL_i32;
 660 }
 661
 662 class LSHR_Common <bits<32> inst> : R600_2OP <
 663   inst, "LSHR $dst, $src0, $src1",
 664   [] >{
 665   let AMDILOp = AMDILInst.USHR_i32;
 666 }
 667
 668 class ASHR_Common <bits<32> inst> : R600_2OP <
 669   inst, "ASHR $dst, $src0, $src1",
 670   [] >{
 671   let AMDILOp = AMDILInst.SHR_i32;
 672 }
 673
 674 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
 675   inst, "MULHI_INT $dst, $src0, $src1",
 676   [] >{
 677   let AMDILOp = AMDILInst.SMULHI_i32;
 678 }
 679
 680 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
 681         inst, "MULHI $dst, $src0, $src1",
 682         []
 683 >;
 684
 685 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
 686   inst, "MULLO_INT $dst, $src0, $src1",
 687   [] >{
 688   let AMDILOp = AMDILInst.SMUL_i32;
 689 }
 690
 691 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
 692   inst, "MULLO_UINT $dst, $src0, $src1",
 693   []
 694 >;
 695
 696 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 697   inst, "RECIP_CLAMPED",
 698   []
 699 >;
 700
 701 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
 702   inst, "RECIP_IEEE",
 703   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
 704   let AMDILOp = AMDILInst.RSQ_f32;
 705 }
 706
 707 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
 708   inst, "RECIP_INT $dst, $src",
 709   []
 710 >;
 711
 712 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
 713   inst, "RECIPSQRT_CLAMPED",
 714   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 715 >;
 716
 717 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 718   inst, "RECIPSQRT_IEEE",
 719   []
 720 >;
 721
 722 class SIN_Common <bits<32> inst> : R600_1OP <
 723   inst, "SIN",
 724   []>{
 725   let AMDILOp = AMDILInst.SIN_f32;
 726   let Trig = 1;
 727 }
 728
 729 class COS_Common <bits<32> inst> : R600_1OP <
 730   inst, "COS",
 731   []> {
 732   let AMDILOp = AMDILInst.COS_f32;
 733   let Trig = 1;
 734 }
 735
 736 /* Helper patterns for complex intrinsics */
 737 /* -------------------------------------- */
 738
 739 class DIV_Common <InstR600 recip_ieee> : Pat<
 740   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 741   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 742 >;
 743
 744 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 745   (int_AMDGPU_ssg R600_Reg32:$src),
 746   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 747 >;
 748
 749 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 750   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 751   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 752 >;
 753
 754 /* ---------------------- */
 755 /* R600 / R700 Only Instructions */
 756 /* ---------------------- */
 757
 758 let Predicates = [isR600] in {
 759
 760 let Gen = AMDGPUGen.R600 in {
 761
 762   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 763   def MULADD_r600 : MULADD_Common<0x10>;
 764   def CNDE_r600 : CNDE_Common<0x18>;
 765   def CNDGT_r600 : CNDGT_Common<0x19>;
 766   def CNDGE_r600 : CNDGE_Common<0x1A>;
 767   def DOT4_r600 : DOT4_Common<0x50>;
 768   def CUBE_r600 : CUBE_Common<0x52>;
 769   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 770   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 771   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 772   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 773   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 774   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 775   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 776   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 777   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 778   def SIN_r600 : SIN_Common<0x6E>;
 779   def COS_r600 : COS_Common<0x6F>;
 780   def ASHR_r600 : ASHR_Common<0x70>;
 781   def LSHR_r600 : LSHR_Common<0x71>;
 782   def LSHL_r600 : LSHL_Common<0x72>;
 783   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 784   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 785   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 786   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 787   def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
 788
 789 } // End AMDGPUGen.R600
 790
 791   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 792   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 793   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 794   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 795
 796 }
 797
 798 /* ----------------- */
 799 /* R700+ Trig helper */
 800 /* ----------------- */
 801
 802 /*
 803 class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
 804   (trig_inst R600_Reg32:$src),
 805   (trig_inst (fmul R600_Reg32:$src, (PI))))
 806 >;
 807 */
 808
 809 /* ---------------------- */
 810 /* Evergreen Instructions */
 811 /* ---------------------- */
 812
 813
 814 let Predicates = [isEG] in {
 815
 816 let Gen = AMDGPUGen.EG in {
 817
 818 def RAT_WRITE_CACHELESS_eg :
 819     EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
 820                                    R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
 821 {
 822   let RIM         = 0;
 823   /* XXX: Have a separate instruction for non-indexed writes. */
 824   let TYPE        = 1;
 825   let RW_REL      = 0;
 826   let ELEM_SIZE   = 0;
 827
 828   let ARRAY_SIZE  = 0;
 829   let COMP_MASK   = 1;
 830   let BURST_COUNT = 0;
 831   let VPM         = 0;
 832   let EOP         = 0;
 833   let MARK        = 0;
 834   let BARRIER     = 1;
 835 }
 836
 837 def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
 838                                 (ins R600_TReg32_X:$src, i32imm:$buffer_id),
 839                                 "VTX_READ_eg $dst, $src", []>
 840 {
 841 /*
 842   bits<7> DST_GPR;
 843   bits<7> SRC_GPR;
 844   bits<8> BUFFER_ID;
 845 */
 846   /* If any of these field below need to be calculated at compile time, and
 847    * a ins operand for them and move them to the list of operands above. */
 848
 849   /* XXX: This instruction is manual encoded, so none of these values are used.
 850    */
 851 /*
 852   bits<5> VC_INST          = 0; //VC_INST_FETCH
 853   bits<2> FETCH_TYPE       = 2;
 854   bits<1> FETCH_WHOLE_QUAD = 1;
 855   bits<1> SRC_REL          = 0;
 856   bits<2> SRC_SEL_X        = 0;
 857   bits<6> MEGA_FETCH_COUNT = 4;
 858 */
 859 /*
 860
 861   bits<1> DST_REL          = 0;
 862   bits<3> DST_SEL_X        = 0;
 863   bits<3> DST_SEL_Y        = 7; //Masked
 864   bits<3> DST_SEL_Z        = 7; //Masked
 865   bits<3> DST_SEL_W        = 7; //Masked
 866   bits<1> USE_CONST_FIELDS = 1; //Masked
 867   bits<6> DATA_FORMAT      = 0;
 868   bits<2> NUM_FORMAT_ALL   = 0;
 869   bits<1> FORMAT_COMP_ALL  = 0;
 870   bits<1> SRF_MODE_ALL     = 0;
 871 */
 872
 873 /*
 874   let Inst{4-0}   = VC_INST;
 875   let Inst{6-5}   = FETCH_TYPE;
 876   let Inst{7}     = FETCH_WHOLE_QUAD;
 877   let Inst{15-8}  = BUFFER_ID;
 878   let Inst{22-16} = SRC_GPR;
 879   let Inst{23}    = SRC_REL;
 880   let Inst{25-24} = SRC_SEL_X;
 881   let Inst{31-26} = MEGA_FETCH_COUNT;
 882 */
 883   /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you
 884    * from statically setting bits > 31.  This field will be set by
 885    * getMachineValueOp which can set bits > 31.
 886    */
 887 //  let Inst{32-38} = DST_GPR;
 888
 889   /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */
 890
 891 /*
 892   let Inst{39}    = DST_REL;
 893   let Inst{40}    = 0; //Reserved
 894   let Inst{43-41} = DST_SEL_X;
 895   let Inst{46-44} = DST_SEL_Y;
 896   let Inst{49-47} = DST_SEL_Z;
 897   let Inst{52-50} = DST_SEL_W;
 898   let Inst{53}    = USE_CONST_FIELDS;
 899   let Inst{59-54} = DATA_FORMAT;
 900   let Inst{61-60} = NUM_FORMAT_ALL;
 901   let Inst{62}    = FORMAT_COMP_ALL;
 902   let Inst{63}    = SRF_MODE_ALL;
 903 */
 904 }
 905
 906
 907
 908 } // End AMDGPUGen.EG
 909 /* XXX: Need to convert PTR to rat_id */
 910 /*
 911 def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
 912            (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
 913                                                   (f32 R600_Reg32:$value),
 914                                                    sel_x),
 915                                     (f32 ZERO), 0, R600_Reg32:$ptr)>;
 916 */
 917
 918 class VTX_Param_Read_Pattern <ValueType vt> : Pat <
 919     (vt (load_param ADDRParam:$mem)),
 920     (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>;
 921
 922 def : VTX_Param_Read_Pattern <f32>;
 923 def : VTX_Param_Read_Pattern <i32>;
 924
 925 } // End isEG Predicate
 926
 927 /* ------------------------------- */
 928 /* Evergreen / Cayman Instructions */
 929 /* ------------------------------- */
 930
 931 let Predicates = [isEGorCayman] in {
 932
 933 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
 934   (intr R600_Reg32:$src),
 935   (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
 936 >;
 937
 938 let Gen = AMDGPUGen.EG_CAYMAN in {
 939
 940   def MULADD_eg : MULADD_Common<0x14>;
 941   def ASHR_eg : ASHR_Common<0x15>;
 942   def LSHR_eg : LSHR_Common<0x16>;
 943   def LSHL_eg : LSHL_Common<0x17>;
 944   def CNDE_eg : CNDE_Common<0x19>;
 945   def CNDGT_eg : CNDGT_Common<0x1A>;
 946   def CNDGE_eg : CNDGE_Common<0x1B>;
 947   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 948   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>;
 949   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 950   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 951   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 952   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 953   def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 954   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 955   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 956   def SIN_eg : SIN_Common<0x8D>;
 957   def COS_eg : COS_Common<0x8E>;
 958   def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 959   def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 960   def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 961   def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 962   def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 963   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
 964   def DOT4_eg : DOT4_Common<0xBE>;
 965   def CUBE_eg : CUBE_Common<0xC0>;
 966
 967 } // End AMDGPUGen.EG_CAYMAN
 968
 969   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
 970   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
 971   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
 972   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 973
 974   def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
 975   def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
 976
 977 }
 978
 979 let Predicates = [isCayman] in {
 980
 981 let Gen = AMDGPUGen.CAYMAN in {
 982
 983   /* XXX: I'm not sure if this opcode is correct. */
 984   def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
 985
 986 } // End AMDGPUGen.CAYMAN
 987
 988 } // End isCayman
 989
 990 /* Other Instructions */
 991
 992 let isCodeGenOnly = 1 in {
 993 /*
 994   def SWIZZLE : AMDGPUShaderInst <
 995     (outs GPRV4F32:$dst),
 996     (ins GPRV4F32:$src0, i32imm:$src1),
 997     "SWIZZLE $dst, $src0, $src1",
 998     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
 999   >;
1000 */
1001
1002   def LAST : AMDGPUShaderInst <
1003     (outs),
1004     (ins),
1005     "LAST",
1006     []
1007   >;
1008
1009   def GET_CHAN : AMDGPUShaderInst <
1010     (outs R600_Reg32:$dst),
1011     (ins R600_Reg128:$src0, i32imm:$src1),
1012     "GET_CHAN $dst, $src0, $src1",
1013     []
1014   >;
1015
1016   def MULLIT : AMDGPUShaderInst <
1017     (outs R600_Reg128:$dst),
1018     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
1019     "MULLIT $dst, $src0, $src1",
1020     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
1021   >;
1022
1023 let usesCustomInserter = 1, isPseudo = 1 in {
1024
1025 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
1026   (outs R600_TReg32:$dst),
1027   (ins),
1028   asm,
1029   [(set R600_TReg32:$dst, (intr))]
1030 >;
1031
1032 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
1033 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
1034 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
1035
1036 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
1037 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
1038 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
1039
1040 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
1041 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
1042 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
1043
1044 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
1045                                      int_r600_read_global_size_x>;
1046 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
1047                                      int_r600_read_global_size_y>;
1048 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
1049                                      int_r600_read_global_size_z>;
1050
1051 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
1052                                     int_r600_read_local_size_x>;
1053 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
1054                                     int_r600_read_local_size_y>;
1055 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
1056                                     int_r600_read_local_size_z>;
1057
1058 def R600_LOAD_CONST : AMDGPUShaderInst <
1059   (outs R600_Reg32:$dst),
1060   (ins i32imm:$src0),
1061   "R600_LOAD_CONST $dst, $src0",
1062   [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1063 >;
1064
1065 def LOAD_INPUT : AMDGPUShaderInst <
1066   (outs R600_Reg32:$dst),
1067   (ins i32imm:$src),
1068   "LOAD_INPUT $dst, $src",
1069   [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1070 >;
1071
1072 def RESERVE_REG : AMDGPUShaderInst <
1073   (outs),
1074   (ins i32imm:$src),
1075   "RESERVE_REG $src",
1076   [(int_AMDGPU_reserve_reg imm:$src)]
1077 >;
1078
1079 def STORE_OUTPUT: AMDGPUShaderInst <
1080   (outs),
1081   (ins R600_Reg32:$src0, i32imm:$src1),
1082   "STORE_OUTPUT $src0, $src1",
1083   [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1084 >;
1085
1086 def TXD: AMDGPUShaderInst <
1087   (outs R600_Reg128:$dst),
1088   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1089   "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1090   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1091 >;
1092
1093 def TXD_SHADOW: AMDGPUShaderInst <
1094   (outs R600_Reg128:$dst),
1095   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1096   "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1097   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1098 >;
1099
1100 } // End usesCustomInserter = 1, isPseudo = 1
1101
1102 } // End isCodeGenOnly = 1
1103
1104
1105
1106 let isPseudo = 1 in {
1107
1108 def LOAD_VTX : AMDGPUShaderInst <
1109     (outs R600_Reg32:$dst),
1110     (ins MEMri:$mem),
1111     "LOAD_VTX",
1112     [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
1113 >;
1114
1115
1116 } //End isPseudo
1117
1118 //===----------------------------------------------------------------------===//
1119 // ISel Patterns
1120 //===----------------------------------------------------------------------===//
1121
1122 // SGT Reverse args
1123 def : Pat <
1124   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1125   (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1126 >;
1127
1128 // SGE Reverse args
1129 def : Pat <
1130   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1131   (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1132 >;
1133
1134 // SETGT_INT reverse args
1135 def : Pat <
1136   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1137   (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1138 >;
1139
1140 // SETGE_INT reverse args
1141 def : Pat <
1142   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1143   (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1144 >;
1145
1146 // SETGT_UINT reverse args
1147 def : Pat <
1148   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1149   (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1150 >;
1151
1152 // SETGE_UINT reverse args
1153 def : Pat <
1154   (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1155   (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1156 >;
1157
1158 // The next two patterns are special cases for handling 'true if ordered' and
1159 // 'true if unordered' conditionals.  The assumption here is that the behavior of
1160 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
1161 // described here:
1162 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
1163 // We assume that  SETE returns false when one of the operands is NAN and
1164 // SNE returns true when on of the operands is NAN
1165
1166 //SETE - 'true if ordered'
1167 def : Pat <
1168   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1169   (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1170 >;
1171
1172 //SNE - 'true if unordered'
1173 def : Pat <
1174   (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1175   (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1176 >;
1177
1178 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1179 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1180 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1181 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1182
1183 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1184 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1185 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1186 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1187
1188 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1189 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1190 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1191 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1192
1193 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1194 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1195 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1196 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1197
1198 } // End isR600toCayman Predicate