src/gallium/drivers/radeon/R600Instructions.td

   1 //===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 Tablegen instruction definitions
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "R600Intrinsics.td"
  15
  16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
  17                 InstrItinClass itin>
  18     : AMDGPUInst <outs, ins, asm, pattern> {
  19
  20   field bits<32> Inst;
  21         bit Trig = 0;
  22   bit Op3 = 0;
  23
  24   let Inst = inst;
  25   let Namespace = "AMDIL";
  26   let OutOperandList = outs;
  27   let InOperandList = ins;
  28   let AsmString = asm;
  29   let Pattern = pattern;
  30   let Itinerary = itin;
  31
  32   let TSFlags{4} = Trig;
  33   let TSFlags{5} = Op3;
  34 }
  35
  36 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
  37     AMDGPUInst <outs, ins, asm, pattern>
  38 {
  39   field bits<64> Inst;
  40
  41   let Namespace = "AMDIL";
  42 }
  43
  44 def MEMri : Operand<iPTRAny> {
  45   let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
  46 }
  47
  48 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
  49
  50 class R600_ALU {
  51
  52   bits<7> DST_GPR = 0;
  53   bits<9> SRC0_SEL = 0;
  54   bits<1> SRC0_NEG = 0;
  55   bits<9> SRC1_SEL = 0;
  56   bits<1> SRC1_NEG = 0;
  57   bits<1> CLAMP = 0;
  58
  59 }
  60
  61
  62 class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
  63                 InstrItinClass itin = AnyALU> :
  64   InstR600 <inst,
  65           (outs R600_Reg32:$dst),
  66           (ins R600_Reg32:$src, variable_ops),
  67           !strconcat(opName, " $dst, $src"),
  68           pattern,
  69           itin
  70   >;
  71
  72 class R600_2OP <bits<32> inst, string opName, list<dag> pattern,
  73                 InstrItinClass itin = AnyALU> :
  74   InstR600 <inst,
  75           (outs R600_Reg32:$dst),
  76           (ins R600_Reg32:$src0, R600_Reg32:$src1, variable_ops),
  77           !strconcat(opName, " $dst, $src0, $src1"),
  78           pattern,
  79           itin
  80   >;
  81
  82 class R600_3OP <bits<32> inst, string opName, list<dag> pattern,
  83                 InstrItinClass itin = AnyALU> :
  84   InstR600 <inst,
  85           (outs R600_Reg32:$dst),
  86           (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2, variable_ops),
  87           !strconcat(opName, " $dst, $src0, $src1, $src2"),
  88           pattern,
  89           itin>{
  90
  91     let Op3 = 1;
  92   }
  93
  94 class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
  95                       InstrItinClass itin = VecALU> :
  96   InstR600 <inst,
  97           (outs R600_Reg32:$dst),
  98           ins,
  99           asm,
 100           pattern,
 101           itin
 102
 103   >;
 104
 105 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
 106                 InstrItinClass itin = AnyALU> :
 107   InstR600 <inst,
 108           (outs R600_Reg128:$dst),
 109           (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
 110           !strconcat(opName, "$dst, $src0, $src1, $src2"),
 111           pattern,
 112           itin
 113   >;
 114
 115 def TEX_SHADOW : PatLeaf<
 116   (imm),
 117   [{uint32_t TType = (uint32_t)N->getZExtValue();
 118     return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12;
 119   }]
 120 >;
 121
 122 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
 123                  string asm> :
 124     InstR600ISA <outs, ins, asm, []>
 125 {
 126   bits<7>  RW_GPR;
 127   bits<7>  INDEX_GPR;
 128   bits<4>  RAT_ID;
 129
 130   bits<2>  RIM;
 131   bits<2>  TYPE;
 132   bits<1>  RW_REL;
 133   bits<2>  ELEM_SIZE;
 134
 135   bits<12> ARRAY_SIZE;
 136   bits<4>  COMP_MASK;
 137   bits<4>  BURST_COUNT;
 138   bits<1>  VPM;
 139   bits<1>  EOP;
 140   bits<1>  MARK;
 141   bits<1>  BARRIER;
 142
 143   /* CF_ALLOC_EXPORT_WORD0_RAT */
 144   let Inst{3-0}   = RAT_ID;
 145   let Inst{9-4}   = rat_inst;
 146   let Inst{10}    = 0; /* Reserved */
 147   let Inst{12-11} = RIM;
 148   let Inst{14-13} = TYPE;
 149   let Inst{21-15} = RW_GPR;
 150   let Inst{22}    = RW_REL;
 151   let Inst{29-23} = INDEX_GPR;
 152   let Inst{31-30} = ELEM_SIZE;
 153
 154   /* CF_ALLOC_EXPORT_WORD1_BUF */
 155   let Inst{43-32} = ARRAY_SIZE;
 156   let Inst{47-44} = COMP_MASK;
 157   let Inst{51-48} = BURST_COUNT;
 158   let Inst{52}    = VPM;
 159   let Inst{53}    = EOP;
 160   let Inst{61-54} = cf_inst;
 161   let Inst{62}    = MARK;
 162   let Inst{63}    = BARRIER;
 163 }
 164
 165 /*
 166 def store_global : PatFrag<(ops node:$value, node:$ptr),
 167                            (store node:$value, node:$ptr),
 168                            [{
 169                             const Value *Src;
 170                             const PointerType *Type;
 171                             if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
 172                                  PT = dyn_cast<PointerType>(Src->getType()))) {
 173                               return PT->getAddressSpace() == 1;
 174                             }
 175                             return false;
 176                            }]>;
 177
 178 */
 179
 180 def load_param : PatFrag<(ops node:$ptr),
 181                          (load node:$ptr),
 182                           [{
 183                            return true;
 184                            const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
 185                            if (Src) {
 186                                 PointerType * PT = dyn_cast<PointerType>(Src->getType());
 187                                 return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
 188                            }
 189                            return false;
 190                           }]>;
 191
 192 //class EG_CF <bits<32> inst, string asm> :
 193 //    InstR600 <inst, (outs), (ins), asm, []>;
 194
 195 /* XXX: We will use this when we emit the real ISA.
 196   bits<24> ADDR = 0;
 197   bits<3> JTS = 0;
 198
 199   bits<3> PC = 0;
 200   bits<5> CF_CONS = 0;
 201   bits<2> COND = 0;
 202   bits<6> COUNT = 0;
 203   bits<1> VPM = 0;
 204   bits<1> EOP = 0;
 205   bits<8> CF_INST = 0;
 206   bits<1> WQM = 0;
 207   bits<1> B = 0;
 208
 209   let Inst{23-0} = ADDR;
 210   let Inst{26-24} = JTS;
 211   let Inst{34-32} = PC;
 212   let Inst{39-35} = CF_CONST;
 213   let Inst{41-40} = COND;
 214   let Inst{47-42} = COUNT;
 215   let Inst{52} = VPM;
 216   let Inst{53} = EOP;
 217   let Inst{61-54} = CF_INST;
 218   let Inst{62} = WQM;
 219   let Inst{63} = B;
 220 //}
 221 */
 222 def isR600 : Predicate<"Subtarget.device()"
 223                             "->getGeneration() == AMDILDeviceInfo::HD4XXX">;
 224 def isEG : Predicate<"Subtarget.device()"
 225                             "->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
 226                             "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
 227 def isCayman : Predicate<"Subtarget.device()"
 228                             "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
 229 def isEGorCayman : Predicate<"Subtarget.device()"
 230                             "->getGeneration() == AMDILDeviceInfo::HD5XXX"
 231                             "|| Subtarget.device()->getGeneration() =="
 232                             "AMDILDeviceInfo::HD6XXX">;
 233
 234 def isR600toCayman : Predicate<
 235                      "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
 236
 237
 238 let Predicates = [isR600toCayman] in {
 239
 240 /* ------------------------------------------- */
 241 /* Common Instructions R600, R700, Evergreen, Cayman */
 242 /* ------------------------------------------- */
 243 let Gen = AMDGPUGen.R600_CAYMAN  in {
 244
 245 def ADD : R600_2OP <
 246   0x0, "ADD",
 247   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
 248 >;
 249
 250 // Non-IEEE MUL: 0 * anything = 0
 251 def MUL : R600_2OP <
 252   0x1, "MUL NON-IEEE",
 253   [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
 254 >;
 255
 256 def MUL_IEEE : R600_2OP <
 257   0x2, "MUL_IEEE",
 258   [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
 259 >;
 260
 261 def MAX : R600_2OP <
 262   0x3, "MAX",
 263   [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
 264 >;
 265
 266 def MIN : R600_2OP <
 267   0x4, "MIN",
 268   [(set R600_Reg32:$dst, (int_AMDIL_min R600_Reg32:$src0, R600_Reg32:$src1))]> {
 269   let AMDILOp = AMDILInst.MIN_f32;
 270 }
 271
 272 /* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
 273  * so some of the instruction names don't match the asm string.
 274  * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
 275  */
 276
 277 def SETE : R600_2OP <
 278   0x08, "SETE",
 279   [(set R600_Reg32:$dst, (int_AMDGPU_seq R600_Reg32:$src0, R600_Reg32:$src1))]> {
 280   let AMDILOp = AMDILInst.FEQ;
 281 }
 282
 283 def SGT : R600_2OP <
 284   0x09, "SETGT",
 285   [(set R600_Reg32:$dst, (int_AMDGPU_sgt R600_Reg32:$src0, R600_Reg32:$src1))]
 286 >;
 287
 288 def SGE : R600_2OP <
 289   0xA, "SETGE",
 290   [(set R600_Reg32:$dst, (int_AMDGPU_sge R600_Reg32:$src0, R600_Reg32:$src1))]> {
 291   let AMDILOp = AMDILInst.FGE;
 292 }
 293
 294 def SNE : R600_2OP <
 295   0xB, "SETNE",
 296   [(set R600_Reg32:$dst, (int_AMDGPU_sne R600_Reg32:$src0, R600_Reg32:$src1))]> {
 297   let AMDILOp = AMDILInst.FNE;
 298 }
 299
 300 def FRACT : R600_1OP <
 301   0x10, "FRACT",
 302   []> {
 303   let AMDILOp = AMDILInst.FRAC_f32;
 304 }
 305
 306 def TRUNC : R600_1OP <
 307   0x11, "TRUNC",
 308   [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))]
 309 >;
 310
 311 def CEIL : R600_1OP <
 312   0x12, "CEIL",
 313   [(set R600_Reg32:$dst, (int_AMDIL_round_posinf R600_Reg32:$src))]> {
 314   let AMDILOp = AMDILInst.ROUND_POSINF_f32;
 315 }
 316
 317 def RNDNE : R600_1OP <
 318   0x13, "RNDNE",
 319   [(set R600_Reg32:$dst, (int_AMDIL_round_nearest R600_Reg32:$src))]> {
 320   let AMDILOp = AMDILInst.ROUND_NEAREST_f32;
 321 }
 322
 323 def FLOOR : R600_1OP <
 324   0x14, "FLOOR",
 325   [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
 326 >;
 327
 328 def MOV : R600_1OP <0x19, "MOV", []>;
 329
 330 def KILLGT : R600_2OP <
 331   0x2D, "KILLGT",
 332   []
 333 >;
 334
 335 def AND_INT : R600_2OP <
 336   0x30, "AND_INT",
 337   []> {
 338   let AMDILOp = AMDILInst.AND_i32;
 339 }
 340
 341 def OR_INT : R600_2OP <
 342   0x31, "OR_INT",
 343   []>{
 344   let AMDILOp = AMDILInst.BINARY_OR_i32;
 345 }
 346
 347 def XOR_INT : R600_2OP <
 348   0x32, "XOR_INT",
 349   []
 350 >;
 351
 352 def NOT_INT : R600_1OP <
 353   0x33, "NOT_INT",
 354   []>{
 355   let AMDILOp = AMDILInst.BINARY_NOT_i32;
 356 }
 357
 358 def ADD_INT : R600_2OP <
 359   0x34, "ADD_INT",
 360   []>{
 361   let AMDILOp = AMDILInst.ADD_i32;
 362 }
 363
 364 def SUB_INT : R600_2OP <
 365         0x35, "SUB_INT",
 366         [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
 367 >;
 368
 369 def MAX_INT : R600_2OP <
 370   0x36, "MAX_INT",
 371   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 372
 373 def MIN_INT : R600_2OP <
 374   0x37, "MIN_INT",
 375   [(set R600_Reg32:$dst, (int_AMDGPU_imin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 376
 377 def MAX_UINT : R600_2OP <
 378   0x38, "MAX_UINT",
 379   [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
 380
 381 def MIN_UINT : R600_2OP <
 382   0x39, "MIN_UINT",
 383   [(set R600_Reg32:$dst, (int_AMDGPU_umin R600_Reg32:$src0, R600_Reg32:$src1))]>;
 384
 385
 386 def SETE_INT : R600_2OP <
 387   0x3A, "SETE_INT",
 388   []>{
 389   let AMDILOp = AMDILInst.IEQ;
 390 }
 391
 392 def SETGT_INT : R600_2OP <
 393   0x3B, "SGT_INT",
 394   []
 395 >;
 396
 397 def SETGE_INT : R600_2OP <
 398         0x3C, "SETGE_INT",
 399         []>{
 400   let AMDILOp = AMDILInst.IGE;
 401 }
 402
 403 def SETNE_INT : R600_2OP <
 404   0x3D, "SETNE_INT",
 405   []>{
 406   let AMDILOp = AMDILInst.INE;
 407 }
 408
 409 def SETGT_UINT : R600_2OP <
 410   0x3E, "SETGT_UINT",
 411   []>{
 412   let AMDILOp = AMDILInst.UGT;
 413 }
 414
 415 def SETGE_UINT : R600_2OP <
 416   0x3F, "SETGE_UINT",
 417   []>{
 418   let AMDILOp = AMDILInst.UGE;
 419 }
 420
 421 def CNDE_INT : R600_3OP <
 422         0x1C, "CNDE_INT",
 423   [(set (i32 R600_Reg32:$dst),
 424    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 425 >;
 426
 427 /* Texture instructions */
 428
 429
 430 def TEX_LD : R600_TEX <
 431   0x03, "TEX_LD",
 432   [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
 433 > {
 434 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
 435 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
 436 }
 437
 438 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
 439   0x04, "TEX_GET_TEXTURE_RESINFO",
 440   [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
 441 >;
 442
 443 def TEX_GET_GRADIENTS_H : R600_TEX <
 444   0x07, "TEX_GET_GRADIENTS_H",
 445   [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
 446 >;
 447
 448 def TEX_GET_GRADIENTS_V : R600_TEX <
 449   0x08, "TEX_GET_GRADIENTS_V",
 450   [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
 451 >;
 452
 453 def TEX_SET_GRADIENTS_H : R600_TEX <
 454   0x0B, "TEX_SET_GRADIENTS_H",
 455   []
 456 >;
 457
 458 def TEX_SET_GRADIENTS_V : R600_TEX <
 459   0x0C, "TEX_SET_GRADIENTS_V",
 460   []
 461 >;
 462
 463 def TEX_SAMPLE : R600_TEX <
 464   0x10, "TEX_SAMPLE",
 465   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 466 >;
 467
 468 def TEX_SAMPLE_C : R600_TEX <
 469   0x18, "TEX_SAMPLE_C",
 470   [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 471 >;
 472
 473 def TEX_SAMPLE_L : R600_TEX <
 474   0x11, "TEX_SAMPLE_L",
 475   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 476 >;
 477
 478 def TEX_SAMPLE_C_L : R600_TEX <
 479   0x19, "TEX_SAMPLE_C_L",
 480   [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 481 >;
 482
 483 def TEX_SAMPLE_LB : R600_TEX <
 484   0x12, "TEX_SAMPLE_LB",
 485   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 486 >;
 487
 488 def TEX_SAMPLE_C_LB : R600_TEX <
 489   0x1A, "TEX_SAMPLE_C_LB",
 490   [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 491 >;
 492
 493 def TEX_SAMPLE_G : R600_TEX <
 494   0x14, "TEX_SAMPLE_G",
 495   []
 496 >;
 497
 498 def TEX_SAMPLE_C_G : R600_TEX <
 499   0x1C, "TEX_SAMPLE_C_G",
 500   []
 501 >;
 502
 503 } // End Gen R600_CAYMAN
 504
 505 def KILP : Pat <
 506   (int_AMDGPU_kilp),
 507   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
 508 >;
 509
 510 def KIL : Pat <
 511   (int_AMDGPU_kill R600_Reg32:$src0),
 512   (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
 513 >;
 514
 515 /* Helper classes for common instructions */
 516
 517 class MUL_LIT_Common <bits<32> inst> : R600_3OP <
 518   inst, "MUL_LIT",
 519   []
 520 >;
 521
 522 class MULADD_Common <bits<32> inst> : R600_3OP <
 523   inst, "MULADD",
 524   [(set (f32 R600_Reg32:$dst),
 525    (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 526 >;
 527
 528 class CNDE_Common <bits<32> inst> : R600_3OP <
 529   inst, "CNDE",
 530   [(set (f32 R600_Reg32:$dst),
 531    (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 532 >;
 533
 534 class CNDGT_Common <bits<32> inst> : R600_3OP <
 535   inst, "CNDGT",
 536   []
 537 >;
 538
 539 class CNDGE_Common <bits<32> inst> : R600_3OP <
 540   inst, "CNDGE",
 541   [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
 542 >;
 543
 544 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
 545   inst,
 546   (ins R600_Reg128:$src0, R600_Reg128:$src1),
 547   "DOT4 $dst $src0, $src1",
 548   [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 549 >;
 550
 551 class CUBE_Common <bits<32> inst> : InstR600 <
 552   inst,
 553   (outs R600_Reg128:$dst),
 554   (ins R600_Reg128:$src),
 555   "CUBE $dst $src",
 556   [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
 557   VecALU
 558 >;
 559
 560 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
 561   inst, "EXP_IEEE",
 562   []> {
 563   let AMDILOp = AMDILInst.EXP_f32;
 564 }
 565
 566 class FLT_TO_INT_Common <bits<32> inst> : R600_1OP <
 567   inst, "FLT_TO_INT", []> {
 568   let AMDILOp = AMDILInst.FTOI;
 569 }
 570
 571 class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
 572   inst, "INT_TO_FLT", []> {
 573   let AMDILOp = AMDILInst.ITOF;
 574 }
 575
 576 class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 577   inst, "LOG_CLAMPED",
 578   []
 579 >;
 580
 581 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
 582   inst, "LOG_IEEE",
 583   []> {
 584   let AMDILOp = AMDILInst.LOG_f32;
 585 }
 586
 587 class LSHL_Common <bits<32> inst> : R600_2OP <
 588   inst, "LSHL $dst, $src0, $src1",
 589   [] >{
 590   let AMDILOp = AMDILInst.SHL_i32;
 591 }
 592
 593 class LSHR_Common <bits<32> inst> : R600_2OP <
 594   inst, "LSHR $dst, $src0, $src1",
 595   [] >{
 596   let AMDILOp = AMDILInst.USHR_i32;
 597 }
 598
 599 class ASHR_Common <bits<32> inst> : R600_2OP <
 600   inst, "ASHR $dst, $src0, $src1",
 601   [] >{
 602   let AMDILOp = AMDILInst.SHR_i32;
 603 }
 604
 605 class MULHI_INT_Common <bits<32> inst> : R600_2OP <
 606   inst, "MULHI_INT $dst, $src0, $src1",
 607   [] >{
 608   let AMDILOp = AMDILInst.SMULHI_i32;
 609 }
 610
 611 class MULHI_UINT_Common <bits<32> inst> : R600_2OP <
 612         inst, "MULHI $dst, $src0, $src1",
 613         []
 614 >;
 615
 616 class MULLO_INT_Common <bits<32> inst> : R600_2OP <
 617   inst, "MULLO_INT $dst, $src0, $src1",
 618   [] >{
 619   let AMDILOp = AMDILInst.SMUL_i32;
 620 }
 621
 622 class MULLO_UINT_Common <bits<32> inst> : R600_2OP <
 623   inst, "MULLO_UINT $dst, $src0, $src1",
 624   []
 625 >;
 626
 627 class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 628   inst, "RECIP_CLAMPED",
 629   []
 630 >;
 631
 632 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
 633   inst, "RECIP_IEEE",
 634   [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
 635   let AMDILOp = AMDILInst.RSQ_f32;
 636 }
 637
 638 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
 639   inst, "RECIP_INT $dst, $src",
 640   []
 641 >;
 642
 643 class RECIPSQRT_CLAMPED_Common <bits<32> inst> : R600_1OP <
 644   inst, "RECIPSQRT_CLAMPED",
 645   [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))]
 646 >;
 647
 648 class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 649   inst, "RECIPSQRT_IEEE",
 650   []
 651 >;
 652
 653 class SIN_Common <bits<32> inst> : R600_1OP <
 654   inst, "SIN",
 655   []>{
 656   let AMDILOp = AMDILInst.SIN_f32;
 657   let Trig = 1;
 658 }
 659
 660 class COS_Common <bits<32> inst> : R600_1OP <
 661   inst, "COS",
 662   []> {
 663   let AMDILOp = AMDILInst.COS_f32;
 664   let Trig = 1;
 665 }
 666
 667 /* Helper patterns for complex intrinsics */
 668 /* -------------------------------------- */
 669
 670 class DIV_Common <InstR600 recip_ieee> : Pat<
 671   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
 672   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 673 >;
 674
 675 class LRP_Common <InstR600 muladd> : Pat <
 676   (int_AMDGPU_lrp R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
 677   (muladd R600_Reg32:$src0, R600_Reg32:$src1, (MUL (SUB_f32 ONE, R600_Reg32:$src0), R600_Reg32:$src2))
 678 >;
 679
 680 class SSG_Common <InstR600 cndgt, InstR600 cndge> : Pat <
 681   (int_AMDGPU_ssg R600_Reg32:$src),
 682   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE)))
 683 >;
 684
 685 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
 686   (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
 687   (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
 688 >;
 689
 690 /* ---------------------- */
 691 /* R600 / R700 Only Instructions */
 692 /* ---------------------- */
 693
 694 let Predicates = [isR600] in {
 695
 696 let Gen = AMDGPUGen.R600 in {
 697
 698   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
 699   def MULADD_r600 : MULADD_Common<0x10>;
 700   def CNDE_r600 : CNDE_Common<0x18>;
 701   def CNDGT_r600 : CNDGT_Common<0x19>;
 702   def CNDGE_r600 : CNDGE_Common<0x1A>;
 703   def DOT4_r600 : DOT4_Common<0x50>;
 704   def CUBE_r600 : CUBE_Common<0x52>;
 705   def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
 706   def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
 707   def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
 708   def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
 709   def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
 710   def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
 711   def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
 712   def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
 713   def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
 714   def SIN_r600 : SIN_Common<0x6E>;
 715   def COS_r600 : COS_Common<0x6F>;
 716   def ASHR_r600 : ASHR_Common<0x70>;
 717   def LSHR_r600 : LSHR_Common<0x71>;
 718   def LSHL_r600 : LSHL_Common<0x72>;
 719   def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
 720   def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
 721   def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
 722   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
 723   def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
 724
 725 } // End AMDGPUGen.R600
 726
 727   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
 728   def LRP_r600 : LRP_Common<MULADD_r600>;
 729   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
 730   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
 731   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
 732
 733 }
 734
 735 /* ----------------- */
 736 /* R700+ Trig helper */
 737 /* ----------------- */
 738
 739 /*
 740 class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
 741   (trig_inst R600_Reg32:$src),
 742   (trig_inst (fmul R600_Reg32:$src, (PI))))
 743 >;
 744 */
 745
 746 /* ---------------------- */
 747 /* Evergreen Instructions */
 748 /* ---------------------- */
 749
 750
 751 let Predicates = [isEG] in {
 752
 753 let Gen = AMDGPUGen.EG in {
 754
 755 def RAT_WRITE_CACHELESS_eg :
 756     EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
 757                                    R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
 758 {
 759   let RIM         = 0;
 760   /* XXX: Have a separate instruction for non-indexed writes. */
 761   let TYPE        = 1;
 762   let RW_REL      = 0;
 763   let ELEM_SIZE   = 0;
 764
 765   let ARRAY_SIZE  = 0;
 766   let COMP_MASK   = 1;
 767   let BURST_COUNT = 0;
 768   let VPM         = 0;
 769   let EOP         = 0;
 770   let MARK        = 0;
 771   let BARRIER     = 1;
 772 }
 773
 774 def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
 775                                 (ins R600_TReg32_X:$src, i32imm:$buffer_id),
 776                                 "VTX_READ_eg $dst, $src", []>
 777 {
 778 /*
 779   bits<7> DST_GPR;
 780   bits<7> SRC_GPR;
 781   bits<8> BUFFER_ID;
 782 */
 783   /* If any of these field below need to be calculated at compile time, and
 784    * a ins operand for them and move them to the list of operands above. */
 785
 786   /* XXX: This instruction is manual encoded, so none of these values are used.
 787    */
 788 /*
 789   bits<5> VC_INST          = 0; //VC_INST_FETCH
 790   bits<2> FETCH_TYPE       = 2;
 791   bits<1> FETCH_WHOLE_QUAD = 1;
 792   bits<1> SRC_REL          = 0;
 793   bits<2> SRC_SEL_X        = 0;
 794   bits<6> MEGA_FETCH_COUNT = 4;
 795 */
 796 /*
 797
 798   bits<1> DST_REL          = 0;
 799   bits<3> DST_SEL_X        = 0;
 800   bits<3> DST_SEL_Y        = 7; //Masked
 801   bits<3> DST_SEL_Z        = 7; //Masked
 802   bits<3> DST_SEL_W        = 7; //Masked
 803   bits<1> USE_CONST_FIELDS = 1; //Masked
 804   bits<6> DATA_FORMAT      = 0;
 805   bits<2> NUM_FORMAT_ALL   = 0;
 806   bits<1> FORMAT_COMP_ALL  = 0;
 807   bits<1> SRF_MODE_ALL     = 0;
 808 */
 809
 810 /*
 811   let Inst{4-0}   = VC_INST;
 812   let Inst{6-5}   = FETCH_TYPE;
 813   let Inst{7}     = FETCH_WHOLE_QUAD;
 814   let Inst{15-8}  = BUFFER_ID;
 815   let Inst{22-16} = SRC_GPR;
 816   let Inst{23}    = SRC_REL;
 817   let Inst{25-24} = SRC_SEL_X;
 818   let Inst{31-26} = MEGA_FETCH_COUNT;
 819 */
 820   /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you
 821    * from statically setting bits > 31.  This field will be set by
 822    * getMachineValueOp which can set bits > 31.
 823    */
 824 //  let Inst{32-38} = DST_GPR;
 825
 826   /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */
 827
 828 /*
 829   let Inst{39}    = DST_REL;
 830   let Inst{40}    = 0; //Reserved
 831   let Inst{43-41} = DST_SEL_X;
 832   let Inst{46-44} = DST_SEL_Y;
 833   let Inst{49-47} = DST_SEL_Z;
 834   let Inst{52-50} = DST_SEL_W;
 835   let Inst{53}    = USE_CONST_FIELDS;
 836   let Inst{59-54} = DATA_FORMAT;
 837   let Inst{61-60} = NUM_FORMAT_ALL;
 838   let Inst{62}    = FORMAT_COMP_ALL;
 839   let Inst{63}    = SRF_MODE_ALL;
 840 */
 841 }
 842
 843
 844
 845 } // End AMDGPUGen.EG
 846 /* XXX: Need to convert PTR to rat_id */
 847 /*
 848 def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
 849            (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
 850                                                   (f32 R600_Reg32:$value),
 851                                                    sel_x),
 852                                     (f32 ZERO), 0, R600_Reg32:$ptr)>;
 853 */
 854
 855 class VTX_Param_Read_Pattern <ValueType vt> : Pat <
 856     (vt (load_param ADDRParam:$mem)),
 857     (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>;
 858
 859 def : VTX_Param_Read_Pattern <f32>;
 860 def : VTX_Param_Read_Pattern <i32>;
 861
 862 } // End isEG Predicate
 863
 864 /* ------------------------------- */
 865 /* Evergreen / Cayman Instructions */
 866 /* ------------------------------- */
 867
 868 let Predicates = [isEGorCayman] in {
 869
 870 class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
 871   (intr R600_Reg32:$src),
 872   (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
 873 >;
 874
 875 let Gen = AMDGPUGen.EG_CAYMAN in {
 876
 877   def MULADD_eg : MULADD_Common<0x14>;
 878   def ASHR_eg : ASHR_Common<0x15>;
 879   def LSHR_eg : LSHR_Common<0x16>;
 880   def LSHL_eg : LSHL_Common<0x17>;
 881   def CNDE_eg : CNDE_Common<0x19>;
 882   def CNDGT_eg : CNDGT_Common<0x1A>;
 883   def CNDGE_eg : CNDGE_Common<0x1B>;
 884   def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
 885   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>;
 886   def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
 887   def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
 888   def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
 889   def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
 890   def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
 891   def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
 892   def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
 893   def SIN_eg : SIN_Common<0x8D>;
 894   def COS_eg : COS_Common<0x8E>;
 895   def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
 896   def MULHI_INT_eg : MULHI_INT_Common<0x90>;
 897   def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
 898   def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
 899   def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
 900   def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
 901   def DOT4_eg : DOT4_Common<0xBE>;
 902   def CUBE_eg : CUBE_Common<0xC0>;
 903
 904 } // End AMDGPUGen.EG_CAYMAN
 905
 906   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
 907   def LRP_eg : LRP_Common<MULADD_eg>;
 908   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
 909   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
 910   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 911
 912   def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
 913   def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
 914
 915 }
 916
 917 let Predicates = [isCayman] in {
 918
 919 let Gen = AMDGPUGen.CAYMAN in {
 920
 921   /* XXX: I'm not sure if this opcode is correct. */
 922   def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
 923
 924 } // End AMDGPUGen.CAYMAN
 925
 926 } // End isCayman
 927
 928 /* Other Instructions */
 929
 930 let isCodeGenOnly = 1 in {
 931 /*
 932   def SWIZZLE : AMDGPUShaderInst <
 933     (outs GPRV4F32:$dst),
 934     (ins GPRV4F32:$src0, i32imm:$src1),
 935     "SWIZZLE $dst, $src0, $src1",
 936     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
 937   >;
 938 */
 939
 940   def LAST : AMDGPUShaderInst <
 941     (outs),
 942     (ins),
 943     "LAST",
 944     []
 945   >;
 946
 947   def GET_CHAN : AMDGPUShaderInst <
 948     (outs R600_Reg32:$dst),
 949     (ins R600_Reg128:$src0, i32imm:$src1),
 950     "GET_CHAN $dst, $src0, $src1",
 951     []
 952   >;
 953
 954   def MULLIT : AMDGPUShaderInst <
 955     (outs R600_Reg128:$dst),
 956     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
 957     "MULLIT $dst, $src0, $src1",
 958     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
 959   >;
 960
 961 let usesCustomInserter = 1, isPseudo = 1 in {
 962
 963 class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
 964   (outs R600_TReg32:$dst),
 965   (ins),
 966   asm,
 967   [(set R600_TReg32:$dst, (intr))]
 968 >;
 969
 970 def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
 971 def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>;
 972 def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>;
 973
 974 def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
 975 def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>;
 976 def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>;
 977
 978 def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
 979 def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>;
 980 def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>;
 981
 982 def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X",
 983                                      int_r600_read_global_size_x>;
 984 def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y",
 985                                      int_r600_read_global_size_y>;
 986 def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z",
 987                                      int_r600_read_global_size_z>;
 988
 989 def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X",
 990                                     int_r600_read_local_size_x>;
 991 def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y",
 992                                     int_r600_read_local_size_y>;
 993 def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
 994                                     int_r600_read_local_size_z>;
 995
 996 def R600_LOAD_CONST : AMDGPUShaderInst <
 997   (outs R600_Reg32:$dst),
 998   (ins i32imm:$src0),
 999   "R600_LOAD_CONST $dst, $src0",
1000   [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1001 >;
1002
1003 def LOAD_INPUT : AMDGPUShaderInst <
1004   (outs R600_Reg32:$dst),
1005   (ins i32imm:$src),
1006   "LOAD_INPUT $dst, $src",
1007   [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))]
1008 >;
1009
1010 def RESERVE_REG : AMDGPUShaderInst <
1011   (outs),
1012   (ins i32imm:$src),
1013   "RESERVE_REG $src",
1014   [(int_AMDGPU_reserve_reg imm:$src)]
1015 >;
1016
1017 def STORE_OUTPUT: AMDGPUShaderInst <
1018   (outs),
1019   (ins R600_Reg32:$src0, i32imm:$src1),
1020   "STORE_OUTPUT $src0, $src1",
1021   [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)]
1022 >;
1023
1024 def TXD: AMDGPUShaderInst <
1025   (outs R600_Reg128:$dst),
1026   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1027   "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1028   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, imm:$src4))]
1029 >;
1030
1031 def TXD_SHADOW: AMDGPUShaderInst <
1032   (outs R600_Reg128:$dst),
1033   (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1034   "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1035   [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$src3, TEX_SHADOW:$src4))]
1036 >;
1037
1038 } // End usesCustomInserter = 1, isPseudo = 1
1039
1040 } // End isCodeGenOnly = 1
1041
1042
1043
1044 let isPseudo = 1 in {
1045
1046 def LOAD_VTX : AMDGPUShaderInst <
1047     (outs R600_Reg32:$dst),
1048     (ins MEMri:$mem),
1049     "LOAD_VTX",
1050     [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
1051 >;
1052
1053
1054 } //End isPseudo
1055
1056 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sel_x>;
1057 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sel_y>;
1058 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sel_z>;
1059 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sel_w>;
1060
1061 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 4, sel_x>;
1062 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 5, sel_y>;
1063 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 6, sel_z>;
1064 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 7, sel_w>;
1065
1066 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sel_x>;
1067 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sel_y>;
1068 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sel_z>;
1069 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sel_w>;
1070
1071 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 4, sel_x>;
1072 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 5, sel_y>;
1073 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 6, sel_z>;
1074 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 7, sel_w>;
1075
1076 } // End isR600toCayman Predicate