src/gallium/drivers/radeon/R600RegisterInfo.cpp

   1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // The file contains the R600 implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "R600RegisterInfo.h"
  15 #include "AMDGPUTargetMachine.h"
  16 #include "R600MachineFunctionInfo.h"
  17
  18 using namespace llvm;
  19
  20 R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
  21     const TargetInstrInfo &tii)
  22 : AMDGPURegisterInfo(tm, tii),
  23   TM(tm),
  24   TII(tii)
  25   { }
  26
  27 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
  28 {
  29   BitVector Reserved(getNumRegs());
  30   const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
  31
  32   Reserved.set(AMDGPU::ZERO);
  33   Reserved.set(AMDGPU::HALF);
  34   Reserved.set(AMDGPU::ONE);
  35   Reserved.set(AMDGPU::ONE_INT);
  36   Reserved.set(AMDGPU::NEG_HALF);
  37   Reserved.set(AMDGPU::NEG_ONE);
  38   Reserved.set(AMDGPU::PV_X);
  39   Reserved.set(AMDGPU::ALU_LITERAL_X);
  40
  41   for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(),
  42                         E = AMDGPU::R600_CReg32RegClass.end(); I != E; ++I) {
  43     Reserved.set(*I);
  44   }
  45
  46   for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
  47                                     E = MFI->ReservedRegs.end(); I != E; ++I) {
  48     Reserved.set(*I);
  49   }
  50
  51   return Reserved;
  52 }
  53
  54 const TargetRegisterClass *
  55 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
  56 {
  57   switch (rc->getID()) {
  58   case AMDGPU::GPRF32RegClassID:
  59   case AMDGPU::GPRI32RegClassID:
  60     return &AMDGPU::R600_Reg32RegClass;
  61   default: return rc;
  62   }
  63 }
  64
  65 unsigned R600RegisterInfo::getHWRegIndex(unsigned reg) const
  66 {
  67   switch(reg) {
  68   case AMDGPU::ZERO: return 248;
  69   case AMDGPU::ONE:
  70   case AMDGPU::NEG_ONE: return 249;
  71   case AMDGPU::ONE_INT: return 250;
  72   case AMDGPU::HALF:
  73   case AMDGPU::NEG_HALF: return 252;
  74   case AMDGPU::ALU_LITERAL_X: return 253;
  75   default: return getHWRegIndexGen(reg);
  76   }
  77 }
  78
  79 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
  80 {
  81   switch(reg) {
  82   case AMDGPU::ZERO:
  83   case AMDGPU::ONE:
  84   case AMDGPU::ONE_INT:
  85   case AMDGPU::NEG_ONE:
  86   case AMDGPU::HALF:
  87   case AMDGPU::NEG_HALF:
  88   case AMDGPU::ALU_LITERAL_X:
  89     return 0;
  90   default: return getHWRegChanGen(reg);
  91   }
  92 }
  93
  94 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
  95                                                                    MVT VT) const
  96 {
  97   switch(VT.SimpleTy) {
  98   default:
  99   case MVT::i32: return AMDGPU::R600_TReg32RegisterClass;
 100   }
 101 }
 102 #include "R600HwRegInfo.include"