src/gallium/drivers/radeon/R600RegisterInfo.cpp

   1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // The file contains the R600 implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "R600RegisterInfo.h"
  15 #include "AMDGPUTargetMachine.h"
  16 #include "R600MachineFunctionInfo.h"
  17
  18 using namespace llvm;
  19
  20 R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
  21     const TargetInstrInfo &tii)
  22 : AMDGPURegisterInfo(tm, tii),
  23   TM(tm),
  24   TII(tii)
  25   { }
  26
  27 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
  28 {
  29   BitVector Reserved(getNumRegs());
  30   const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
  31
  32   Reserved.set(AMDGPU::ZERO);
  33   Reserved.set(AMDGPU::HALF);
  34   Reserved.set(AMDGPU::ONE);
  35   Reserved.set(AMDGPU::ONE_INT);
  36   Reserved.set(AMDGPU::NEG_HALF);
  37   Reserved.set(AMDGPU::NEG_ONE);
  38   Reserved.set(AMDGPU::PV_X);
  39   Reserved.set(AMDGPU::ALU_LITERAL_X);
  40   Reserved.set(AMDGPU::PREDICATE_BIT);
  41   Reserved.set(AMDGPU::PRED_SEL_OFF);
  42   Reserved.set(AMDGPU::PRED_SEL_ZERO);
  43   Reserved.set(AMDGPU::PRED_SEL_ONE);
  44
  45   for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(),
  46                         E = AMDGPU::R600_CReg32RegClass.end(); I != E; ++I) {
  47     Reserved.set(*I);
  48   }
  49
  50   for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
  51                                     E = MFI->ReservedRegs.end(); I != E; ++I) {
  52     Reserved.set(*I);
  53   }
  54
  55   return Reserved;
  56 }
  57
  58 const TargetRegisterClass *
  59 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
  60 {
  61   switch (rc->getID()) {
  62   case AMDGPU::GPRF32RegClassID:
  63   case AMDGPU::GPRI32RegClassID:
  64     return &AMDGPU::R600_Reg32RegClass;
  65   default: return rc;
  66   }
  67 }
  68
  69 unsigned R600RegisterInfo::getHWRegIndex(unsigned reg) const
  70 {
  71   switch(reg) {
  72   case AMDGPU::ZERO: return 248;
  73   case AMDGPU::ONE:
  74   case AMDGPU::NEG_ONE: return 249;
  75   case AMDGPU::ONE_INT: return 250;
  76   case AMDGPU::HALF:
  77   case AMDGPU::NEG_HALF: return 252;
  78   case AMDGPU::ALU_LITERAL_X: return 253;
  79   case AMDGPU::PREDICATE_BIT:
  80   case AMDGPU::PRED_SEL_OFF:
  81   case AMDGPU::PRED_SEL_ZERO:
  82   case AMDGPU::PRED_SEL_ONE:
  83     return 0;
  84   default: return getHWRegIndexGen(reg);
  85   }
  86 }
  87
  88 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
  89 {
  90   switch(reg) {
  91   case AMDGPU::ZERO:
  92   case AMDGPU::ONE:
  93   case AMDGPU::ONE_INT:
  94   case AMDGPU::NEG_ONE:
  95   case AMDGPU::HALF:
  96   case AMDGPU::NEG_HALF:
  97   case AMDGPU::ALU_LITERAL_X:
  98   case AMDGPU::PREDICATE_BIT:
  99   case AMDGPU::PRED_SEL_OFF:
 100   case AMDGPU::PRED_SEL_ZERO:
 101   case AMDGPU::PRED_SEL_ONE:
 102     return 0;
 103   default: return getHWRegChanGen(reg);
 104   }
 105 }
 106
 107 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
 108                                                                    MVT VT) const
 109 {
 110   switch(VT.SimpleTy) {
 111   default:
 112   case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
 113   }
 114 }
 115
 116 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const
 117 {
 118   switch (Channel) {
 119     default: assert(!"Invalid channel index"); return 0;
 120     case 0: return AMDGPU::sel_x;
 121     case 1: return AMDGPU::sel_y;
 122     case 2: return AMDGPU::sel_z;
 123     case 3: return AMDGPU::sel_w;
 124   }
 125 }
 126
 127 #include "R600HwRegInfo.include"