src/gallium/drivers/radeon/R600Schedule.td

   1 //===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // R600 has a VLIW architecture.  On pre-cayman cards there are 5 instruction
  11 // slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS.  For cayman cards, the TRANS
  12 // slot has been removed.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16
  17 def ALU_X : FuncUnit;
  18 def ALU_Y : FuncUnit;
  19 def ALU_Z : FuncUnit;
  20 def ALU_W : FuncUnit;
  21 def TRANS : FuncUnit;
  22
  23
  24 def AnyALU : InstrItinClass;
  25 def VecALU : InstrItinClass;
  26 def TransALU : InstrItinClass;
  27
  28 def R600_EG_Itin : ProcessorItineraries <
  29   [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS],
  30   [],
  31   [
  32     InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
  33     InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>,
  34     InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>
  35   ]
  36 >;