src/gallium/drivers/radeon/SIGenRegisterInfo.pl

   1 #===-- SIGenRegisterInfo.pl - Script for generating register info files ----===#
   2 #
   3 #                     The LLVM Compiler Infrastructure
   4 #
   5 # This file is distributed under the University of Illinois Open Source
   6 # License. See LICENSE.TXT for details.
   7 #
   8 #===------------------------------------------------------------------------===#
   9 #
  10 # This perl script prints to stdout .td code to be used as SIRegisterInfo.td
  11 # it also generates a file called SIHwRegInfo.include, which contains helper
  12 # functions for determining the hw encoding of registers.
  13 #
  14 #===------------------------------------------------------------------------===#
  15
  16 use strict;
  17 use warnings;
  18
  19 my $SGPR_COUNT = 104;
  20 my $VGPR_COUNT = 256;
  21
  22 my $SGPR_MAX_IDX = $SGPR_COUNT - 1;
  23 my $VGPR_MAX_IDX = $VGPR_COUNT - 1;
  24
  25 my $INDEX_FILE = defined($ARGV[0]) ? $ARGV[0] : '';
  26
  27 print <<STRING;
  28
  29 let Namespace = "AMDGPU" in {
  30   def low : SubRegIndex;
  31   def high : SubRegIndex;
  32
  33   def sub0 : SubRegIndex;
  34   def sub1 : SubRegIndex;
  35   def sub2 : SubRegIndex;
  36   def sub3 : SubRegIndex;
  37   def sub4 : SubRegIndex;
  38   def sub5 : SubRegIndex;
  39   def sub6 : SubRegIndex;
  40   def sub7 : SubRegIndex;
  41 }
  42
  43 class SIReg <string n> : Register<n> {
  44   let Namespace = "AMDGPU";
  45 }
  46
  47 class SI_64 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
  48   let Namespace = "AMDGPU";
  49   let SubRegIndices = [low, high];
  50 }
  51
  52 class SI_128 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
  53   let Namespace = "AMDGPU";
  54   let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
  55 }
  56
  57 class SI_256 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
  58   let Namespace = "AMDGPU";
  59   let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
  60 }
  61
  62 class SGPR_32 <bits<8> num, string name> : SIReg<name> {
  63   field bits<8> Num;
  64
  65   let Num = num;
  66 }
  67
  68
  69 class VGPR_32 <bits<9> num, string name> : SIReg<name> {
  70   field bits<9> Num;
  71
  72   let Num = num;
  73 }
  74
  75 class SGPR_64 <bits<8> num, string name, list<Register> subregs> :
  76     SI_64 <name, subregs>;
  77
  78 class VGPR_64 <bits<9> num, string name, list<Register> subregs> :
  79     SI_64 <name, subregs>;
  80
  81 class SGPR_128 <bits<8> num, string name, list<Register> subregs> :
  82     SI_128 <name, subregs>;
  83
  84 class VGPR_128 <bits<9> num, string name, list<Register> subregs> :
  85     SI_128 <name, subregs>;
  86
  87 class SGPR_256 <bits<8> num, string name, list<Register> subregs> :
  88     SI_256 <name, subregs>;
  89
  90 def VCC : SIReg<"VCC">;
  91 def EXEC_LO : SIReg<"EXEC LO">;
  92 def EXEC_HI : SIReg<"EXEC HI">;
  93 def EXEC : SI_64<"EXEC", [EXEC_LO,EXEC_HI]>;
  94 def SCC : SIReg<"SCC">;
  95 def SREG_LIT_0 : SIReg <"S LIT 0">;
  96 def SI_LITERAL_CONSTANT : SIReg<"LITERAL CONSTANT">;
  97
  98 def M0 : SIReg <"M0">;
  99
 100 //Interpolation registers
 101
 102 def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">;
 103 def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">;
 104 def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">;
 105 def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">;
 106 def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">;
 107 def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">;
 108 def PERSP_I_W : SIReg <"PERSP_I_W">;
 109 def PERSP_J_W : SIReg <"PERSP_J_W">;
 110 def PERSP_1_W : SIReg <"PERSP_1_W">;
 111 def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">;
 112 def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">;
 113 def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">;
 114 def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">;
 115 def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">;
 116 def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">;
 117 def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">;
 118 def POS_X_FLOAT : SIReg <"POS_X_FLOAT">;
 119 def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">;
 120 def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">;
 121 def POS_W_FLOAT : SIReg <"POS_W_FLOAT">;
 122 def FRONT_FACE : SIReg <"FRONT_FACE">;
 123 def ANCILLARY : SIReg <"ANCILLARY">;
 124 def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">;
 125 def POS_FIXED_PT : SIReg <"POS_FIXED_PT">;
 126
 127 STRING
 128
 129 #32 bit register
 130
 131 my @SGPR;
 132 for (my $i = 0; $i < $SGPR_COUNT; $i++) {
 133   print "def SGPR$i : SGPR_32 <$i, \"SGPR$i\">;\n";
 134   $SGPR[$i] = "SGPR$i";
 135 }
 136
 137 my @VGPR;
 138 for (my $i = 0; $i < $VGPR_COUNT; $i++) {
 139   print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\">;\n";
 140   $VGPR[$i] = "VGPR$i";
 141 }
 142
 143 print <<STRING;
 144
 145 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 146     (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX),  SREG_LIT_0, M0, EXEC_LO, EXEC_HI)
 147 >;
 148
 149 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 150     (add (sequence "VGPR%u", 0, $VGPR_MAX_IDX),
 151     PERSP_SAMPLE_I, PERSP_SAMPLE_J,
 152     PERSP_CENTER_I, PERSP_CENTER_J,
 153     PERSP_CENTROID_I, PERSP_CENTROID_J,
 154     PERSP_I_W, PERSP_J_W, PERSP_1_W,
 155     LINEAR_SAMPLE_I, LINEAR_SAMPLE_J,
 156     LINEAR_CENTER_I, LINEAR_CENTER_J,
 157     LINEAR_CENTROID_I, LINEAR_CENTROID_J,
 158     LINE_STIPPLE_TEX_COORD,
 159     POS_X_FLOAT,
 160     POS_Y_FLOAT,
 161     POS_Z_FLOAT,
 162     POS_W_FLOAT,
 163     FRONT_FACE,
 164     ANCILLARY,
 165     SAMPLE_COVERAGE,
 166     POS_FIXED_PT
 167     )
 168 >;
 169
 170 def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 171     (add VReg_32, SReg_32)
 172 >;
 173
 174 def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
 175 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
 176 def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
 177 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
 178
 179
 180 STRING
 181
 182 my @subregs_64 = ('low', 'high');
 183 my @subregs_128 = ('sel_x', 'sel_y', 'sel_z', 'sel_w');
 184 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
 185
 186 my @SGPR64 = print_sgpr_class(64, \@subregs_64, ('i64'));
 187 my @SGPR128 = print_sgpr_class(128, \@subregs_128, ('v4f32', 'v4i32'));
 188 my @SGPR256 = print_sgpr_class(256, \@subregs_256, ('v8i32'));
 189
 190 my @VGPR64 = print_vgpr_class(64, \@subregs_64, ('i64'));
 191 my @VGPR128 = print_vgpr_class(128, \@subregs_128, ('v4f32'));
 192
 193
 194 my $sgpr64_list = join(',', @SGPR64);
 195 my $vgpr64_list = join(',', @VGPR64);
 196 print <<STRING;
 197
 198 def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64,
 199     (add $sgpr64_list, $vgpr64_list)
 200 >;
 201
 202 STRING
 203
 204 if ($INDEX_FILE ne '') {
 205   open(my $fh, ">", $INDEX_FILE);
 206   my %hw_values;
 207
 208   for (my $i = 0; $i <= $#SGPR; $i++) {
 209     push (@{$hw_values{$i}}, $SGPR[$i]);
 210   }
 211
 212   for (my $i = 0; $i <= $#SGPR64; $i++) {
 213     push (@{$hw_values{$i * 2}}, $SGPR64[$i])
 214   }
 215
 216   for (my $i = 0; $i <= $#SGPR128; $i++) {
 217     push (@{$hw_values{$i * 4}}, $SGPR128[$i]);
 218   }
 219
 220   for (my $i = 0; $i <= $#SGPR256; $i++) {
 221     push (@{$hw_values{$i * 8}}, $SGPR256[$i]);
 222   }
 223
 224   for (my $i = 0; $i <= $#VGPR; $i++) {
 225     push (@{$hw_values{$i}}, $VGPR[$i]);
 226   }
 227   for (my $i = 0; $i <= $#VGPR64; $i++) {
 228     push (@{$hw_values{$i * 2}}, $VGPR64[$i]);
 229   }
 230
 231   for (my $i = 0; $i <= $#VGPR128; $i++) {
 232     push (@{$hw_values{$i * 4}}, $VGPR128[$i]);
 233   }
 234
 235
 236   print $fh "unsigned SIRegisterInfo::getHWRegNum(unsigned reg) const\n{\n  switch(reg) {\n";
 237   for my $key (keys(%hw_values)) {
 238     my @names = @{$hw_values{$key}};
 239     for my $regname (@names) {
 240       print $fh "  case AMDGPU::$regname:\n"
 241     }
 242     print $fh "    return $key;\n";
 243   }
 244   print $fh "  default: assert(!\"Unknown Register\"); return 0;\n  }\n}\n"
 245 }
 246
 247
 248
 249
 250 sub print_sgpr_class {
 251   my ($reg_width, $sub_reg_ref, @types) = @_;
 252   return print_reg_class('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types);
 253 }
 254
 255 sub print_vgpr_class {
 256   my ($reg_width, $sub_reg_ref, @types) = @_;
 257   return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
 258 }
 259
 260 sub print_reg_class {
 261   my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_;
 262   my @registers;
 263   my $component_count = $reg_width / 32;
 264
 265   for (my $i = 0; $i < $reg_count; $i += $component_count) {
 266     my $reg_name = $reg_prefix . $i . '_' . $reg_width;
 267     my @sub_regs;
 268     for (my $idx = 0; $idx < $component_count; $idx++) {
 269       my $sub_idx = $i + $idx;
 270       push(@sub_regs, $reg_prefix . $sub_idx);
 271     }
 272     print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n";
 273     push (@registers, $reg_name);
 274   }
 275
 276   #Add VCC to SReg_64
 277   if ($class_prefix eq 'SReg' and $reg_width == 64) {
 278     push (@registers, 'VCC')
 279   }
 280
 281   #Add EXEC to SReg_64
 282   if ($class_prefix eq 'SReg' and $reg_width == 64) {
 283     push (@registers, 'EXEC')
 284   }
 285
 286   my $reg_list = join(', ', @registers);
 287
 288   print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n  (add $reg_list)\n>{\n";
 289   print "  let SubRegClasses = [($class_prefix\_", ($reg_width / $component_count) , ' ', join(', ', @{$sub_reg_ref}), ")];\n}\n";
 290   return @registers;
 291 }