1 #===-- SIGenRegisterInfo.pl - TODO: Add brief description -------===#
3 # The LLVM Compiler Infrastructure
5 # This file is distributed under the University of Illinois Open Source
6 # License. See LICENSE.TXT for details.
8 #===----------------------------------------------------------------------===#
10 # TODO: Add full description
12 #===----------------------------------------------------------------------===#
21 my $SGPR_MAX_IDX = $SGPR_COUNT - 1;
22 my $VGPR_MAX_IDX = $VGPR_COUNT - 1;
24 my $INDEX_FILE = defined($ARGV[0]) ?
$ARGV[0] : '';
28 let Namespace = "AMDIL" in {
29 def low : SubRegIndex;
30 def high : SubRegIndex;
32 def sub0 : SubRegIndex;
33 def sub1 : SubRegIndex;
34 def sub2 : SubRegIndex;
35 def sub3 : SubRegIndex;
36 def sub4 : SubRegIndex;
37 def sub5 : SubRegIndex;
38 def sub6 : SubRegIndex;
39 def sub7 : SubRegIndex;
42 class SIReg <string n> : Register<n> {
43 let Namespace = "AMDIL";
46 class SI_64 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
47 let Namespace = "AMDIL";
48 let SubRegIndices = [low, high];
51 class SI_128 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
52 let Namespace = "AMDIL";
53 let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
56 class SI_256 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
57 let Namespace = "AMDIL";
58 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
61 class SGPR_32 <bits<8> num, string name> : SIReg<name> {
68 class VGPR_32 <bits<9> num, string name, Register gprf32_alias> : SIReg<name> {
72 let Aliases = [gprf32_alias];
75 class SGPR_64 <bits<8> num, string name, list<Register> subregs> :
76 SI_64 <name, subregs>;
78 class VGPR_64 <bits<9> num, string name, list<Register> subregs> :
79 SI_64 <name, subregs>;
81 class SGPR_128 <bits<8> num, string name, list<Register> subregs> :
82 SI_128 <name, subregs>;
84 class VGPR_128 <bits<9> num, string name, list<Register> subregs> :
85 SI_128 <name, subregs>;
87 class SGPR_256 <bits<8> num, string name, list<Register> subregs> :
88 SI_256 <name, subregs>;
90 def VCC : SIReg<"VCC">;
91 def SCC : SIReg<"SCC">;
92 def SREG_LIT_0 : SIReg <"S LIT 0">;
94 def M0 : SIReg <"M0">;
96 //Interpolation registers
98 def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">;
99 def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">;
100 def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">;
101 def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">;
102 def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">;
103 def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">;
104 def PERSP_I_W : SIReg <"PERSP_I_W">;
105 def PERSP_J_W : SIReg <"PERSP_J_W">;
106 def PERSP_1_W : SIReg <"PERSP_1_W">;
107 def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">;
108 def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">;
109 def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">;
110 def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">;
111 def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">;
112 def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">;
113 def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">;
114 def POS_X_FLOAT : SIReg <"POS_X_FLOAT">;
115 def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">;
116 def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">;
117 def POS_W_FLOAT : SIReg <"POS_W_FLOAT">;
118 def FRONT_FACE : SIReg <"FRONT_FACE">;
119 def ANCILLARY : SIReg <"ANCILLARY">;
120 def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">;
121 def POS_FIXED_PT : SIReg <"POS_FIXED_PT">;
128 for (my $i = 0; $i < $SGPR_COUNT; $i++) {
129 print "def SGPR$i : SGPR_32 <$i, \"SGPR$i\">;\n";
130 $SGPR[$i] = "SGPR$i";
135 for (my $i = 0; $i < $VGPR_COUNT; $i++) {
136 my $gprf32_num = $i + 1;
137 my $gprf32_name = "R$gprf32_num";
138 print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\", $gprf32_name>;\n";
139 $VGPR[$i] = "VGPR$i";
140 $GPRF32[$i] = $gprf32_name;
145 def SReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
146 (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0)
149 def VReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
150 (add (sequence "VGPR%u", 0, $VGPR_MAX_IDX),
151 PERSP_SAMPLE_I, PERSP_SAMPLE_J,
152 PERSP_CENTER_I, PERSP_CENTER_J,
153 PERSP_CENTROID_I, PERSP_CENTROID_J,
154 PERSP_I_W, PERSP_J_W, PERSP_1_W,
155 LINEAR_SAMPLE_I, LINEAR_SAMPLE_J,
156 LINEAR_CENTER_I, LINEAR_CENTER_J,
157 LINEAR_CENTROID_I, LINEAR_CENTROID_J,
158 LINE_STIPPLE_TEX_COORD,
170 def AllReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
173 (sequence "R%u", 1, $VGPR_COUNT))
176 def CCReg : RegisterClass<"AMDIL", [f32], 32, (add VCC, SCC)>;
180 my @subregs_64 = ('low', 'high');
181 my @subregs_128 = ('sel_x', 'sel_y', 'sel_z', 'sel_w');
182 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
184 my @SGPR64 = print_sgpr_class
(64, \
@subregs_64, ('i64', 'iPTRAny'));
185 my @SGPR128 = print_sgpr_class
(128, \
@subregs_128, ('v4f32'));
186 my @SGPR256 = print_sgpr_class
(256, \
@subregs_256, ('v8i32'));
188 my @VGPR64 = print_vgpr_class
(64, \
@subregs_64, ('i64'));
189 my @VGPR128 = print_vgpr_class
(128, \
@subregs_128, ('v4f32'));
192 my $sgpr64_list = join(',', @SGPR64);
193 my $vgpr64_list = join(',', @VGPR64);
196 def AllReg_64 : RegisterClass<"AMDIL", [f64, i64], 64,
197 (add $sgpr64_list, $vgpr64_list)
202 if ($INDEX_FILE ne '') {
203 open(my $fh, ">", $INDEX_FILE);
206 for (my $i = 0; $i <= $#SGPR; $i++) {
207 push (@
{$hw_values{$i}}, $SGPR[$i]);
210 for (my $i = 0; $i <= $#SGPR64; $i++) {
211 push (@
{$hw_values{$i * 2}}, $SGPR64[$i])
214 for (my $i = 0; $i <= $#SGPR128; $i++) {
215 push (@
{$hw_values{$i * 4}}, $SGPR128[$i]);
218 for (my $i = 0; $i <= $#SGPR256; $i++) {
219 push (@
{$hw_values{$i * 8}}, $SGPR256[$i]);
222 for (my $i = 0; $i <= $#VGPR; $i++) {
223 push (@
{$hw_values{$i}}, $VGPR[$i]);
225 for (my $i = 0; $i <= $#VGPR64; $i++) {
226 push (@
{$hw_values{$i * 2}}, $VGPR64[$i]);
229 for (my $i = 0; $i <= $#VGPR128; $i++) {
230 push (@
{$hw_values{$i * 4}}, $VGPR128[$i]);
234 print $fh "unsigned SIRegisterInfo::getHWRegNum(unsigned reg) const\n{\n switch(reg) {\n";
235 for my $key (keys(%hw_values)) {
236 my @names = @
{$hw_values{$key}};
237 for my $regname (@names) {
238 print $fh " case AMDIL::$regname:\n"
240 print $fh " return $key;\n";
242 print $fh " default: return 0;\n }\n}\n"
248 sub print_sgpr_class
{
249 my ($reg_width, $sub_reg_ref, @types) = @_;
250 return print_reg_class
('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types);
253 sub print_vgpr_class
{
254 my ($reg_width, $sub_reg_ref, @types) = @_;
255 return print_reg_class
('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
258 sub print_reg_class
{
259 my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_;
261 my $component_count = $reg_width / 32;
263 for (my $i = 0; $i < $reg_count; $i += $component_count) {
264 my $reg_name = $reg_prefix . $i . '_' . $reg_width;
266 for (my $idx = 0; $idx < $component_count; $idx++) {
267 my $sub_idx = $i + $idx;
268 push(@sub_regs, $reg_prefix . $sub_idx);
270 print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n";
271 push (@registers, $reg_name);
273 my $reg_list = join(', ', @registers);
275 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDIL\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";
276 print " let SubRegClasses = [($class_prefix\_", ($reg_width / $component_count) , ' ', join(', ', @
{$sub_reg_ref}), ")];\n}\n";