src/gallium/drivers/radeon/SIGenRegisterInfo.pl

   1 #===-- SIGenRegisterInfo.pl - Script for generating register info files ----===#
   2 #
   3 #                     The LLVM Compiler Infrastructure
   4 #
   5 # This file is distributed under the University of Illinois Open Source
   6 # License. See LICENSE.TXT for details.
   7 #
   8 #===------------------------------------------------------------------------===#
   9 #
  10 # This perl script prints to stdout .td code to be used as SIRegisterInfo.td
  11 # it also generates a file called SIHwRegInfo.include, which contains helper
  12 # functions for determining the hw encoding of registers.
  13 #
  14 #===------------------------------------------------------------------------===#
  15
  16 use strict;
  17 use warnings;
  18
  19 my $SGPR_COUNT = 104;
  20 my $VGPR_COUNT = 256;
  21
  22 my $SGPR_MAX_IDX = $SGPR_COUNT - 1;
  23 my $VGPR_MAX_IDX = $VGPR_COUNT - 1;
  24
  25 my $INDEX_FILE = defined($ARGV[0]) ? $ARGV[0] : '';
  26
  27 print <<STRING;
  28
  29 let Namespace = "AMDGPU" in {
  30   def low : SubRegIndex;
  31   def high : SubRegIndex;
  32
  33   def sub0 : SubRegIndex;
  34   def sub1 : SubRegIndex;
  35   def sub2 : SubRegIndex;
  36   def sub3 : SubRegIndex;
  37   def sub4 : SubRegIndex;
  38   def sub5 : SubRegIndex;
  39   def sub6 : SubRegIndex;
  40   def sub7 : SubRegIndex;
  41 }
  42
  43 class SIReg <string n> : Register<n> {
  44   let Namespace = "AMDGPU";
  45 }
  46
  47 class SI_64 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
  48   let Namespace = "AMDGPU";
  49   let SubRegIndices = [low, high];
  50 }
  51
  52 class SI_128 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
  53   let Namespace = "AMDGPU";
  54   let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
  55 }
  56
  57 class SI_256 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
  58   let Namespace = "AMDGPU";
  59   let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
  60 }
  61
  62 class SGPR_32 <bits<8> num, string name> : SIReg<name> {
  63   field bits<8> Num;
  64
  65   let Num = num;
  66 }
  67
  68
  69 class VGPR_32 <bits<9> num, string name> : SIReg<name> {
  70   field bits<9> Num;
  71
  72   let Num = num;
  73 }
  74
  75 class SGPR_64 <bits<8> num, string name, list<Register> subregs> :
  76     SI_64 <name, subregs>;
  77
  78 class VGPR_64 <bits<9> num, string name, list<Register> subregs> :
  79     SI_64 <name, subregs>;
  80
  81 class SGPR_128 <bits<8> num, string name, list<Register> subregs> :
  82     SI_128 <name, subregs>;
  83
  84 class VGPR_128 <bits<9> num, string name, list<Register> subregs> :
  85     SI_128 <name, subregs>;
  86
  87 class SGPR_256 <bits<8> num, string name, list<Register> subregs> :
  88     SI_256 <name, subregs>;
  89
  90 def VCC : SIReg<"VCC">;
  91 def SCC : SIReg<"SCC">;
  92 def SREG_LIT_0 : SIReg <"S LIT 0">;
  93
  94 def M0 : SIReg <"M0">;
  95
  96 //Interpolation registers
  97
  98 def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">;
  99 def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">;
 100 def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">;
 101 def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">;
 102 def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">;
 103 def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">;
 104 def PERSP_I_W : SIReg <"PERSP_I_W">;
 105 def PERSP_J_W : SIReg <"PERSP_J_W">;
 106 def PERSP_1_W : SIReg <"PERSP_1_W">;
 107 def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">;
 108 def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">;
 109 def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">;
 110 def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">;
 111 def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">;
 112 def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">;
 113 def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">;
 114 def POS_X_FLOAT : SIReg <"POS_X_FLOAT">;
 115 def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">;
 116 def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">;
 117 def POS_W_FLOAT : SIReg <"POS_W_FLOAT">;
 118 def FRONT_FACE : SIReg <"FRONT_FACE">;
 119 def ANCILLARY : SIReg <"ANCILLARY">;
 120 def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">;
 121 def POS_FIXED_PT : SIReg <"POS_FIXED_PT">;
 122
 123 STRING
 124
 125 #32 bit register
 126
 127 my @SGPR;
 128 for (my $i = 0; $i < $SGPR_COUNT; $i++) {
 129   print "def SGPR$i : SGPR_32 <$i, \"SGPR$i\">;\n";
 130   $SGPR[$i] = "SGPR$i";
 131 }
 132
 133 my @VGPR;
 134 for (my $i = 0; $i < $VGPR_COUNT; $i++) {
 135   print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\">;\n";
 136   $VGPR[$i] = "VGPR$i";
 137 }
 138
 139 print <<STRING;
 140
 141 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 142     (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX),  SREG_LIT_0, M0)
 143 >;
 144
 145 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 146     (add (sequence "VGPR%u", 0, $VGPR_MAX_IDX),
 147     PERSP_SAMPLE_I, PERSP_SAMPLE_J,
 148     PERSP_CENTER_I, PERSP_CENTER_J,
 149     PERSP_CENTROID_I, PERSP_CENTROID_J,
 150     PERSP_I_W, PERSP_J_W, PERSP_1_W,
 151     LINEAR_SAMPLE_I, LINEAR_SAMPLE_J,
 152     LINEAR_CENTER_I, LINEAR_CENTER_J,
 153     LINEAR_CENTROID_I, LINEAR_CENTROID_J,
 154     LINE_STIPPLE_TEX_COORD,
 155     POS_X_FLOAT,
 156     POS_Y_FLOAT,
 157     POS_Z_FLOAT,
 158     POS_W_FLOAT,
 159     FRONT_FACE,
 160     ANCILLARY,
 161     SAMPLE_COVERAGE,
 162     POS_FIXED_PT
 163     )
 164 >;
 165
 166 def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 167     (add VReg_32, SReg_32)
 168 >;
 169
 170 def CCReg : RegisterClass<"AMDGPU", [f32], 32, (add VCC, SCC)>;
 171
 172 STRING
 173
 174 my @subregs_64 = ('low', 'high');
 175 my @subregs_128 = ('sel_x', 'sel_y', 'sel_z', 'sel_w');
 176 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
 177
 178 my @SGPR64 = print_sgpr_class(64, \@subregs_64, ('i64'));
 179 my @SGPR128 = print_sgpr_class(128, \@subregs_128, ('v4f32', 'v4i32'));
 180 my @SGPR256 = print_sgpr_class(256, \@subregs_256, ('v8i32'));
 181
 182 my @VGPR64 = print_vgpr_class(64, \@subregs_64, ('i64'));
 183 my @VGPR128 = print_vgpr_class(128, \@subregs_128, ('v4f32'));
 184
 185
 186 my $sgpr64_list = join(',', @SGPR64);
 187 my $vgpr64_list = join(',', @VGPR64);
 188 print <<STRING;
 189
 190 def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64,
 191     (add $sgpr64_list, $vgpr64_list)
 192 >;
 193
 194 STRING
 195
 196 if ($INDEX_FILE ne '') {
 197   open(my $fh, ">", $INDEX_FILE);
 198   my %hw_values;
 199
 200   for (my $i = 0; $i <= $#SGPR; $i++) {
 201     push (@{$hw_values{$i}}, $SGPR[$i]);
 202   }
 203
 204   for (my $i = 0; $i <= $#SGPR64; $i++) {
 205     push (@{$hw_values{$i * 2}}, $SGPR64[$i])
 206   }
 207
 208   for (my $i = 0; $i <= $#SGPR128; $i++) {
 209     push (@{$hw_values{$i * 4}}, $SGPR128[$i]);
 210   }
 211
 212   for (my $i = 0; $i <= $#SGPR256; $i++) {
 213     push (@{$hw_values{$i * 8}}, $SGPR256[$i]);
 214   }
 215
 216   for (my $i = 0; $i <= $#VGPR; $i++) {
 217     push (@{$hw_values{$i}}, $VGPR[$i]);
 218   }
 219   for (my $i = 0; $i <= $#VGPR64; $i++) {
 220     push (@{$hw_values{$i * 2}}, $VGPR64[$i]);
 221   }
 222
 223   for (my $i = 0; $i <= $#VGPR128; $i++) {
 224     push (@{$hw_values{$i * 4}}, $VGPR128[$i]);
 225   }
 226
 227
 228   print $fh "unsigned SIRegisterInfo::getHWRegNum(unsigned reg) const\n{\n  switch(reg) {\n";
 229   for my $key (keys(%hw_values)) {
 230     my @names = @{$hw_values{$key}};
 231     for my $regname (@names) {
 232       print $fh "  case AMDGPU::$regname:\n"
 233     }
 234     print $fh "    return $key;\n";
 235   }
 236   print $fh "  default: return 0;\n  }\n}\n"
 237 }
 238
 239
 240
 241
 242 sub print_sgpr_class {
 243   my ($reg_width, $sub_reg_ref, @types) = @_;
 244   return print_reg_class('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types);
 245 }
 246
 247 sub print_vgpr_class {
 248   my ($reg_width, $sub_reg_ref, @types) = @_;
 249   return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
 250 }
 251
 252 sub print_reg_class {
 253   my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_;
 254   my @registers;
 255   my $component_count = $reg_width / 32;
 256
 257   for (my $i = 0; $i < $reg_count; $i += $component_count) {
 258     my $reg_name = $reg_prefix . $i . '_' . $reg_width;
 259     my @sub_regs;
 260     for (my $idx = 0; $idx < $component_count; $idx++) {
 261       my $sub_idx = $i + $idx;
 262       push(@sub_regs, $reg_prefix . $sub_idx);
 263     }
 264     print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n";
 265     push (@registers, $reg_name);
 266   }
 267   my $reg_list = join(', ', @registers);
 268
 269   print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n  (add $reg_list)\n>{\n";
 270   print "  let SubRegClasses = [($class_prefix\_", ($reg_width / $component_count) , ' ', join(', ', @{$sub_reg_ref}), ")];\n}\n";
 271   return @registers;
 272 }