src/gallium/drivers/radeon/SIISelLowering.cpp

   1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp.  This file is
  11 // mostly EmitInstrWithCustomInserter().
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "SIISelLowering.h"
  16 #include "SIInstrInfo.h"
  17 #include "SIRegisterInfo.h"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19
  20 using namespace llvm;
  21
  22 SITargetLowering::SITargetLowering(TargetMachine &TM) :
  23     AMDGPUTargetLowering(TM),
  24     TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo()))
  25 {
  26   addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
  27   addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
  28   addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
  29   addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass);
  30   addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass);
  31   addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass);
  32
  33   addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
  34   addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
  35
  36   computeRegisterProperties();
  37
  38   setOperationAction(ISD::ADD, MVT::i64, Legal);
  39   setOperationAction(ISD::ADD, MVT::i32, Legal);
  40
  41   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
  42
  43   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
  44   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
  45
  46   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
  47 }
  48
  49 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
  50     MachineInstr * MI, MachineBasicBlock * BB) const
  51 {
  52   const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
  53   MachineRegisterInfo & MRI = BB->getParent()->getRegInfo();
  54   MachineBasicBlock::iterator I = MI;
  55
  56   if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) {
  57     AppendS_WAITCNT(MI, *BB, llvm::next(I));
  58     return BB;
  59   }
  60
  61   switch (MI->getOpcode()) {
  62   default:
  63     return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
  64
  65   case AMDGPU::CLAMP_SI:
  66     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
  67            .addOperand(MI->getOperand(0))
  68            .addOperand(MI->getOperand(1))
  69            // VSRC1-2 are unused, but we still need to fill all the
  70            // operand slots, so we just reuse the VSRC0 operand
  71            .addOperand(MI->getOperand(1))
  72            .addOperand(MI->getOperand(1))
  73            .addImm(0) // ABS
  74            .addImm(1) // CLAMP
  75            .addImm(0) // OMOD
  76            .addImm(0); // NEG
  77     MI->eraseFromParent();
  78     break;
  79
  80   case AMDGPU::FABS_SI:
  81     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
  82                  .addOperand(MI->getOperand(0))
  83                  .addOperand(MI->getOperand(1))
  84                  // VSRC1-2 are unused, but we still need to fill all the
  85                  // operand slots, so we just reuse the VSRC0 operand
  86                  .addOperand(MI->getOperand(1))
  87                  .addOperand(MI->getOperand(1))
  88                  .addImm(1) // ABS
  89                  .addImm(0) // CLAMP
  90                  .addImm(0) // OMOD
  91                  .addImm(0); // NEG
  92     MI->eraseFromParent();
  93     break;
  94
  95   case AMDGPU::SI_INTERP:
  96     LowerSI_INTERP(MI, *BB, I, MRI);
  97     break;
  98   case AMDGPU::SI_INTERP_CONST:
  99     LowerSI_INTERP_CONST(MI, *BB, I);
 100     break;
 101   case AMDGPU::SI_V_CNDLT:
 102     LowerSI_V_CNDLT(MI, *BB, I, MRI);
 103     break;
 104   case AMDGPU::USE_SGPR_32:
 105   case AMDGPU::USE_SGPR_64:
 106     lowerUSE_SGPR(MI, BB->getParent(), MRI);
 107     MI->eraseFromParent();
 108     break;
 109   case AMDGPU::VS_LOAD_BUFFER_INDEX:
 110     addLiveIn(MI, BB->getParent(), MRI, TII, AMDGPU::VGPR0);
 111     MI->eraseFromParent();
 112     break;
 113   }
 114   return BB;
 115 }
 116
 117 void SITargetLowering::AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB,
 118     MachineBasicBlock::iterator I) const
 119 {
 120   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT))
 121           .addImm(0);
 122 }
 123
 124 void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
 125     MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
 126 {
 127   unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
 128   MachineOperand dst = MI->getOperand(0);
 129   MachineOperand iReg = MI->getOperand(1);
 130   MachineOperand jReg = MI->getOperand(2);
 131   MachineOperand attr_chan = MI->getOperand(3);
 132   MachineOperand attr = MI->getOperand(4);
 133   MachineOperand params = MI->getOperand(5);
 134
 135   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32))
 136           .addReg(AMDGPU::M0)
 137           .addOperand(params);
 138
 139   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
 140           .addOperand(iReg)
 141           .addOperand(attr_chan)
 142           .addOperand(attr);
 143
 144   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32))
 145           .addOperand(dst)
 146           .addReg(tmp)
 147           .addOperand(jReg)
 148           .addOperand(attr_chan)
 149           .addOperand(attr);
 150
 151   MI->eraseFromParent();
 152 }
 153
 154 void SITargetLowering::LowerSI_INTERP_CONST(MachineInstr *MI,
 155     MachineBasicBlock &BB, MachineBasicBlock::iterator I) const
 156 {
 157   MachineOperand dst = MI->getOperand(0);
 158   MachineOperand attr_chan = MI->getOperand(1);
 159   MachineOperand attr = MI->getOperand(2);
 160   MachineOperand params = MI->getOperand(3);
 161
 162   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32))
 163           .addReg(AMDGPU::M0)
 164           .addOperand(params);
 165
 166   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32))
 167           .addOperand(dst)
 168           .addOperand(attr_chan)
 169           .addOperand(attr);
 170
 171   MI->eraseFromParent();
 172 }
 173
 174 void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
 175     MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
 176 {
 177   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32))
 178           .addOperand(MI->getOperand(1))
 179           .addReg(AMDGPU::SREG_LIT_0);
 180
 181   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32))
 182           .addOperand(MI->getOperand(0))
 183           .addOperand(MI->getOperand(2))
 184           .addOperand(MI->getOperand(3));
 185
 186   MI->eraseFromParent();
 187 }
 188
 189 void SITargetLowering::lowerUSE_SGPR(MachineInstr *MI,
 190     MachineFunction * MF, MachineRegisterInfo & MRI) const
 191 {
 192   const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
 193   unsigned dstReg = MI->getOperand(0).getReg();
 194   int64_t newIndex = MI->getOperand(1).getImm();
 195   const TargetRegisterClass * dstClass = MRI.getRegClass(dstReg);
 196   unsigned DwordWidth = dstClass->getSize() / 4;
 197   assert(newIndex % DwordWidth == 0 && "USER_SGPR not properly aligned");
 198   newIndex = newIndex / DwordWidth;
 199
 200   unsigned newReg = dstClass->getRegister(newIndex);
 201   addLiveIn(MI, MF, MRI, TII, newReg);
 202 }
 203
 204 EVT SITargetLowering::getSetCCResultType(EVT VT) const
 205 {
 206   return MVT::i1;
 207 }
 208
 209 //===----------------------------------------------------------------------===//
 210 // Custom DAG Lowering Operations
 211 //===----------------------------------------------------------------------===//
 212
 213 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
 214 {
 215   switch (Op.getOpcode()) {
 216   default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
 217   case ISD::BR_CC: return LowerBR_CC(Op, DAG);
 218   case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
 219   }
 220 }
 221
 222 SDValue SITargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
 223 {
 224   SDValue Chain = Op.getOperand(0);
 225   SDValue CC = Op.getOperand(1);
 226   SDValue LHS   = Op.getOperand(2);
 227   SDValue RHS   = Op.getOperand(3);
 228   SDValue JumpT  = Op.getOperand(4);
 229   SDValue CmpValue;
 230   SDValue Result;
 231   CmpValue = DAG.getNode(
 232       ISD::SETCC,
 233       Op.getDebugLoc(),
 234       MVT::i1,
 235       LHS, RHS,
 236       CC);
 237
 238   Result = DAG.getNode(
 239       AMDILISD::BRANCH_COND,
 240       CmpValue.getDebugLoc(),
 241       MVT::Other, Chain,
 242       JumpT, CmpValue);
 243   return Result;
 244 }
 245
 246 SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
 247 {
 248   SDValue LHS = Op.getOperand(0);
 249   SDValue RHS = Op.getOperand(1);
 250   SDValue True = Op.getOperand(2);
 251   SDValue False = Op.getOperand(3);
 252   SDValue CC = Op.getOperand(4);
 253   EVT VT = Op.getValueType();
 254   DebugLoc DL = Op.getDebugLoc();
 255
 256   SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
 257   return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
 258 }