src/gallium/drivers/radeon/SIInstrFormats.td

   1 //===-- SIInstrFormats.td - SI Instruction Formats ------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // SI Instruction format definitions.
  11 //
  12 // Instructions with _32 take 32-bit operands.
  13 // Instructions with _64 take 64-bit operands.
  14 //
  15 // VOP_* instructions can use either a 32-bit or 64-bit encoding.  The 32-bit
  16 // encoding is the standard encoding, but instruction that make use of
  17 // any of the instruction modifiers must use the 64-bit encoding.
  18 //
  19 // Instructions with _e32 use the 32-bit encoding.
  20 // Instructions with _e64 use the 64-bit encoding.
  21 //
  22 //===----------------------------------------------------------------------===//
  23
  24
  25 class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
  26   : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
  27
  28 class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
  29   : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
  30
  31
  32 class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
  33   : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
  34
  35 class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
  36   : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
  37
  38 class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
  39   : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
  40
  41 class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
  42   : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
  43
  44 class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
  45                    string opName, list<dag> pattern> :
  46   VOP1 <
  47     op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
  48   >;
  49
  50 multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
  51   def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
  52   def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
  53                       opName, []
  54   >;
  55 }
  56
  57 multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
  58
  59   def _e32 : VOP1_Helper <op, VReg_64, AllReg_64, opName, pattern>;
  60
  61   def _e64 : VOP3_64 <
  62     {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
  63     opName, []
  64   >;
  65 }
  66
  67 class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
  68                    string opName, list<dag> pattern> :
  69   VOP2 <
  70     op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
  71   >;
  72
  73 multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
  74
  75   def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
  76
  77   def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
  78                       opName, []
  79   >;
  80 }
  81
  82 multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
  83   def _e32: VOP2_Helper <op, VReg_64, AllReg_64, opName, pattern>;
  84
  85   def _e64 : VOP3_64 <
  86     {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
  87     opName, []
  88   >;
  89 }
  90
  91 class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
  92   : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
  93
  94 class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
  95   : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
  96
  97 class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
  98                  string opName, list<dag> pattern> :
  99   VOPC <
 100     op, (outs), (ins arc:$src0, vrc:$src1), opName, pattern
 101   >;
 102
 103 multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern> {
 104
 105   def _e32 : VOPC_Helper <op, VReg_32, AllReg_32, opName, pattern>;
 106
 107   def _e64 : VOP3_32 <
 108     {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
 109     opName, []
 110   >;
 111 }
 112
 113 multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> {
 114
 115   def _e32 : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>;
 116
 117   def _e64 : VOP3_64 <
 118     {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
 119     opName, []
 120   >;
 121 }
 122
 123 class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
 124   : SOPC <op, (outs CCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
 125
 126 class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
 127   : SOPC <op, (outs CCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
 128