src/gallium/drivers/radeon/SIInstrInfo.cpp

   1 //===-- SIInstrInfo.cpp - SI Instruction Information  ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // SI Implementation of TargetInstrInfo.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 #include "SIInstrInfo.h"
  16 #include "AMDGPUTargetMachine.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19 #include "llvm/MC/MCInstrDesc.h"
  20
  21 #include <stdio.h>
  22
  23 using namespace llvm;
  24
  25 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
  26   : AMDGPUInstrInfo(tm),
  27     RI(tm, *this),
  28     TM(tm)
  29     { }
  30
  31 const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const
  32 {
  33   return RI;
  34 }
  35
  36 void
  37 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  38                            MachineBasicBlock::iterator MI, DebugLoc DL,
  39                            unsigned DestReg, unsigned SrcReg,
  40                            bool KillSrc) const
  41 {
  42
  43   // If we are trying to copy to or from SCC, there is a bug somewhere else in
  44   // the backend.  While it may be theoretically possible to do this, it should
  45   // never be necessary.
  46   assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
  47
  48   BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
  49    .addReg(SrcReg, getKillRegState(KillSrc));
  50 }
  51
  52 unsigned SIInstrInfo::getEncodingType(const MachineInstr &MI) const
  53 {
  54   return get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
  55 }
  56
  57 unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
  58 {
  59
  60   /* Instructions with literal constants are expanded to 64-bits, and
  61    * the constant is stored in bits [63:32] */
  62   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
  63     if (MI.getOperand(i).getType() == MachineOperand::MO_FPImmediate) {
  64       return 8;
  65     }
  66   }
  67
  68   /* This instruction always has a literal */
  69   if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) {
  70     return 8;
  71   }
  72
  73   unsigned encoding_type = getEncodingType(MI);
  74   switch (encoding_type) {
  75     case SIInstrEncodingType::EXP:
  76     case SIInstrEncodingType::LDS:
  77     case SIInstrEncodingType::MUBUF:
  78     case SIInstrEncodingType::MTBUF:
  79     case SIInstrEncodingType::MIMG:
  80     case SIInstrEncodingType::VOP3:
  81       return 8;
  82     default:
  83       return 4;
  84   }
  85 }
  86
  87 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
  88                                            int64_t Imm) const
  89 {
  90   MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
  91   MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
  92   MachineInstrBuilder(MI).addImm(Imm);
  93
  94   return MI;
  95
  96 }
  97
  98 bool SIInstrInfo::isMov(unsigned Opcode) const
  99 {
 100   switch(Opcode) {
 101   default: return false;
 102   case AMDGPU::S_MOV_B32:
 103   case AMDGPU::S_MOV_B64:
 104   case AMDGPU::V_MOV_B32_e32:
 105   case AMDGPU::V_MOV_B32_e64:
 106   case AMDGPU::V_MOV_IMM_F32:
 107   case AMDGPU::V_MOV_IMM_I32:
 108   case AMDGPU::S_MOV_IMM_I32:
 109     return true;
 110   }
 111 }