src/gallium/drivers/radeon/SIInstrInfo.cpp

   1 //===-- SIInstrInfo.cpp - SI Instruction Information  ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // SI Implementation of TargetInstrInfo.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 #include "SIInstrInfo.h"
  16 #include "AMDGPUTargetMachine.h"
  17 #include "llvm/CodeGen/MachineRegisterInfo.h"
  18 #include "llvm/MC/MCInstrDesc.h"
  19
  20 #include <stdio.h>
  21
  22 using namespace llvm;
  23
  24 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
  25   : AMDGPUInstrInfo(tm),
  26     RI(tm, *this),
  27     TM(tm)
  28     { }
  29
  30 const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const
  31 {
  32   return RI;
  33 }
  34
  35 void
  36 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  37                            MachineBasicBlock::iterator MI, DebugLoc DL,
  38                            unsigned DestReg, unsigned SrcReg,
  39                            bool KillSrc) const
  40 {
  41   BuildMI(MBB, MI, DL, get(AMDIL::V_MOV_B32_e32), DestReg)
  42    .addReg(SrcReg, getKillRegState(KillSrc));
  43 }
  44
  45 unsigned SIInstrInfo::getEncodingType(const MachineInstr &MI) const
  46 {
  47   return get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
  48 }
  49
  50 unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
  51 {
  52
  53   /* Instructions with literal constants are expanded to 64-bits, and
  54    * the constant is stored in bits [63:32] */
  55   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
  56     if (MI.getOperand(i).getType() == MachineOperand::MO_FPImmediate) {
  57       return 8;
  58     }
  59   }
  60
  61   /* This instruction always has a literal */
  62   if (MI.getOpcode() == AMDIL::S_MOV_IMM_I32) {
  63     return 8;
  64   }
  65
  66   unsigned encoding_type = getEncodingType(MI);
  67   switch (encoding_type) {
  68     case SIInstrEncodingType::EXP:
  69     case SIInstrEncodingType::LDS:
  70     case SIInstrEncodingType::MUBUF:
  71     case SIInstrEncodingType::MTBUF:
  72     case SIInstrEncodingType::MIMG:
  73     case SIInstrEncodingType::VOP3:
  74       return 8;
  75     default:
  76       return 4;
  77   }
  78 }
  79
  80 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
  81                                            int64_t Imm) const
  82 {
  83   MachineInstr * MI = MF->CreateMachineInstr(get(AMDIL::V_MOV_IMM_I32), DebugLoc());
  84   MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
  85   MachineInstrBuilder(MI).addImm(Imm);
  86
  87   return MI;
  88
  89 }
  90
  91 bool SIInstrInfo::isMov(unsigned Opcode) const
  92 {
  93   switch(Opcode) {
  94   default: return false;
  95   case AMDIL::S_MOV_B32:
  96   case AMDIL::S_MOV_B64:
  97   case AMDIL::V_MOV_B32_e32:
  98   case AMDIL::V_MOV_B32_e64:
  99   case AMDIL::V_MOV_IMM_F32:
 100   case AMDIL::V_MOV_IMM_I32:
 101   case AMDIL::S_MOV_IMM_I32:
 102     return true;
 103   }
 104 }