src/gallium/drivers/radeon/SIInstrInfo.td

   1 //===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10
  11
  12 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
  13     AMDGPUInst<outs, ins, asm, pattern> {
  14
  15   field bits<4> EncodingType = 0;
  16   field bits<1> NeedWait = 0;
  17
  18   let TSFlags{3-0} = EncodingType;
  19   let TSFlags{4} = NeedWait;
  20
  21 }
  22
  23 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
  24     InstSI <outs, ins, asm, pattern> {
  25
  26   field bits<32> Inst;
  27 }
  28
  29 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
  30     InstSI <outs, ins, asm, pattern> {
  31
  32   field bits<64> Inst;
  33 }
  34
  35 class GPR4Align <RegisterClass rc> : Operand <vAny> {
  36   let EncoderMethod = "GPR4AlignEncode";
  37   let MIOperandInfo = (ops rc:$reg);
  38 }
  39
  40 class GPR2Align <RegisterClass rc, ValueType vt> : Operand <vt> {
  41   let EncoderMethod = "GPR2AlignEncode";
  42   let MIOperandInfo = (ops rc:$reg);
  43 }
  44
  45 def i32Literal : Operand <i32> {
  46   let EncoderMethod = "i32LiteralEncode";
  47 }
  48
  49 def EXP : Enc64<
  50   (outs),
  51   (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
  52        VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
  53   "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
  54   [] > {
  55
  56   bits<4> EN;
  57   bits<6> TGT;
  58   bits<1> COMPR;
  59   bits<1> DONE;
  60   bits<1> VM;
  61   bits<8> VSRC0;
  62   bits<8> VSRC1;
  63   bits<8> VSRC2;
  64   bits<8> VSRC3;
  65
  66   let Inst{3-0} = EN;
  67   let Inst{9-4} = TGT;
  68   let Inst{10} = COMPR;
  69   let Inst{11} = DONE;
  70   let Inst{12} = VM;
  71   let Inst{31-26} = 0x3e;
  72   let Inst{39-32} = VSRC0;
  73   let Inst{47-40} = VSRC1;
  74   let Inst{55-48} = VSRC2;
  75   let Inst{63-56} = VSRC3;
  76   let EncodingType = 0; //SIInstrEncodingType::EXP
  77
  78   let NeedWait = 1;
  79   let usesCustomInserter = 1;
  80 }
  81
  82 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
  83     Enc64 <outs, ins, asm, pattern> {
  84
  85   bits<8> VDATA;
  86   bits<4> DMASK;
  87   bits<1> UNORM;
  88   bits<1> GLC;
  89   bits<1> DA;
  90   bits<1> R128;
  91   bits<1> TFE;
  92   bits<1> LWE;
  93   bits<1> SLC;
  94   bits<8> VADDR;
  95   bits<5> SRSRC;
  96   bits<5> SSAMP;
  97
  98   let Inst{11-8} = DMASK;
  99   let Inst{12} = UNORM;
 100   let Inst{13} = GLC;
 101   let Inst{14} = DA;
 102   let Inst{15} = R128;
 103   let Inst{16} = TFE;
 104   let Inst{17} = LWE;
 105   let Inst{24-18} = op;
 106   let Inst{25} = SLC;
 107   let Inst{31-26} = 0x3c;
 108   let Inst{39-32} = VADDR;
 109   let Inst{47-40} = VDATA;
 110   let Inst{52-48} = SRSRC;
 111   let Inst{57-53} = SSAMP;
 112
 113   let EncodingType = 2; //SIInstrEncodingType::MIMG
 114
 115   let NeedWait = 1;
 116   let usesCustomInserter = 1;
 117 }
 118
 119 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
 120     Enc64<outs, ins, asm, pattern> {
 121
 122   bits<8> VDATA;
 123   bits<12> OFFSET;
 124   bits<1> OFFEN;
 125   bits<1> IDXEN;
 126   bits<1> GLC;
 127   bits<1> ADDR64;
 128   bits<4> DFMT;
 129   bits<3> NFMT;
 130   bits<8> VADDR;
 131   bits<5> SRSRC;
 132   bits<1> SLC;
 133   bits<1> TFE;
 134   bits<8> SOFFSET;
 135
 136   let Inst{11-0} = OFFSET;
 137   let Inst{12} = OFFEN;
 138   let Inst{13} = IDXEN;
 139   let Inst{14} = GLC;
 140   let Inst{15} = ADDR64;
 141   let Inst{18-16} = op;
 142   let Inst{22-19} = DFMT;
 143   let Inst{25-23} = NFMT;
 144   let Inst{31-26} = 0x3a; //encoding
 145   let Inst{39-32} = VADDR;
 146   let Inst{47-40} = VDATA;
 147   let Inst{52-48} = SRSRC;
 148   let Inst{54} = SLC;
 149   let Inst{55} = TFE;
 150   let Inst{63-56} = SOFFSET;
 151   let EncodingType = 3; //SIInstrEncodingType::MTBUF
 152
 153   let NeedWait = 1;
 154   let usesCustomInserter = 1;
 155   let neverHasSideEffects = 1;
 156 }
 157
 158 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 159     Enc64<outs, ins, asm, pattern> {
 160
 161   bits<8> VDATA;
 162   bits<12> OFFSET;
 163   bits<1> OFFEN;
 164   bits<1> IDXEN;
 165   bits<1> GLC;
 166   bits<1> ADDR64;
 167   bits<1> LDS;
 168   bits<8> VADDR;
 169   bits<5> SRSRC;
 170   bits<1> SLC;
 171   bits<1> TFE;
 172   bits<8> SOFFSET;
 173
 174   let Inst{11-0} = OFFSET;
 175   let Inst{12} = OFFEN;
 176   let Inst{13} = IDXEN;
 177   let Inst{14} = GLC;
 178   let Inst{15} = ADDR64;
 179   let Inst{16} = LDS;
 180   let Inst{24-18} = op;
 181   let Inst{31-26} = 0x38; //encoding
 182   let Inst{39-32} = VADDR;
 183   let Inst{47-40} = VDATA;
 184   let Inst{52-48} = SRSRC;
 185   let Inst{54} = SLC;
 186   let Inst{55} = TFE;
 187   let Inst{63-56} = SOFFSET;
 188   let EncodingType = 4; //SIInstrEncodingType::MUBUF
 189
 190   let NeedWait = 1;
 191   let usesCustomInserter = 1;
 192   let neverHasSideEffects = 1;
 193 }
 194
 195 class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
 196     Enc32<outs, ins, asm, pattern> {
 197
 198   bits<7> SDST;
 199   bits<8> OFFSET;
 200   bits<6> SBASE;
 201   bits<1> IMM = 0; // Determined by subclasses
 202
 203   let Inst{7-0} = OFFSET;
 204   let Inst{8} = IMM;
 205   let Inst{14-9} = SBASE;
 206   let Inst{21-15} = SDST;
 207   let Inst{26-22} = op;
 208   let Inst{31-27} = 0x18; //encoding
 209   let EncodingType = 5; //SIInstrEncodingType::SMRD
 210
 211   let NeedWait = 1;
 212   let usesCustomInserter = 1;
 213 }
 214
 215 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 216     Enc32<outs, ins, asm, pattern> {
 217
 218   bits<7> SDST;
 219   bits<8> SSRC0;
 220
 221   let Inst{7-0} = SSRC0;
 222   let Inst{15-8} = op;
 223   let Inst{22-16} = SDST;
 224   let Inst{31-23} = 0x17d; //encoding;
 225   let EncodingType = 6; //SIInstrEncodingType::SOP1
 226 }
 227
 228 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 229     Enc32 <outs, ins, asm, pattern> {
 230
 231   bits<7> SDST;
 232   bits<8> SSRC0;
 233   bits<8> SSRC1;
 234
 235   let Inst{7-0} = SSRC0;
 236   let Inst{15-8} = SSRC1;
 237   let Inst{22-16} = SDST;
 238   let Inst{29-23} = op;
 239   let Inst{31-30} = 0x2; // encoding
 240   let EncodingType = 7; // SIInstrEncodingType::SOP2
 241 }
 242
 243 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 244   Enc32<outs, ins, asm, pattern> {
 245
 246   bits<8> SSRC0;
 247   bits<8> SSRC1;
 248
 249   let Inst{7-0} = SSRC0;
 250   let Inst{15-8} = SSRC1;
 251   let Inst{22-16} = op;
 252   let Inst{31-23} = 0x17e;
 253   let EncodingType = 8; // SIInstrEncodingType::SOPC
 254 }
 255
 256 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
 257    Enc32 <outs, ins , asm, pattern> {
 258
 259   bits <7> SDST;
 260   bits <16> SIMM16;
 261
 262   let Inst{15-0} = SIMM16;
 263   let Inst{22-16} = SDST;
 264   let Inst{27-23} = op;
 265   let Inst{31-28} = 0xb; //encoding
 266   let EncodingType = 9; // SIInstrEncodingType::SOPK
 267 }
 268
 269 class SOPP <bits<7> op, dag ins, string asm> : Enc32 <
 270   (outs),
 271   ins,
 272   asm,
 273   [] > {
 274
 275   bits <16> SIMM16;
 276
 277   let Inst{15-0} = SIMM16;
 278   let Inst{22-16} = op;
 279   let Inst{31-23} = 0x17f; // encoding
 280   let EncodingType = 10; // SIInstrEncodingType::SOPP
 281 }
 282
 283
 284 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
 285     Enc32 <outs, ins, asm, pattern> {
 286
 287   bits<8> VDST;
 288   bits<8> VSRC;
 289   bits<2> ATTRCHAN;
 290   bits<6> ATTR;
 291
 292   let Inst{7-0} = VSRC;
 293   let Inst{9-8} = ATTRCHAN;
 294   let Inst{15-10} = ATTR;
 295   let Inst{17-16} = op;
 296   let Inst{25-18} = VDST;
 297   let Inst{31-26} = 0x32; // encoding
 298   let EncodingType = 11; // SIInstrEncodingType::VINTRP
 299
 300   let Uses = [M0];
 301 }
 302
 303 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 304     Enc32 <outs, ins, asm, pattern> {
 305
 306   bits<8> VDST;
 307   bits<9> SRC0;
 308
 309   let Inst{8-0} = SRC0;
 310   let Inst{16-9} = op;
 311   let Inst{24-17} = VDST;
 312   let Inst{31-25} = 0x3f; //encoding
 313
 314   let EncodingType = 12; // SIInstrEncodingType::VOP1
 315   let PostEncoderMethod = "VOPPostEncode";
 316 }
 317
 318 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
 319     Enc32 <outs, ins, asm, pattern> {
 320
 321   bits<8> VDST;
 322   bits<9> SRC0;
 323   bits<8> VSRC1;
 324
 325   let Inst{8-0} = SRC0;
 326   let Inst{16-9} = VSRC1;
 327   let Inst{24-17} = VDST;
 328   let Inst{30-25} = op;
 329   let Inst{31} = 0x0; //encoding
 330
 331   let EncodingType = 13; // SIInstrEncodingType::VOP2
 332   let PostEncoderMethod = "VOPPostEncode";
 333 }
 334
 335 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
 336     Enc64 <outs, ins, asm, pattern> {
 337
 338   bits<8> VDST;
 339   bits<9> SRC0;
 340   bits<9> SRC1;
 341   bits<9> SRC2;
 342   bits<3> ABS;
 343   bits<1> CLAMP;
 344   bits<2> OMOD;
 345   bits<3> NEG;
 346
 347   let Inst{7-0} = VDST;
 348   let Inst{10-8} = ABS;
 349   let Inst{11} = CLAMP;
 350   let Inst{25-17} = op;
 351   let Inst{31-26} = 0x34; //encoding
 352   let Inst{40-32} = SRC0;
 353   let Inst{49-41} = SRC1;
 354   let Inst{58-50} = SRC2;
 355   let Inst{60-59} = OMOD;
 356   let Inst{63-61} = NEG;
 357
 358   let EncodingType = 14; // SIInstrEncodingType::VOP3
 359   let PostEncoderMethod = "VOPPostEncode";
 360 }
 361
 362 class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 363     Enc32 <outs, ins, asm, pattern> {
 364
 365   bits<9> SRC0;
 366   bits<8> VSRC1;
 367
 368   let Inst{8-0} = SRC0;
 369   let Inst{16-9} = VSRC1;
 370   let Inst{24-17} = op;
 371   let Inst{31-25} = 0x3e;
 372
 373   let EncodingType = 15; //SIInstrEncodingType::VOPC
 374   let PostEncoderMethod = "VOPPostEncode";
 375
 376   let Defs = [VCC];
 377 }
 378
 379 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
 380   op,
 381   (outs VReg_128:$vdata),
 382   (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
 383        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
 384        GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
 385   asm,
 386   []
 387 >;
 388
 389 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
 390   op,
 391   (outs regClass:$dst),
 392   (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
 393        i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
 394        i1imm:$tfe, SReg_32:$soffset),
 395   asm,
 396   []> {
 397   let mayLoad = 1;
 398 }
 399
 400 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
 401   op,
 402   (outs regClass:$dst),
 403   (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
 404        i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
 405        i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
 406   asm,
 407   []> {
 408   let mayLoad = 1;
 409 }
 410
 411 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
 412   op,
 413   (outs),
 414   (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
 415    i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
 416    GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
 417   asm,
 418   []> {
 419   let mayStore = 1;
 420 }
 421
 422 /*XXX: We should be able to infer the imm bit based on the arg types */
 423 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
 424
 425   def _SGPR : SMRD <
 426               op,
 427               (outs dstClass:$dst),
 428               (ins SReg_32:$offset, GPR2Align<SReg_64,i64>:$sbase),
 429               asm,
 430               []
 431   > {
 432     let IMM = 0;
 433   }
 434
 435   def _IMM : SMRD <
 436               op,
 437               (outs dstClass:$dst),
 438               (ins i32imm:$offset, GPR2Align<SReg_64,i64>:$sbase),
 439               asm,
 440               []
 441   > {
 442     let IMM = 1;
 443   }
 444 }
 445
 446 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
 447   let EncoderMethod = "encodeOperand";
 448   let MIOperandInfo = opInfo;
 449 }
 450
 451 def IMM8bit : ImmLeaf <
 452   i32,
 453   [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
 454 >;
 455
 456 def IMM12bit : ImmLeaf <
 457   i16,
 458   [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
 459 >;
 460
 461 include "SIInstrFormats.td"
 462
 463 include "SIInstructions.td"