src/gallium/drivers/radeon/SIInstrInfo.td

   1 //===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10
  11
  12 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
  13     AMDGPUInst<outs, ins, asm, pattern> {
  14
  15   field bits<4> EncodingType = 0;
  16   field bits<1> NeedWait = 0;
  17
  18   let TSFlags{3-0} = EncodingType;
  19   let TSFlags{4} = NeedWait;
  20
  21 }
  22
  23 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
  24     InstSI <outs, ins, asm, pattern> {
  25
  26   field bits<32> Inst;
  27 }
  28
  29 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
  30     InstSI <outs, ins, asm, pattern> {
  31
  32   field bits<64> Inst;
  33 }
  34
  35 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
  36   let EncoderMethod = "encodeOperand";
  37   let MIOperandInfo = opInfo;
  38 }
  39
  40 def IMM8bit : ImmLeaf <
  41   i32,
  42   [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
  43 >;
  44
  45 def IMM12bit : ImmLeaf <
  46   i16,
  47   [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
  48 >;
  49
  50 class GPR4Align <RegisterClass rc> : Operand <vAny> {
  51   let EncoderMethod = "GPR4AlignEncode";
  52   let MIOperandInfo = (ops rc:$reg);
  53 }
  54
  55 class GPR2Align <RegisterClass rc, ValueType vt> : Operand <vt> {
  56   let EncoderMethod = "GPR2AlignEncode";
  57   let MIOperandInfo = (ops rc:$reg);
  58 }
  59
  60 def i32Literal : Operand <i32> {
  61   let EncoderMethod = "i32LiteralEncode";
  62 }
  63
  64 def SMRDmemrr : Operand<iPTR> {
  65   let MIOperandInfo = (ops SReg_64, SReg_32);
  66   let EncoderMethod = "GPR2AlignEncode";
  67 }
  68
  69 def SMRDmemri : Operand<iPTR> {
  70   let MIOperandInfo = (ops SReg_64, i32imm);
  71   let EncoderMethod = "SMRDmemriEncode";
  72 }
  73
  74 def ADDR_Reg     : ComplexPattern<i64, 2, "SelectADDRReg", [], []>;
  75 def ADDR_Offset8 : ComplexPattern<i64, 2, "SelectADDR8BitOffset", [], []>;
  76
  77 def EXP : Enc64<
  78   (outs),
  79   (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
  80        VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
  81   "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
  82   [] > {
  83
  84   bits<4> EN;
  85   bits<6> TGT;
  86   bits<1> COMPR;
  87   bits<1> DONE;
  88   bits<1> VM;
  89   bits<8> VSRC0;
  90   bits<8> VSRC1;
  91   bits<8> VSRC2;
  92   bits<8> VSRC3;
  93
  94   let Inst{3-0} = EN;
  95   let Inst{9-4} = TGT;
  96   let Inst{10} = COMPR;
  97   let Inst{11} = DONE;
  98   let Inst{12} = VM;
  99   let Inst{31-26} = 0x3e;
 100   let Inst{39-32} = VSRC0;
 101   let Inst{47-40} = VSRC1;
 102   let Inst{55-48} = VSRC2;
 103   let Inst{63-56} = VSRC3;
 104   let EncodingType = 0; //SIInstrEncodingType::EXP
 105
 106   let NeedWait = 1;
 107   let usesCustomInserter = 1;
 108 }
 109
 110 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 111     Enc64 <outs, ins, asm, pattern> {
 112
 113   bits<8> VDATA;
 114   bits<4> DMASK;
 115   bits<1> UNORM;
 116   bits<1> GLC;
 117   bits<1> DA;
 118   bits<1> R128;
 119   bits<1> TFE;
 120   bits<1> LWE;
 121   bits<1> SLC;
 122   bits<8> VADDR;
 123   bits<5> SRSRC;
 124   bits<5> SSAMP;
 125
 126   let Inst{11-8} = DMASK;
 127   let Inst{12} = UNORM;
 128   let Inst{13} = GLC;
 129   let Inst{14} = DA;
 130   let Inst{15} = R128;
 131   let Inst{16} = TFE;
 132   let Inst{17} = LWE;
 133   let Inst{24-18} = op;
 134   let Inst{25} = SLC;
 135   let Inst{31-26} = 0x3c;
 136   let Inst{39-32} = VADDR;
 137   let Inst{47-40} = VDATA;
 138   let Inst{52-48} = SRSRC;
 139   let Inst{57-53} = SSAMP;
 140
 141   let EncodingType = 2; //SIInstrEncodingType::MIMG
 142
 143   let NeedWait = 1;
 144   let usesCustomInserter = 1;
 145 }
 146
 147 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
 148     Enc64<outs, ins, asm, pattern> {
 149
 150   bits<8> VDATA;
 151   bits<12> OFFSET;
 152   bits<1> OFFEN;
 153   bits<1> IDXEN;
 154   bits<1> GLC;
 155   bits<1> ADDR64;
 156   bits<4> DFMT;
 157   bits<3> NFMT;
 158   bits<8> VADDR;
 159   bits<5> SRSRC;
 160   bits<1> SLC;
 161   bits<1> TFE;
 162   bits<8> SOFFSET;
 163
 164   let Inst{11-0} = OFFSET;
 165   let Inst{12} = OFFEN;
 166   let Inst{13} = IDXEN;
 167   let Inst{14} = GLC;
 168   let Inst{15} = ADDR64;
 169   let Inst{18-16} = op;
 170   let Inst{22-19} = DFMT;
 171   let Inst{25-23} = NFMT;
 172   let Inst{31-26} = 0x3a; //encoding
 173   let Inst{39-32} = VADDR;
 174   let Inst{47-40} = VDATA;
 175   let Inst{52-48} = SRSRC;
 176   let Inst{54} = SLC;
 177   let Inst{55} = TFE;
 178   let Inst{63-56} = SOFFSET;
 179   let EncodingType = 3; //SIInstrEncodingType::MTBUF
 180
 181   let NeedWait = 1;
 182   let usesCustomInserter = 1;
 183   let neverHasSideEffects = 1;
 184 }
 185
 186 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 187     Enc64<outs, ins, asm, pattern> {
 188
 189   bits<8> VDATA;
 190   bits<12> OFFSET;
 191   bits<1> OFFEN;
 192   bits<1> IDXEN;
 193   bits<1> GLC;
 194   bits<1> ADDR64;
 195   bits<1> LDS;
 196   bits<8> VADDR;
 197   bits<5> SRSRC;
 198   bits<1> SLC;
 199   bits<1> TFE;
 200   bits<8> SOFFSET;
 201
 202   let Inst{11-0} = OFFSET;
 203   let Inst{12} = OFFEN;
 204   let Inst{13} = IDXEN;
 205   let Inst{14} = GLC;
 206   let Inst{15} = ADDR64;
 207   let Inst{16} = LDS;
 208   let Inst{24-18} = op;
 209   let Inst{31-26} = 0x38; //encoding
 210   let Inst{39-32} = VADDR;
 211   let Inst{47-40} = VDATA;
 212   let Inst{52-48} = SRSRC;
 213   let Inst{54} = SLC;
 214   let Inst{55} = TFE;
 215   let Inst{63-56} = SOFFSET;
 216   let EncodingType = 4; //SIInstrEncodingType::MUBUF
 217
 218   let NeedWait = 1;
 219   let usesCustomInserter = 1;
 220   let neverHasSideEffects = 1;
 221 }
 222
 223 class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
 224     Enc32<outs, ins, asm, pattern> {
 225
 226   bits<7> SDST;
 227   bits<15> PTR;
 228   bits<8> OFFSET = PTR{7-0};
 229   bits<1> IMM    = PTR{8};
 230   bits<6> SBASE  = PTR{14-9};
 231
 232   let Inst{7-0} = OFFSET;
 233   let Inst{8} = IMM;
 234   let Inst{14-9} = SBASE;
 235   let Inst{21-15} = SDST;
 236   let Inst{26-22} = op;
 237   let Inst{31-27} = 0x18; //encoding
 238   let EncodingType = 5; //SIInstrEncodingType::SMRD
 239
 240   let NeedWait = 1;
 241   let usesCustomInserter = 1;
 242 }
 243
 244 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 245     Enc32<outs, ins, asm, pattern> {
 246
 247   bits<7> SDST;
 248   bits<8> SSRC0;
 249
 250   let Inst{7-0} = SSRC0;
 251   let Inst{15-8} = op;
 252   let Inst{22-16} = SDST;
 253   let Inst{31-23} = 0x17d; //encoding;
 254   let EncodingType = 6; //SIInstrEncodingType::SOP1
 255 }
 256
 257 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 258     Enc32 <outs, ins, asm, pattern> {
 259
 260   bits<7> SDST;
 261   bits<8> SSRC0;
 262   bits<8> SSRC1;
 263
 264   let Inst{7-0} = SSRC0;
 265   let Inst{15-8} = SSRC1;
 266   let Inst{22-16} = SDST;
 267   let Inst{29-23} = op;
 268   let Inst{31-30} = 0x2; // encoding
 269   let EncodingType = 7; // SIInstrEncodingType::SOP2
 270 }
 271
 272 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 273   Enc32<outs, ins, asm, pattern> {
 274
 275   bits<8> SSRC0;
 276   bits<8> SSRC1;
 277
 278   let Inst{7-0} = SSRC0;
 279   let Inst{15-8} = SSRC1;
 280   let Inst{22-16} = op;
 281   let Inst{31-23} = 0x17e;
 282   let EncodingType = 8; // SIInstrEncodingType::SOPC
 283 }
 284
 285 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
 286    Enc32 <outs, ins , asm, pattern> {
 287
 288   bits <7> SDST;
 289   bits <16> SIMM16;
 290
 291   let Inst{15-0} = SIMM16;
 292   let Inst{22-16} = SDST;
 293   let Inst{27-23} = op;
 294   let Inst{31-28} = 0xb; //encoding
 295   let EncodingType = 9; // SIInstrEncodingType::SOPK
 296 }
 297
 298 class SOPP <bits<7> op, dag ins, string asm> : Enc32 <
 299   (outs),
 300   ins,
 301   asm,
 302   [] > {
 303
 304   bits <16> SIMM16;
 305
 306   let Inst{15-0} = SIMM16;
 307   let Inst{22-16} = op;
 308   let Inst{31-23} = 0x17f; // encoding
 309   let EncodingType = 10; // SIInstrEncodingType::SOPP
 310 }
 311
 312
 313 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
 314     Enc32 <outs, ins, asm, pattern> {
 315
 316   bits<8> VDST;
 317   bits<8> VSRC;
 318   bits<2> ATTRCHAN;
 319   bits<6> ATTR;
 320
 321   let Inst{7-0} = VSRC;
 322   let Inst{9-8} = ATTRCHAN;
 323   let Inst{15-10} = ATTR;
 324   let Inst{17-16} = op;
 325   let Inst{25-18} = VDST;
 326   let Inst{31-26} = 0x32; // encoding
 327   let EncodingType = 11; // SIInstrEncodingType::VINTRP
 328
 329   let Uses = [M0];
 330 }
 331
 332 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 333     Enc32 <outs, ins, asm, pattern> {
 334
 335   bits<8> VDST;
 336   bits<9> SRC0;
 337
 338   let Inst{8-0} = SRC0;
 339   let Inst{16-9} = op;
 340   let Inst{24-17} = VDST;
 341   let Inst{31-25} = 0x3f; //encoding
 342
 343   let EncodingType = 12; // SIInstrEncodingType::VOP1
 344   let PostEncoderMethod = "VOPPostEncode";
 345 }
 346
 347 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
 348     Enc32 <outs, ins, asm, pattern> {
 349
 350   bits<8> VDST;
 351   bits<9> SRC0;
 352   bits<8> VSRC1;
 353
 354   let Inst{8-0} = SRC0;
 355   let Inst{16-9} = VSRC1;
 356   let Inst{24-17} = VDST;
 357   let Inst{30-25} = op;
 358   let Inst{31} = 0x0; //encoding
 359
 360   let EncodingType = 13; // SIInstrEncodingType::VOP2
 361   let PostEncoderMethod = "VOPPostEncode";
 362 }
 363
 364 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
 365     Enc64 <outs, ins, asm, pattern> {
 366
 367   bits<8> VDST;
 368   bits<9> SRC0;
 369   bits<9> SRC1;
 370   bits<9> SRC2;
 371   bits<3> ABS;
 372   bits<1> CLAMP;
 373   bits<2> OMOD;
 374   bits<3> NEG;
 375
 376   let Inst{7-0} = VDST;
 377   let Inst{10-8} = ABS;
 378   let Inst{11} = CLAMP;
 379   let Inst{25-17} = op;
 380   let Inst{31-26} = 0x34; //encoding
 381   let Inst{40-32} = SRC0;
 382   let Inst{49-41} = SRC1;
 383   let Inst{58-50} = SRC2;
 384   let Inst{60-59} = OMOD;
 385   let Inst{63-61} = NEG;
 386
 387   let EncodingType = 14; // SIInstrEncodingType::VOP3
 388   let PostEncoderMethod = "VOPPostEncode";
 389 }
 390
 391 class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 392     Enc32 <outs, ins, asm, pattern> {
 393
 394   bits<9> SRC0;
 395   bits<8> VSRC1;
 396
 397   let Inst{8-0} = SRC0;
 398   let Inst{16-9} = VSRC1;
 399   let Inst{24-17} = op;
 400   let Inst{31-25} = 0x3e;
 401
 402   let EncodingType = 15; //SIInstrEncodingType::VOPC
 403   let PostEncoderMethod = "VOPPostEncode";
 404
 405   let Defs = [VCC];
 406 }
 407
 408 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
 409   op,
 410   (outs VReg_128:$vdata),
 411   (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
 412        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
 413        GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
 414   asm,
 415   []
 416 >;
 417
 418 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
 419   op,
 420   (outs regClass:$dst),
 421   (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
 422        i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
 423        i1imm:$tfe, SReg_32:$soffset),
 424   asm,
 425   []> {
 426   let mayLoad = 1;
 427 }
 428
 429 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
 430   op,
 431   (outs regClass:$dst),
 432   (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
 433        i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
 434        i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
 435   asm,
 436   []> {
 437   let mayLoad = 1;
 438 }
 439
 440 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
 441   op,
 442   (outs),
 443   (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
 444    i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
 445    GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
 446   asm,
 447   []> {
 448   let mayStore = 1;
 449 }
 450
 451 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
 452                         ValueType vt> {
 453
 454   def _SGPR : SMRD <
 455               op,
 456               (outs dstClass:$dst),
 457               (ins SMRDmemrr:$src0),
 458               asm,
 459               [(set (vt dstClass:$dst), (constant_load ADDR_Reg:$src0))]
 460   >;
 461
 462   def _IMM : SMRD <
 463               op,
 464               (outs dstClass:$dst),
 465               (ins SMRDmemri:$src0),
 466               asm,
 467               [(set (vt dstClass:$dst), (constant_load ADDR_Offset8:$src0))]
 468   >;
 469 }
 470
 471 multiclass SMRD_32 <bits<5> op, string asm, RegisterClass dstClass> {
 472   defm _F32 : SMRD_Helper <op, asm, dstClass, f32>;
 473   defm _I32 : SMRD_Helper <op, asm, dstClass, i32>;
 474 }
 475
 476 include "SIInstrFormats.td"
 477 include "SIInstructions.td"