src/gallium/drivers/radeon/SIInstrInfo.td

   1 //===-- SIInstrInfo.td - TODO: Add brief description -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // TODO: Add full description
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15
  16 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
  17     AMDGPUInst<outs, ins, asm, pattern> {
  18
  19   field bits<4> EncodingType = 0;
  20   field bits<1> NeedWait = 0;
  21
  22   let TSFlags{3-0} = EncodingType;
  23   let TSFlags{4} = NeedWait;
  24
  25 }
  26
  27 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
  28     InstSI <outs, ins, asm, pattern> {
  29
  30   field bits<32> Inst;
  31 }
  32
  33 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
  34     InstSI <outs, ins, asm, pattern> {
  35
  36   field bits<64> Inst;
  37 }
  38
  39 class GPR4Align <RegisterClass rc> : Operand <vAny> {
  40   let EncoderMethod = "GPR4AlignEncode";
  41   let MIOperandInfo = (ops rc:$reg);
  42 }
  43
  44 class GPR2Align <RegisterClass rc, ValueType vt> : Operand <vt> {
  45   let EncoderMethod = "GPR2AlignEncode";
  46   let MIOperandInfo = (ops rc:$reg);
  47 }
  48
  49 def i32Literal : Operand <i32> {
  50   let EncoderMethod = "i32LiteralEncode";
  51 }
  52
  53 def EXP : Enc64<
  54   (outs),
  55   (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
  56        VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
  57   "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
  58   [] > {
  59
  60   bits<4> EN;
  61   bits<6> TGT;
  62   bits<1> COMPR;
  63   bits<1> DONE;
  64   bits<1> VM;
  65   bits<8> VSRC0;
  66   bits<8> VSRC1;
  67   bits<8> VSRC2;
  68   bits<8> VSRC3;
  69
  70   let Inst{3-0} = EN;
  71   let Inst{9-4} = TGT;
  72   let Inst{10} = COMPR;
  73   let Inst{11} = DONE;
  74   let Inst{12} = VM;
  75   let Inst{31-26} = 0x3e;
  76   let Inst{39-32} = VSRC0;
  77   let Inst{47-40} = VSRC1;
  78   let Inst{55-48} = VSRC2;
  79   let Inst{63-56} = VSRC3;
  80   let EncodingType = 0; //SIInstrEncodingType::EXP
  81
  82   let NeedWait = 1;
  83   let usesCustomInserter = 1;
  84 }
  85
  86 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
  87     Enc64 <outs, ins, asm, pattern> {
  88
  89   bits<8> VDATA;
  90   bits<4> DMASK;
  91   bits<1> UNORM;
  92   bits<1> GLC;
  93   bits<1> DA;
  94   bits<1> R128;
  95   bits<1> TFE;
  96   bits<1> LWE;
  97   bits<1> SLC;
  98   bits<8> VADDR;
  99   bits<5> SRSRC;
 100   bits<5> SSAMP;
 101
 102   let Inst{11-8} = DMASK;
 103   let Inst{12} = UNORM;
 104   let Inst{13} = GLC;
 105   let Inst{14} = DA;
 106   let Inst{15} = R128;
 107   let Inst{16} = TFE;
 108   let Inst{17} = LWE;
 109   let Inst{24-18} = op;
 110   let Inst{25} = SLC;
 111   let Inst{31-26} = 0x3c;
 112   let Inst{39-32} = VADDR;
 113   let Inst{47-40} = VDATA;
 114   let Inst{52-48} = SRSRC;
 115   let Inst{57-53} = SSAMP;
 116
 117   let EncodingType = 2; //SIInstrEncodingType::MIMG
 118
 119 }
 120
 121 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
 122     Enc64<outs, ins, asm, pattern> {
 123
 124   bits<8> VDATA;
 125   bits<12> OFFSET;
 126   bits<1> OFFEN;
 127   bits<1> IDXEN;
 128   bits<1> GLC;
 129   bits<1> ADDR64;
 130   bits<4> DFMT;
 131   bits<3> NFMT;
 132   bits<8> VADDR;
 133   bits<5> SRSRC;
 134   bits<1> SLC;
 135   bits<1> TFE;
 136   bits<8> SOFFSET;
 137
 138   let Inst{11-0} = OFFSET;
 139   let Inst{12} = OFFEN;
 140   let Inst{13} = IDXEN;
 141   let Inst{14} = GLC;
 142   let Inst{15} = ADDR64;
 143   let Inst{18-16} = op;
 144   let Inst{22-19} = DFMT;
 145   let Inst{25-23} = NFMT;
 146   let Inst{31-26} = 0x3a; //encoding
 147   let Inst{39-32} = VADDR;
 148   let Inst{47-40} = VDATA;
 149   let Inst{52-48} = SRSRC;
 150   let Inst{54} = SLC;
 151   let Inst{55} = TFE;
 152   let Inst{63-56} = SOFFSET;
 153   let EncodingType = 3; //SIInstrEncodingType::MTBUF
 154
 155   let NeedWait = 1;
 156   let usesCustomInserter = 1;
 157   let neverHasSideEffects = 1;
 158 }
 159
 160 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 161     Enc64<outs, ins, asm, pattern> {
 162
 163   bits<8> VDATA;
 164   bits<12> OFFSET;
 165   bits<1> OFFEN;
 166   bits<1> IDXEN;
 167   bits<1> GLC;
 168   bits<1> ADDR64;
 169   bits<1> LDS;
 170   bits<8> VADDR;
 171   bits<5> SRSRC;
 172   bits<1> SLC;
 173   bits<1> TFE;
 174   bits<8> SOFFSET;
 175
 176   let Inst{11-0} = OFFSET;
 177   let Inst{12} = OFFEN;
 178   let Inst{13} = IDXEN;
 179   let Inst{14} = GLC;
 180   let Inst{15} = ADDR64;
 181   let Inst{16} = LDS;
 182   let Inst{24-18} = op;
 183   let Inst{31-26} = 0x38; //encoding
 184   let Inst{39-32} = VADDR;
 185   let Inst{47-40} = VDATA;
 186   let Inst{52-48} = SRSRC;
 187   let Inst{54} = SLC;
 188   let Inst{55} = TFE;
 189   let Inst{63-56} = SOFFSET;
 190   let EncodingType = 4; //SIInstrEncodingType::MUBUF
 191
 192   let NeedWait = 1;
 193   let usesCustomInserter = 1;
 194   let neverHasSideEffects = 1;
 195 }
 196
 197 class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
 198     Enc32<outs, ins, asm, pattern> {
 199
 200   bits<7> SDST;
 201   bits<8> OFFSET;
 202   bits<6> SBASE;
 203   bits<1> IMM = 0; // Determined by subclasses
 204
 205   let Inst{7-0} = OFFSET;
 206   let Inst{8} = IMM;
 207   let Inst{14-9} = SBASE;
 208   let Inst{21-15} = SDST;
 209   let Inst{26-22} = op;
 210   let Inst{31-27} = 0x18; //encoding
 211   let EncodingType = 5; //SIInstrEncodingType::SMRD
 212
 213   let NeedWait = 1;
 214   let usesCustomInserter = 1;
 215 }
 216
 217 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 218     Enc32<outs, ins, asm, pattern> {
 219
 220   bits<7> SDST;
 221   bits<8> SSRC0;
 222
 223   let Inst{7-0} = SSRC0;
 224   let Inst{15-8} = op;
 225   let Inst{22-16} = SDST;
 226   let Inst{31-23} = 0x17d; //encoding;
 227   let EncodingType = 6; //SIInstrEncodingType::SOP1
 228 }
 229
 230 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 231     Enc32 <outs, ins, asm, pattern> {
 232
 233   bits<7> SDST;
 234   bits<8> SSRC0;
 235   bits<8> SSRC1;
 236
 237   let Inst{7-0} = SSRC0;
 238   let Inst{15-8} = SSRC1;
 239   let Inst{22-16} = SDST;
 240   let Inst{29-23} = op;
 241   let Inst{31-30} = 0x2; // encoding
 242   let EncodingType = 7; // SIInstrEncodingType::SOP2
 243 }
 244
 245 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
 246   Enc32<outs, ins, asm, pattern> {
 247
 248   bits<8> SSRC0;
 249   bits<8> SSRC1;
 250
 251   let Inst{7-0} = SSRC0;
 252   let Inst{15-8} = SSRC1;
 253   let Inst{22-16} = op;
 254   let Inst{31-23} = 0x17e;
 255   let EncodingType = 8; // SIInstrEncodingType::SOPC
 256 }
 257
 258 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
 259    Enc32 <outs, ins , asm, pattern> {
 260
 261   bits <7> SDST;
 262   bits <16> SIMM16;
 263
 264   let Inst{15-0} = SIMM16;
 265   let Inst{22-16} = SDST;
 266   let Inst{27-23} = op;
 267   let Inst{31-28} = 0xb; //encoding
 268   let EncodingType = 9; // SIInstrEncodingType::SOPK
 269 }
 270
 271 class SOPP <bits<7> op, dag ins, string asm> : Enc32 <
 272   (outs),
 273   ins,
 274   asm,
 275   [] > {
 276
 277   bits <16> SIMM16;
 278
 279   let Inst{15-0} = SIMM16;
 280   let Inst{22-16} = op;
 281   let Inst{31-23} = 0x17f; // encoding
 282   let EncodingType = 10; // SIInstrEncodingType::SOPP
 283 }
 284
 285
 286 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
 287     Enc32 <outs, ins, asm, pattern> {
 288
 289   bits<8> VDST;
 290   bits<8> VSRC;
 291   bits<2> ATTRCHAN;
 292   bits<6> ATTR;
 293
 294   let Inst{7-0} = VSRC;
 295   let Inst{9-8} = ATTRCHAN;
 296   let Inst{15-10} = ATTR;
 297   let Inst{17-16} = op;
 298   let Inst{25-18} = VDST;
 299   let Inst{31-26} = 0x32; // encoding
 300   let EncodingType = 11; // SIInstrEncodingType::VINTRP
 301
 302   let Uses = [M0];
 303 }
 304
 305 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 306     Enc32 <outs, ins, asm, pattern> {
 307
 308   bits<8> VDST;
 309   bits<9> SRC0;
 310
 311   let Inst{8-0} = SRC0;
 312   let Inst{16-9} = op;
 313   let Inst{24-17} = VDST;
 314   let Inst{31-25} = 0x3f; //encoding
 315
 316   let EncodingType = 12; // SIInstrEncodingType::VOP1
 317   let PostEncoderMethod = "VOPPostEncode";
 318 }
 319
 320 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
 321     Enc32 <outs, ins, asm, pattern> {
 322
 323   bits<8> VDST;
 324   bits<9> SRC0;
 325   bits<8> VSRC1;
 326
 327   let Inst{8-0} = SRC0;
 328   let Inst{16-9} = VSRC1;
 329   let Inst{24-17} = VDST;
 330   let Inst{30-25} = op;
 331   let Inst{31} = 0x0; //encoding
 332
 333   let EncodingType = 13; // SIInstrEncodingType::VOP2
 334   let PostEncoderMethod = "VOPPostEncode";
 335 }
 336
 337 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
 338     Enc64 <outs, ins, asm, pattern> {
 339
 340   bits<8> VDST;
 341   bits<9> SRC0;
 342   bits<9> SRC1;
 343   bits<9> SRC2;
 344   bits<3> ABS;
 345   bits<1> CLAMP;
 346   bits<2> OMOD;
 347   bits<3> NEG;
 348
 349   let Inst{7-0} = VDST;
 350   let Inst{10-8} = ABS;
 351   let Inst{11} = CLAMP;
 352   let Inst{25-17} = op;
 353   let Inst{31-26} = 0x34; //encoding
 354   let Inst{40-32} = SRC0;
 355   let Inst{49-41} = SRC1;
 356   let Inst{58-50} = SRC2;
 357   let Inst{60-59} = OMOD;
 358   let Inst{63-61} = NEG;
 359
 360   let EncodingType = 14; // SIInstrEncodingType::VOP3
 361   let PostEncoderMethod = "VOPPostEncode";
 362 }
 363
 364 class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
 365     Enc32 <outs, ins, asm, pattern> {
 366
 367   bits<9> SRC0;
 368   bits<8> VSRC1;
 369
 370   let Inst{8-0} = SRC0;
 371   let Inst{16-9} = VSRC1;
 372   let Inst{24-17} = op;
 373   let Inst{31-25} = 0x3e;
 374
 375   let EncodingType = 15; //SIInstrEncodingType::VOPC
 376   let PostEncoderMethod = "VOPPostEncode";
 377
 378   let Defs = [VCC];
 379 }
 380
 381 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
 382   op,
 383   (outs VReg_128:$vdata),
 384   (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
 385        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
 386        GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
 387   asm,
 388   []
 389 >;
 390
 391 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
 392   op,
 393   (outs regClass:$dst),
 394   (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
 395        i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
 396        i1imm:$tfe, SReg_32:$soffset),
 397   asm,
 398   []> {
 399   let mayLoad = 1;
 400 }
 401
 402 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
 403   op,
 404   (outs regClass:$dst),
 405   (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
 406        i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
 407        i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
 408   asm,
 409   []> {
 410   let mayLoad = 1;
 411 }
 412
 413 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
 414   op,
 415   (outs),
 416   (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
 417    i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
 418    GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
 419   asm,
 420   []> {
 421   let mayStore = 1;
 422 }
 423
 424 /*XXX: We should be able to infer the imm bit based on the arg types */
 425 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
 426
 427   def _SGPR : SMRD <
 428               op,
 429               (outs dstClass:$dst),
 430               (ins SReg_32:$offset, GPR2Align<SReg_64,i64>:$sbase),
 431               asm,
 432               []
 433   > {
 434     let IMM = 0;
 435   }
 436
 437   def _IMM : SMRD <
 438               op,
 439               (outs dstClass:$dst),
 440               (ins i32imm:$offset, GPR2Align<SReg_64,i64>:$sbase),
 441               asm,
 442               []
 443   > {
 444     let IMM = 1;
 445   }
 446 }
 447
 448 class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
 449   let EncoderMethod = "encodeOperand";
 450   let MIOperandInfo = opInfo;
 451 }
 452
 453 def IMM8bit : ImmLeaf <
 454   i32,
 455   [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
 456 >;
 457
 458 def IMM12bit : ImmLeaf <
 459   i16,
 460   [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
 461 >;
 462
 463 include "SIInstrFormats.td"
 464
 465 def LOAD_CONST : AMDGPUShaderInst <
 466   (outs GPRF32:$dst),
 467   (ins i32imm:$src),
 468   "LOAD_CONST $dst, $src",
 469   [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))]
 470 >;
 471
 472 include "SIInstructions.td"