src/gallium/drivers/radeon/SILowerLiteralConstants.cpp

   1 //===-- SILowerLiteralConstants.cpp - Lower intrs using literal constants--===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This pass performs the following transformation on instructions with
  10 // literal constants:
  11 //
  12 // %VGPR0 = V_MOV_IMM_I32 1
  13 //
  14 // becomes:
  15 //
  16 // BUNDLE
  17 //   * %VGPR = V_MOV_B32_32 SI_LITERAL_CONSTANT
  18 //   * SI_LOAD_LITERAL 1
  19 //
  20 // The resulting sequence matches exactly how the hardware handles immediate
  21 // operands, so this transformation greatly simplifies the code generator.
  22 //
  23 // Only the *_MOV_IMM_* support immediate operands at the moment, but when
  24 // support for immediate operands is added to other instructions, they
  25 // will be lowered here as well.
  26 //===----------------------------------------------------------------------===//
  27
  28 #include "AMDGPU.h"
  29 #include "llvm/CodeGen/MachineFunction.h"
  30 #include "llvm/CodeGen/MachineFunctionPass.h"
  31 #include "llvm/CodeGen/MachineInstrBuilder.h"
  32 #include "llvm/CodeGen/MachineInstrBundle.h"
  33
  34 using namespace llvm;
  35
  36 namespace {
  37
  38 class SILowerLiteralConstantsPass : public MachineFunctionPass {
  39
  40 private:
  41   static char ID;
  42   const TargetInstrInfo *TII;
  43
  44 public:
  45   SILowerLiteralConstantsPass(TargetMachine &tm) :
  46     MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
  47
  48   virtual bool runOnMachineFunction(MachineFunction &MF);
  49
  50   const char *getPassName() const {
  51     return "SI Lower literal constants pass";
  52   }
  53 };
  54
  55 } // End anonymous namespace
  56
  57 char SILowerLiteralConstantsPass::ID = 0;
  58
  59 FunctionPass *llvm::createSILowerLiteralConstantsPass(TargetMachine &tm) {
  60   return new SILowerLiteralConstantsPass(tm);
  61 }
  62
  63 bool SILowerLiteralConstantsPass::runOnMachineFunction(MachineFunction &MF) {
  64   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
  65                                                   BB != BB_E; ++BB) {
  66     MachineBasicBlock &MBB = *BB;
  67     for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
  68                                I != MBB.end(); I = Next, Next = llvm::next(I)) {
  69       MachineInstr &MI = *I;
  70       switch (MI.getOpcode()) {
  71       default: break;
  72       case AMDGPU::S_MOV_IMM_I32:
  73       case AMDGPU::S_MOV_IMM_I64:
  74       case AMDGPU::V_MOV_IMM_F32:
  75       case AMDGPU::V_MOV_IMM_I32: {
  76           unsigned MovOpcode;
  77           unsigned LoadLiteralOpcode;
  78           MachineOperand LiteralOp = MI.getOperand(1);
  79           if (AMDGPU::VReg_32RegClass.contains(MI.getOperand(0).getReg())) {
  80             MovOpcode = AMDGPU::V_MOV_B32_e32;
  81           } else {
  82             MovOpcode = AMDGPU::S_MOV_B32;
  83           }
  84           if (LiteralOp.isImm()) {
  85             LoadLiteralOpcode = AMDGPU::SI_LOAD_LITERAL_I32;
  86           } else {
  87             LoadLiteralOpcode = AMDGPU::SI_LOAD_LITERAL_F32;
  88           }
  89           MachineInstr *First =
  90             BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(MovOpcode),
  91                     MI.getOperand(0).getReg())
  92                     .addReg(AMDGPU::SI_LITERAL_CONSTANT);
  93           MachineInstr *Last =
  94             BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(LoadLiteralOpcode))
  95                     .addOperand(MI.getOperand(1));
  96           Last->setIsInsideBundle();
  97           llvm::finalizeBundle(MBB, First, Last);
  98           MI.eraseFromParent();
  99           break;
 100         }
 101       }
 102     }
 103   }
 104   return false;
 105 }