src/gallium/drivers/radeon/SIPropagateImmReads.cpp

   1 //===-- SIPropagateImmReads.cpp - Lower Immediate Reads Pass --------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // We can't do this in the ConvertToISA pass, because later passes might
  11 // create LOADCONST_* instructions that we would miss.  This is why we need
  12 // a separate pass for this.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "AMDGPU.h"
  17 #include "AMDGPUUtil.h"
  18 #include "SIInstrInfo.h"
  19 #include "llvm/CodeGen/MachineFunctionPass.h"
  20
  21 using namespace llvm;
  22
  23 namespace {
  24   class SIPropagateImmReadsPass : public MachineFunctionPass {
  25
  26   private:
  27     static char ID;
  28     TargetMachine &TM;
  29
  30   public:
  31     SIPropagateImmReadsPass(TargetMachine &tm) :
  32       MachineFunctionPass(ID), TM(tm) { }
  33
  34     virtual bool runOnMachineFunction(MachineFunction &MF);
  35   };
  36 } /* End anonymous namespace */
  37
  38 char SIPropagateImmReadsPass::ID = 0;
  39
  40 FunctionPass *llvm::createSIPropagateImmReadsPass(TargetMachine &tm) {
  41   return new SIPropagateImmReadsPass(tm);
  42 }
  43
  44 bool SIPropagateImmReadsPass::runOnMachineFunction(MachineFunction &MF)
  45 {
  46   const SIInstrInfo * TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
  47
  48   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
  49                                                   BB != BB_E; ++BB) {
  50     MachineBasicBlock &MBB = *BB;
  51     for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
  52          I != MBB.end(); I = Next, Next = llvm::next(I)) {
  53       MachineInstr &MI = *I;
  54
  55       switch (MI.getOpcode()) {
  56       case AMDIL::LOADCONST_f32:
  57       case AMDIL::LOADCONST_i32:
  58         break;
  59       default:
  60         continue;
  61       }
  62
  63       /* XXX: Create and use S_MOV_IMM for SREGs */
  64       BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::V_MOV_IMM))
  65           .addOperand(MI.getOperand(0))
  66           .addOperand(MI.getOperand(1));
  67
  68       MI.eraseFromParent();
  69     }
  70   }
  71   return false;
  72 }