src/gallium/drivers/radeon/SIRegisterInfo.cpp

   1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the SI implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 #include "SIRegisterInfo.h"
  16 #include "AMDGPUTargetMachine.h"
  17 #include "AMDGPUUtil.h"
  18
  19 using namespace llvm;
  20
  21 SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm,
  22     const TargetInstrInfo &tii)
  23 : AMDGPURegisterInfo(tm, tii),
  24   TM(tm),
  25   TII(tii)
  26   { }
  27
  28 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const
  29 {
  30   BitVector Reserved(getNumRegs());
  31   return Reserved;
  32 }
  33
  34 unsigned SIRegisterInfo::getBinaryCode(unsigned reg) const
  35 {
  36   switch (reg) {
  37     case AMDIL::M0: return 124;
  38     case AMDIL::SREG_LIT_0: return 128;
  39     default: return getHWRegNum(reg);
  40   }
  41 }
  42
  43 bool SIRegisterInfo::isBaseRegClass(unsigned regClassID) const
  44 {
  45   switch (regClassID) {
  46   default: return true;
  47   case AMDIL::AllReg_32RegClassID:
  48   case AMDIL::AllReg_64RegClassID:
  49     return false;
  50   }
  51 }
  52
  53 const TargetRegisterClass *
  54 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
  55 {
  56   switch (rc->getID()) {
  57   case AMDIL::GPRF32RegClassID:
  58     return &AMDIL::VReg_32RegClass;
  59   case AMDIL::GPRV4F32RegClassID:
  60   case AMDIL::GPRV4I32RegClassID:
  61     return &AMDIL::VReg_128RegClass;
  62   default: return rc;
  63   }
  64 }
  65
  66 #include "SIRegisterGetHWRegNum.inc"