src/gallium/drivers/radeon/SIRegisterInfo.h

   1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Interface definition for SIRegisterInfo
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 #ifndef SIREGISTERINFO_H_
  16 #define SIREGISTERINFO_H_
  17
  18 #include "AMDGPURegisterInfo.h"
  19
  20 namespace llvm {
  21
  22 class AMDGPUTargetMachine;
  23 class TargetInstrInfo;
  24
  25 struct SIRegisterInfo : public AMDGPURegisterInfo
  26 {
  27   AMDGPUTargetMachine &TM;
  28   const TargetInstrInfo &TII;
  29
  30   SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
  31
  32   virtual BitVector getReservedRegs(const MachineFunction &MF) const;
  33
  34   /// getBinaryCode - Returns the hardware encoding for a register
  35   virtual unsigned getBinaryCode(unsigned reg) const;
  36
  37   /// getISARegClass - rc is an AMDIL reg class.  This function returns the
  38   /// SI register class that is equivalent to the given AMDIL register class.
  39   virtual const TargetRegisterClass *
  40     getISARegClass(const TargetRegisterClass * rc) const;
  41
  42   /// getHWRegNum - Generated function that returns the hardware encoding for
  43   /// a register
  44   unsigned getHWRegNum(unsigned reg) const;
  45
  46   /// getCFGStructurizerRegClass - get the register class of the specified
  47   /// type to use in the CFGStructurizer
  48   virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
  49
  50 };
  51
  52 } // End namespace llvm
  53
  54 #endif // SIREGISTERINFO_H_