2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
30 * There are two locations (-4, 4), (4, -4). */
31 const uint32_t eg_sample_locs_2x
[4] = {
32 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
33 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
34 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
35 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
37 const unsigned eg_max_dist_2x
= 4;
39 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
40 const uint32_t eg_sample_locs_4x
[4] = {
41 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
42 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
43 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
44 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
46 const unsigned eg_max_dist_4x
= 6;
49 static const uint32_t cm_sample_locs_8x
[] = {
50 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
51 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
52 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
53 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
54 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
55 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
56 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
57 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
59 static const unsigned cm_max_dist_8x
= 8;
61 static const uint32_t cm_sample_locs_16x
[] = {
62 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
63 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
64 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
65 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
66 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
67 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
68 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
69 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
70 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
71 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
72 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
73 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
74 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
75 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
76 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
77 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
79 static const unsigned cm_max_dist_16x
= 8;
81 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
82 unsigned sample_index
, float *out_value
)
88 switch (sample_count
) {
91 out_value
[0] = out_value
[1] = 0.5;
94 offset
= 4 * (sample_index
* 2);
95 val
.idx
= (eg_sample_locs_2x
[0] >> offset
) & 0xf;
96 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
97 val
.idx
= (eg_sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
98 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
101 offset
= 4 * (sample_index
* 2);
102 val
.idx
= (eg_sample_locs_4x
[0] >> offset
) & 0xf;
103 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
104 val
.idx
= (eg_sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
105 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
108 offset
= 4 * (sample_index
% 4 * 2);
109 index
= (sample_index
/ 4) * 4;
110 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
111 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
112 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
113 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
116 offset
= 4 * (sample_index
% 4 * 2);
117 index
= (sample_index
/ 4) * 4;
118 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
119 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
120 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
121 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
126 void cayman_init_msaa(struct pipe_context
*ctx
)
128 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
131 cayman_get_sample_position(ctx
, 1, 0, rctx
->sample_locations_1x
[0]);
133 for (i
= 0; i
< 2; i
++)
134 cayman_get_sample_position(ctx
, 2, i
, rctx
->sample_locations_2x
[i
]);
135 for (i
= 0; i
< 4; i
++)
136 cayman_get_sample_position(ctx
, 4, i
, rctx
->sample_locations_4x
[i
]);
137 for (i
= 0; i
< 8; i
++)
138 cayman_get_sample_position(ctx
, 8, i
, rctx
->sample_locations_8x
[i
]);
139 for (i
= 0; i
< 16; i
++)
140 cayman_get_sample_position(ctx
, 16, i
, rctx
->sample_locations_16x
[i
]);
143 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
)
145 switch (nr_samples
) {
147 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_2x
[0]);
148 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_2x
[1]);
149 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_2x
[2]);
150 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_2x
[3]);
153 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, eg_sample_locs_4x
[0]);
154 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, eg_sample_locs_4x
[1]);
155 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, eg_sample_locs_4x
[2]);
156 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, eg_sample_locs_4x
[3]);
159 radeon_set_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
160 radeon_emit(cs
, cm_sample_locs_8x
[0]);
161 radeon_emit(cs
, cm_sample_locs_8x
[4]);
164 radeon_emit(cs
, cm_sample_locs_8x
[1]);
165 radeon_emit(cs
, cm_sample_locs_8x
[5]);
168 radeon_emit(cs
, cm_sample_locs_8x
[2]);
169 radeon_emit(cs
, cm_sample_locs_8x
[6]);
172 radeon_emit(cs
, cm_sample_locs_8x
[3]);
173 radeon_emit(cs
, cm_sample_locs_8x
[7]);
176 radeon_set_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
177 radeon_emit(cs
, cm_sample_locs_16x
[0]);
178 radeon_emit(cs
, cm_sample_locs_16x
[4]);
179 radeon_emit(cs
, cm_sample_locs_16x
[8]);
180 radeon_emit(cs
, cm_sample_locs_16x
[12]);
181 radeon_emit(cs
, cm_sample_locs_16x
[1]);
182 radeon_emit(cs
, cm_sample_locs_16x
[5]);
183 radeon_emit(cs
, cm_sample_locs_16x
[9]);
184 radeon_emit(cs
, cm_sample_locs_16x
[13]);
185 radeon_emit(cs
, cm_sample_locs_16x
[2]);
186 radeon_emit(cs
, cm_sample_locs_16x
[6]);
187 radeon_emit(cs
, cm_sample_locs_16x
[10]);
188 radeon_emit(cs
, cm_sample_locs_16x
[14]);
189 radeon_emit(cs
, cm_sample_locs_16x
[3]);
190 radeon_emit(cs
, cm_sample_locs_16x
[7]);
191 radeon_emit(cs
, cm_sample_locs_16x
[11]);
192 radeon_emit(cs
, cm_sample_locs_16x
[15]);
197 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
198 int ps_iter_samples
, int overrast_samples
)
200 int setup_samples
= nr_samples
> 1 ? nr_samples
:
201 overrast_samples
> 1 ? overrast_samples
: 0;
203 if (setup_samples
> 1) {
204 /* indexed by log2(nr_samples) */
205 unsigned max_dist
[] = {
212 unsigned log_samples
= util_logbase2(setup_samples
);
213 unsigned log_ps_iter_samples
=
214 util_logbase2(util_next_power_of_two(ps_iter_samples
));
216 radeon_set_context_reg_seq(cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
217 radeon_emit(cs
, S_028BDC_LAST_PIXEL(1) |
218 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
219 radeon_emit(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
220 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
221 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
223 if (nr_samples
> 1) {
224 radeon_set_context_reg(cs
, CM_R_028804_DB_EQAA
,
225 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
226 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
227 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
228 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
229 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
230 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
231 radeon_set_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
,
232 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1) |
233 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
234 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
235 } else if (overrast_samples
> 1) {
236 radeon_set_context_reg(cs
, CM_R_028804_DB_EQAA
,
237 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
238 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
239 S_028804_OVERRASTERIZATION_AMOUNT(log_samples
));
240 radeon_set_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
,
241 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
242 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
245 radeon_set_context_reg_seq(cs
, CM_R_028BDC_PA_SC_LINE_CNTL
, 2);
246 radeon_emit(cs
, S_028BDC_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
247 radeon_emit(cs
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
249 radeon_set_context_reg(cs
, CM_R_028804_DB_EQAA
,
250 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
251 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
252 radeon_set_context_reg(cs
, EG_R_028A4C_PA_SC_MODE_CNTL_1
,
253 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
254 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));