2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
33 boolean
r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
34 struct radeon_winsys_cs_handle
*buf
,
35 enum radeon_bo_usage usage
)
37 if (ctx
->ws
->cs_is_buffer_referenced(ctx
->rings
.gfx
.cs
, buf
, usage
)) {
40 if (ctx
->rings
.dma
.cs
&& ctx
->rings
.dma
.cs
->cdw
&&
41 ctx
->ws
->cs_is_buffer_referenced(ctx
->rings
.dma
.cs
, buf
, usage
)) {
47 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
48 struct r600_resource
*resource
,
51 enum radeon_bo_usage rusage
= RADEON_USAGE_READWRITE
;
54 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
55 return ctx
->ws
->buffer_map(resource
->cs_buf
, NULL
, usage
);
58 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
59 /* have to wait for the last write */
60 rusage
= RADEON_USAGE_WRITE
;
63 if (ctx
->rings
.gfx
.cs
->cdw
!= ctx
->initial_gfx_cs_size
&&
64 ctx
->ws
->cs_is_buffer_referenced(ctx
->rings
.gfx
.cs
,
65 resource
->cs_buf
, rusage
)) {
66 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
67 ctx
->rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
70 ctx
->rings
.gfx
.flush(ctx
, 0, NULL
);
74 if (ctx
->rings
.dma
.cs
&&
75 ctx
->rings
.dma
.cs
->cdw
&&
76 ctx
->ws
->cs_is_buffer_referenced(ctx
->rings
.dma
.cs
,
77 resource
->cs_buf
, rusage
)) {
78 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
79 ctx
->rings
.dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
82 ctx
->rings
.dma
.flush(ctx
, 0, NULL
);
87 if (busy
|| !ctx
->ws
->buffer_wait(resource
->buf
, 0, rusage
)) {
88 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
91 /* We will be wait for the GPU. Wait for any offloaded
92 * CS flush to complete to avoid busy-waiting in the winsys. */
93 ctx
->ws
->cs_sync_flush(ctx
->rings
.gfx
.cs
);
94 if (ctx
->rings
.dma
.cs
)
95 ctx
->ws
->cs_sync_flush(ctx
->rings
.dma
.cs
);
99 /* Setting the CS to NULL will prevent doing checks we have done already. */
100 return ctx
->ws
->buffer_map(resource
->cs_buf
, NULL
, usage
);
103 bool r600_init_resource(struct r600_common_screen
*rscreen
,
104 struct r600_resource
*res
,
105 unsigned size
, unsigned alignment
,
106 bool use_reusable_pool
)
108 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
109 struct pb_buffer
*old_buf
, *new_buf
;
110 enum radeon_bo_flag flags
= 0;
112 switch (res
->b
.b
.usage
) {
113 case PIPE_USAGE_STREAM
:
114 flags
= RADEON_FLAG_GTT_WC
;
116 case PIPE_USAGE_STAGING
:
117 /* Transfers are likely to occur more often with these resources. */
118 res
->domains
= RADEON_DOMAIN_GTT
;
120 case PIPE_USAGE_DYNAMIC
:
121 /* Older kernels didn't always flush the HDP cache before
124 if (rscreen
->info
.drm_minor
< 40) {
125 res
->domains
= RADEON_DOMAIN_GTT
;
126 flags
|= RADEON_FLAG_GTT_WC
;
129 flags
|= RADEON_FLAG_CPU_ACCESS
;
131 case PIPE_USAGE_DEFAULT
:
132 case PIPE_USAGE_IMMUTABLE
:
134 /* Not listing GTT here improves performance in some apps. */
135 res
->domains
= RADEON_DOMAIN_VRAM
;
136 flags
|= RADEON_FLAG_GTT_WC
;
140 if (res
->b
.b
.target
== PIPE_BUFFER
&&
141 res
->b
.b
.flags
& (PIPE_RESOURCE_FLAG_MAP_PERSISTENT
|
142 PIPE_RESOURCE_FLAG_MAP_COHERENT
)) {
143 /* Use GTT for all persistent mappings with older kernels,
144 * because they didn't always flush the HDP cache before CS
147 * Write-combined CPU mappings are fine, the kernel ensures all CPU
148 * writes finish before the GPU executes a command stream.
150 if (rscreen
->info
.drm_minor
< 40)
151 res
->domains
= RADEON_DOMAIN_GTT
;
152 else if (res
->domains
& RADEON_DOMAIN_VRAM
)
153 flags
|= RADEON_FLAG_CPU_ACCESS
;
156 /* Tiled textures are unmappable. Always put them in VRAM. */
157 if (res
->b
.b
.target
!= PIPE_BUFFER
&&
158 rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
) {
159 res
->domains
= RADEON_DOMAIN_VRAM
;
160 flags
&= ~RADEON_FLAG_CPU_ACCESS
;
161 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
164 if (rscreen
->debug_flags
& DBG_NO_WC
)
165 flags
&= ~RADEON_FLAG_GTT_WC
;
167 /* Allocate a new resource. */
168 new_buf
= rscreen
->ws
->buffer_create(rscreen
->ws
, size
, alignment
,
170 res
->domains
, flags
);
175 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
176 * NULL. This should prevent crashes with multiple contexts using
177 * the same buffer where one of the contexts invalidates it while
178 * the others are using it. */
180 res
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(new_buf
); /* should be atomic */
181 res
->buf
= new_buf
; /* should be atomic */
183 if (rscreen
->info
.r600_virtual_address
)
184 res
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(res
->cs_buf
);
186 res
->gpu_address
= 0;
188 pb_reference(&old_buf
, NULL
);
190 util_range_set_empty(&res
->valid_buffer_range
);
191 res
->TC_L2_dirty
= false;
193 if (rscreen
->debug_flags
& DBG_VM
&& res
->b
.b
.target
== PIPE_BUFFER
) {
194 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Buffer %u bytes\n",
195 res
->gpu_address
, res
->gpu_address
+ res
->buf
->size
,
201 static void r600_buffer_destroy(struct pipe_screen
*screen
,
202 struct pipe_resource
*buf
)
204 struct r600_resource
*rbuffer
= r600_resource(buf
);
206 util_range_destroy(&rbuffer
->valid_buffer_range
);
207 pb_reference(&rbuffer
->buf
, NULL
);
211 static void *r600_buffer_get_transfer(struct pipe_context
*ctx
,
212 struct pipe_resource
*resource
,
215 const struct pipe_box
*box
,
216 struct pipe_transfer
**ptransfer
,
217 void *data
, struct r600_resource
*staging
,
220 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
221 struct r600_transfer
*transfer
= util_slab_alloc(&rctx
->pool_transfers
);
223 transfer
->transfer
.resource
= resource
;
224 transfer
->transfer
.level
= level
;
225 transfer
->transfer
.usage
= usage
;
226 transfer
->transfer
.box
= *box
;
227 transfer
->transfer
.stride
= 0;
228 transfer
->transfer
.layer_stride
= 0;
229 transfer
->offset
= offset
;
230 transfer
->staging
= staging
;
231 *ptransfer
= &transfer
->transfer
;
235 static bool r600_can_dma_copy_buffer(struct r600_common_context
*rctx
,
236 unsigned dstx
, unsigned srcx
, unsigned size
)
238 bool dword_aligned
= !(dstx
% 4) && !(srcx
% 4) && !(size
% 4);
240 return rctx
->screen
->has_cp_dma
||
241 (dword_aligned
&& (rctx
->rings
.dma
.cs
||
242 rctx
->screen
->has_streamout
));
246 static void *r600_buffer_transfer_map(struct pipe_context
*ctx
,
247 struct pipe_resource
*resource
,
250 const struct pipe_box
*box
,
251 struct pipe_transfer
**ptransfer
)
253 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
254 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)ctx
->screen
;
255 struct r600_resource
*rbuffer
= r600_resource(resource
);
258 assert(box
->x
+ box
->width
<= resource
->width0
);
260 /* See if the buffer range being mapped has never been initialized,
261 * in which case it can be mapped unsynchronized. */
262 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
263 usage
& PIPE_TRANSFER_WRITE
&&
264 !util_ranges_intersect(&rbuffer
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
)) {
265 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
268 /* If discarding the entire range, discard the whole resource instead. */
269 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
&&
270 box
->x
== 0 && box
->width
== resource
->width0
) {
271 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
274 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
&&
275 !(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
276 assert(usage
& PIPE_TRANSFER_WRITE
);
278 /* Check if mapping this buffer would cause waiting for the GPU. */
279 if (r600_rings_is_buffer_referenced(rctx
, rbuffer
->cs_buf
, RADEON_USAGE_READWRITE
) ||
280 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
281 rctx
->invalidate_buffer(&rctx
->b
, &rbuffer
->b
.b
);
283 /* At this point, the buffer is always idle. */
284 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
286 else if ((usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
287 !(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
288 !(rscreen
->debug_flags
& DBG_NO_DISCARD_RANGE
) &&
289 r600_can_dma_copy_buffer(rctx
, box
->x
, 0, box
->width
)) {
290 assert(usage
& PIPE_TRANSFER_WRITE
);
292 /* Check if mapping this buffer would cause waiting for the GPU. */
293 if (r600_rings_is_buffer_referenced(rctx
, rbuffer
->cs_buf
, RADEON_USAGE_READWRITE
) ||
294 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
295 /* Do a wait-free write-only transfer using a temporary buffer. */
297 struct r600_resource
*staging
= NULL
;
299 u_upload_alloc(rctx
->uploader
, 0, box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
),
300 &offset
, (struct pipe_resource
**)&staging
, (void**)&data
);
303 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
304 return r600_buffer_get_transfer(ctx
, resource
, level
, usage
, box
,
305 ptransfer
, data
, staging
, offset
);
307 return NULL
; /* error, shouldn't occur though */
310 /* At this point, the buffer is always idle (we checked it above). */
311 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
313 /* Using a staging buffer in GTT for larger reads is much faster. */
314 else if ((usage
& PIPE_TRANSFER_READ
) &&
315 !(usage
& PIPE_TRANSFER_WRITE
) &&
316 rbuffer
->domains
== RADEON_DOMAIN_VRAM
&&
317 r600_can_dma_copy_buffer(rctx
, 0, box
->x
, box
->width
)) {
318 struct r600_resource
*staging
;
320 staging
= (struct r600_resource
*) pipe_buffer_create(
321 ctx
->screen
, PIPE_BIND_TRANSFER_READ
, PIPE_USAGE_STAGING
,
322 box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
));
324 /* Copy the VRAM buffer to the staging buffer. */
325 rctx
->dma_copy(ctx
, &staging
->b
.b
, 0,
326 box
->x
% R600_MAP_BUFFER_ALIGNMENT
,
327 0, 0, resource
, level
, box
);
329 data
= r600_buffer_map_sync_with_rings(rctx
, staging
, PIPE_TRANSFER_READ
);
330 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
332 return r600_buffer_get_transfer(ctx
, resource
, level
, usage
, box
,
333 ptransfer
, data
, staging
, 0);
337 data
= r600_buffer_map_sync_with_rings(rctx
, rbuffer
, usage
);
343 return r600_buffer_get_transfer(ctx
, resource
, level
, usage
, box
,
344 ptransfer
, data
, NULL
, 0);
347 static void r600_buffer_transfer_unmap(struct pipe_context
*ctx
,
348 struct pipe_transfer
*transfer
)
350 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
351 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
352 struct r600_resource
*rbuffer
= r600_resource(transfer
->resource
);
354 if (rtransfer
->staging
) {
355 if (rtransfer
->transfer
.usage
& PIPE_TRANSFER_WRITE
) {
356 struct pipe_resource
*dst
, *src
;
357 unsigned soffset
, doffset
, size
;
360 dst
= transfer
->resource
;
361 src
= &rtransfer
->staging
->b
.b
;
362 size
= transfer
->box
.width
;
363 doffset
= transfer
->box
.x
;
364 soffset
= rtransfer
->offset
+ transfer
->box
.x
% R600_MAP_BUFFER_ALIGNMENT
;
366 u_box_1d(soffset
, size
, &box
);
368 /* Copy the staging buffer into the original one. */
369 rctx
->dma_copy(ctx
, dst
, 0, doffset
, 0, 0, src
, 0, &box
);
371 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
374 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
375 util_range_add(&rbuffer
->valid_buffer_range
, transfer
->box
.x
,
376 transfer
->box
.x
+ transfer
->box
.width
);
378 util_slab_free(&rctx
->pool_transfers
, transfer
);
381 static const struct u_resource_vtbl r600_buffer_vtbl
=
383 NULL
, /* get_handle */
384 r600_buffer_destroy
, /* resource_destroy */
385 r600_buffer_transfer_map
, /* transfer_map */
386 NULL
, /* transfer_flush_region */
387 r600_buffer_transfer_unmap
, /* transfer_unmap */
388 NULL
/* transfer_inline_write */
391 static struct r600_resource
*
392 r600_alloc_buffer_struct(struct pipe_screen
*screen
,
393 const struct pipe_resource
*templ
)
395 struct r600_resource
*rbuffer
;
397 rbuffer
= MALLOC_STRUCT(r600_resource
);
399 rbuffer
->b
.b
= *templ
;
400 pipe_reference_init(&rbuffer
->b
.b
.reference
, 1);
401 rbuffer
->b
.b
.screen
= screen
;
402 rbuffer
->b
.vtbl
= &r600_buffer_vtbl
;
404 rbuffer
->TC_L2_dirty
= false;
405 util_range_init(&rbuffer
->valid_buffer_range
);
409 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
410 const struct pipe_resource
*templ
,
413 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
414 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
416 if (!r600_init_resource(rscreen
, rbuffer
, templ
->width0
, alignment
, TRUE
)) {
420 return &rbuffer
->b
.b
;
423 struct pipe_resource
*
424 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
425 const struct pipe_resource
*templ
,
428 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
429 struct radeon_winsys
*ws
= rscreen
->ws
;
430 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
432 rbuffer
->domains
= RADEON_DOMAIN_GTT
;
433 util_range_add(&rbuffer
->valid_buffer_range
, 0, templ
->width0
);
435 /* Convert a user pointer to a buffer. */
436 rbuffer
->buf
= ws
->buffer_from_ptr(ws
, user_memory
, templ
->width0
);
442 rbuffer
->cs_buf
= ws
->buffer_get_cs_handle(rbuffer
->buf
);
444 if (rscreen
->info
.r600_virtual_address
)
445 rbuffer
->gpu_address
=
446 ws
->buffer_get_virtual_address(rbuffer
->cs_buf
);
448 rbuffer
->gpu_address
= 0;
450 return &rbuffer
->b
.b
;