src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                         struct pb_buffer *buf,
  35                                         enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  38                 return TRUE;
  39         }
  40         if (ctx->dma.cs && ctx->dma.cs->cdw &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  42                 return TRUE;
  43         }
  44         return FALSE;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  55                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  56         }
  57
  58         if (!(usage & PIPE_TRANSFER_WRITE)) {
  59                 /* have to wait for the last write */
  60                 rusage = RADEON_USAGE_WRITE;
  61         }
  62
  63         if (ctx->gfx.cs->cdw != ctx->initial_gfx_cs_size &&
  64             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  65                                              resource->buf, rusage)) {
  66                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  67                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  68                         return NULL;
  69                 } else {
  70                         ctx->gfx.flush(ctx, 0, NULL);
  71                         busy = true;
  72                 }
  73         }
  74         if (ctx->dma.cs &&
  75             ctx->dma.cs->cdw &&
  76             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  77                                              resource->buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  80                         return NULL;
  81                 } else {
  82                         ctx->dma.flush(ctx, 0, NULL);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  94                         if (ctx->dma.cs)
  95                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return ctx->ws->buffer_map(resource->buf, NULL, usage);
 101 }
 102
 103 bool r600_init_resource(struct r600_common_screen *rscreen,
 104                         struct r600_resource *res,
 105                         uint64_t size, unsigned alignment,
 106                         bool use_reusable_pool)
 107 {
 108         struct r600_texture *rtex = (struct r600_texture*)res;
 109         struct pb_buffer *old_buf, *new_buf;
 110         enum radeon_bo_flag flags = 0;
 111
 112         switch (res->b.b.usage) {
 113         case PIPE_USAGE_STREAM:
 114                 flags = RADEON_FLAG_GTT_WC;
 115                 /* fall through */
 116         case PIPE_USAGE_STAGING:
 117                 /* Transfers are likely to occur more often with these resources. */
 118                 res->domains = RADEON_DOMAIN_GTT;
 119                 break;
 120         case PIPE_USAGE_DYNAMIC:
 121                 /* Older kernels didn't always flush the HDP cache before
 122                  * CS execution
 123                  */
 124                 if (rscreen->info.drm_major == 2 &&
 125                     rscreen->info.drm_minor < 40) {
 126                         res->domains = RADEON_DOMAIN_GTT;
 127                         flags |= RADEON_FLAG_GTT_WC;
 128                         break;
 129                 }
 130                 flags |= RADEON_FLAG_CPU_ACCESS;
 131                 /* fall through */
 132         case PIPE_USAGE_DEFAULT:
 133         case PIPE_USAGE_IMMUTABLE:
 134         default:
 135                 /* Not listing GTT here improves performance in some apps. */
 136                 res->domains = RADEON_DOMAIN_VRAM;
 137                 flags |= RADEON_FLAG_GTT_WC;
 138                 break;
 139         }
 140
 141         if (res->b.b.target == PIPE_BUFFER &&
 142             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 143                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 144                 /* Use GTT for all persistent mappings with older kernels,
 145                  * because they didn't always flush the HDP cache before CS
 146                  * execution.
 147                  *
 148                  * Write-combined CPU mappings are fine, the kernel ensures all CPU
 149                  * writes finish before the GPU executes a command stream.
 150                  */
 151                 if (rscreen->info.drm_major == 2 &&
 152                     rscreen->info.drm_minor < 40)
 153                         res->domains = RADEON_DOMAIN_GTT;
 154                 else if (res->domains & RADEON_DOMAIN_VRAM)
 155                         flags |= RADEON_FLAG_CPU_ACCESS;
 156         }
 157
 158         /* Tiled textures are unmappable. Always put them in VRAM. */
 159         if (res->b.b.target != PIPE_BUFFER &&
 160             rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
 161                 res->domains = RADEON_DOMAIN_VRAM;
 162                 flags &= ~RADEON_FLAG_CPU_ACCESS;
 163                 flags |= RADEON_FLAG_NO_CPU_ACCESS |
 164                          RADEON_FLAG_GTT_WC;
 165         }
 166
 167         /* If VRAM is just stolen system memory, allow both VRAM and GTT,
 168          * whichever has free space. If a buffer is evicted from VRAM to GTT,
 169          * it will stay there.
 170          */
 171         if (!rscreen->info.has_dedicated_vram &&
 172             res->domains == RADEON_DOMAIN_VRAM)
 173                 res->domains = RADEON_DOMAIN_VRAM_GTT;
 174
 175         if (rscreen->debug_flags & DBG_NO_WC)
 176                 flags &= ~RADEON_FLAG_GTT_WC;
 177
 178         /* Allocate a new resource. */
 179         new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
 180                                              use_reusable_pool,
 181                                              res->domains, flags);
 182         if (!new_buf) {
 183                 return false;
 184         }
 185
 186         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 187          * NULL. This should prevent crashes with multiple contexts using
 188          * the same buffer where one of the contexts invalidates it while
 189          * the others are using it. */
 190         old_buf = res->buf;
 191         res->buf = new_buf; /* should be atomic */
 192
 193         if (rscreen->info.has_virtual_memory)
 194                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 195         else
 196                 res->gpu_address = 0;
 197
 198         pb_reference(&old_buf, NULL);
 199
 200         util_range_set_empty(&res->valid_buffer_range);
 201         res->TC_L2_dirty = false;
 202
 203         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 204                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 205                         res->gpu_address, res->gpu_address + res->buf->size,
 206                         res->buf->size);
 207         }
 208         return true;
 209 }
 210
 211 static void r600_buffer_destroy(struct pipe_screen *screen,
 212                                 struct pipe_resource *buf)
 213 {
 214         struct r600_resource *rbuffer = r600_resource(buf);
 215
 216         util_range_destroy(&rbuffer->valid_buffer_range);
 217         pb_reference(&rbuffer->buf, NULL);
 218         FREE(rbuffer);
 219 }
 220
 221 static bool
 222 r600_invalidate_buffer(struct r600_common_context *rctx,
 223                        struct r600_resource *rbuffer)
 224 {
 225         /* Shared buffers can't be reallocated. */
 226         if (rbuffer->is_shared)
 227                 return false;
 228
 229         /* In AMD_pinned_memory, the user pointer association only gets
 230          * broken when the buffer is explicitly re-allocated.
 231          */
 232         if (rctx->ws->buffer_is_user_ptr(rbuffer->buf))
 233                 return false;
 234
 235         /* Check if mapping this buffer would cause waiting for the GPU. */
 236         if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 237             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 238                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 239         } else {
 240                 util_range_set_empty(&rbuffer->valid_buffer_range);
 241         }
 242
 243         return true;
 244 }
 245
 246 void r600_invalidate_resource(struct pipe_context *ctx,
 247                               struct pipe_resource *resource)
 248 {
 249         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 250         struct r600_resource *rbuffer = r600_resource(resource);
 251
 252         /* We currently only do anyting here for buffers */
 253         if (resource->target == PIPE_BUFFER)
 254                 (void)r600_invalidate_buffer(rctx, rbuffer);
 255 }
 256
 257 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 258                                       struct pipe_resource *resource,
 259                                       unsigned level,
 260                                       unsigned usage,
 261                                       const struct pipe_box *box,
 262                                       struct pipe_transfer **ptransfer,
 263                                       void *data, struct r600_resource *staging,
 264                                       unsigned offset)
 265 {
 266         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 267         struct r600_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
 268
 269         transfer->transfer.resource = resource;
 270         transfer->transfer.level = level;
 271         transfer->transfer.usage = usage;
 272         transfer->transfer.box = *box;
 273         transfer->transfer.stride = 0;
 274         transfer->transfer.layer_stride = 0;
 275         transfer->offset = offset;
 276         transfer->staging = staging;
 277         *ptransfer = &transfer->transfer;
 278         return data;
 279 }
 280
 281 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 282                                      unsigned dstx, unsigned srcx, unsigned size)
 283 {
 284         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 285
 286         return rctx->screen->has_cp_dma ||
 287                (dword_aligned && (rctx->dma.cs ||
 288                                   rctx->screen->has_streamout));
 289
 290 }
 291
 292 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 293                                       struct pipe_resource *resource,
 294                                       unsigned level,
 295                                       unsigned usage,
 296                                       const struct pipe_box *box,
 297                                       struct pipe_transfer **ptransfer)
 298 {
 299         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 300         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 301         struct r600_resource *rbuffer = r600_resource(resource);
 302         uint8_t *data;
 303
 304         assert(box->x + box->width <= resource->width0);
 305
 306         /* See if the buffer range being mapped has never been initialized,
 307          * in which case it can be mapped unsynchronized. */
 308         if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 309             usage & PIPE_TRANSFER_WRITE &&
 310             !rbuffer->is_shared &&
 311             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 312                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 313         }
 314
 315         /* If discarding the entire range, discard the whole resource instead. */
 316         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 317             box->x == 0 && box->width == resource->width0) {
 318                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 319         }
 320
 321         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 322             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 323                 assert(usage & PIPE_TRANSFER_WRITE);
 324
 325                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 326                         /* At this point, the buffer is always idle. */
 327                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 328                 } else {
 329                         /* Fall back to a temporary buffer. */
 330                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 331                 }
 332         }
 333
 334         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 335             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 336                        PIPE_TRANSFER_PERSISTENT)) &&
 337             !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 338             r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) {
 339                 assert(usage & PIPE_TRANSFER_WRITE);
 340
 341                 /* Check if mapping this buffer would cause waiting for the GPU. */
 342                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 343                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 344                         /* Do a wait-free write-only transfer using a temporary buffer. */
 345                         unsigned offset;
 346                         struct r600_resource *staging = NULL;
 347
 348                         u_upload_alloc(rctx->uploader, 0, box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 349                                        256, &offset, (struct pipe_resource**)&staging, (void**)&data);
 350
 351                         if (staging) {
 352                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 353                                 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 354                                                                 ptransfer, data, staging, offset);
 355                         }
 356                 } else {
 357                         /* At this point, the buffer is always idle (we checked it above). */
 358                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 359                 }
 360         }
 361         /* Using a staging buffer in GTT for larger reads is much faster. */
 362         else if ((usage & PIPE_TRANSFER_READ) &&
 363                  !(usage & (PIPE_TRANSFER_WRITE |
 364                             PIPE_TRANSFER_PERSISTENT)) &&
 365                  rbuffer->domains == RADEON_DOMAIN_VRAM &&
 366                  r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) {
 367                 struct r600_resource *staging;
 368
 369                 staging = (struct r600_resource*) pipe_buffer_create(
 370                                 ctx->screen, PIPE_BIND_TRANSFER_READ, PIPE_USAGE_STAGING,
 371                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 372                 if (staging) {
 373                         /* Copy the VRAM buffer to the staging buffer. */
 374                         rctx->dma_copy(ctx, &staging->b.b, 0,
 375                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 376                                        0, 0, resource, level, box);
 377
 378                         data = r600_buffer_map_sync_with_rings(rctx, staging, PIPE_TRANSFER_READ);
 379                         if (!data) {
 380                                 pipe_resource_reference((struct pipe_resource **)&staging, NULL);
 381                                 return NULL;
 382                         }
 383                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 384
 385                         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 386                                                         ptransfer, data, staging, 0);
 387                 }
 388         }
 389
 390         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 391         if (!data) {
 392                 return NULL;
 393         }
 394         data += box->x;
 395
 396         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 397                                         ptransfer, data, NULL, 0);
 398 }
 399
 400 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 401                                         struct pipe_transfer *transfer,
 402                                         const struct pipe_box *box)
 403 {
 404         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 405         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 406         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 407
 408         if (rtransfer->staging) {
 409                 struct pipe_resource *dst, *src;
 410                 unsigned soffset;
 411                 struct pipe_box dma_box;
 412
 413                 dst = transfer->resource;
 414                 src = &rtransfer->staging->b.b;
 415                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 416
 417                 u_box_1d(soffset, box->width, &dma_box);
 418
 419                 /* Copy the staging buffer into the original one. */
 420                 rctx->dma_copy(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 421         }
 422
 423         util_range_add(&rbuffer->valid_buffer_range, box->x,
 424                        box->x + box->width);
 425 }
 426
 427 static void r600_buffer_flush_region(struct pipe_context *ctx,
 428                                      struct pipe_transfer *transfer,
 429                                      const struct pipe_box *rel_box)
 430 {
 431         if (transfer->usage & (PIPE_TRANSFER_WRITE |
 432                                PIPE_TRANSFER_FLUSH_EXPLICIT)) {
 433                 struct pipe_box box;
 434
 435                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 436                 r600_buffer_do_flush_region(ctx, transfer, &box);
 437         }
 438 }
 439
 440 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 441                                        struct pipe_transfer *transfer)
 442 {
 443         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 444         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 445
 446         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 447             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 448                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 449
 450         if (rtransfer->staging)
 451                 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
 452
 453         util_slab_free(&rctx->pool_transfers, transfer);
 454 }
 455
 456 static const struct u_resource_vtbl r600_buffer_vtbl =
 457 {
 458         NULL,                           /* get_handle */
 459         r600_buffer_destroy,            /* resource_destroy */
 460         r600_buffer_transfer_map,       /* transfer_map */
 461         r600_buffer_flush_region,       /* transfer_flush_region */
 462         r600_buffer_transfer_unmap,     /* transfer_unmap */
 463         NULL                            /* transfer_inline_write */
 464 };
 465
 466 static struct r600_resource *
 467 r600_alloc_buffer_struct(struct pipe_screen *screen,
 468                          const struct pipe_resource *templ)
 469 {
 470         struct r600_resource *rbuffer;
 471
 472         rbuffer = MALLOC_STRUCT(r600_resource);
 473
 474         rbuffer->b.b = *templ;
 475         pipe_reference_init(&rbuffer->b.b.reference, 1);
 476         rbuffer->b.b.screen = screen;
 477         rbuffer->b.vtbl = &r600_buffer_vtbl;
 478         rbuffer->buf = NULL;
 479         rbuffer->TC_L2_dirty = false;
 480         rbuffer->is_shared = false;
 481         util_range_init(&rbuffer->valid_buffer_range);
 482         return rbuffer;
 483 }
 484
 485 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 486                                          const struct pipe_resource *templ,
 487                                          unsigned alignment)
 488 {
 489         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 490         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 491
 492         if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE)) {
 493                 FREE(rbuffer);
 494                 return NULL;
 495         }
 496         return &rbuffer->b.b;
 497 }
 498
 499 struct pipe_resource *r600_aligned_buffer_create(struct pipe_screen *screen,
 500                                                  unsigned bind,
 501                                                  unsigned usage,
 502                                                  unsigned size,
 503                                                  unsigned alignment)
 504 {
 505         struct pipe_resource buffer;
 506
 507         memset(&buffer, 0, sizeof buffer);
 508         buffer.target = PIPE_BUFFER;
 509         buffer.format = PIPE_FORMAT_R8_UNORM;
 510         buffer.bind = bind;
 511         buffer.usage = usage;
 512         buffer.flags = 0;
 513         buffer.width0 = size;
 514         buffer.height0 = 1;
 515         buffer.depth0 = 1;
 516         buffer.array_size = 1;
 517         return r600_buffer_create(screen, &buffer, alignment);
 518 }
 519
 520 struct pipe_resource *
 521 r600_buffer_from_user_memory(struct pipe_screen *screen,
 522                              const struct pipe_resource *templ,
 523                              void *user_memory)
 524 {
 525         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 526         struct radeon_winsys *ws = rscreen->ws;
 527         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 528
 529         rbuffer->domains = RADEON_DOMAIN_GTT;
 530         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 531
 532         /* Convert a user pointer to a buffer. */
 533         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 534         if (!rbuffer->buf) {
 535                 FREE(rbuffer);
 536                 return NULL;
 537         }
 538
 539         if (rscreen->info.has_virtual_memory)
 540                 rbuffer->gpu_address =
 541                         ws->buffer_get_virtual_address(rbuffer->buf);
 542         else
 543                 rbuffer->gpu_address = 0;
 544
 545         return &rbuffer->b.b;
 546 }