src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "r600_cs.h"
  25 #include "util/u_memory.h"
  26 #include "util/u_upload_mgr.h"
  27 #include <inttypes.h>
  28 #include <stdio.h>
  29
  30 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
  31                                    struct pb_buffer *buf,
  32                                    enum radeon_bo_usage usage)
  33 {
  34         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  35                 return true;
  36         }
  37         if (radeon_emitted(ctx->dma.cs, 0) &&
  38             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  39                 return true;
  40         }
  41         return false;
  42 }
  43
  44 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  45                                     struct r600_resource *resource,
  46                                     unsigned usage)
  47 {
  48         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  49         bool busy = false;
  50
  51         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  52
  53         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  54                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  55         }
  56
  57         if (!(usage & PIPE_TRANSFER_WRITE)) {
  58                 /* have to wait for the last write */
  59                 rusage = RADEON_USAGE_WRITE;
  60         }
  61
  62         if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
  63             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  64                                              resource->buf, rusage)) {
  65                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  66                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  67                         return NULL;
  68                 } else {
  69                         ctx->gfx.flush(ctx, 0, NULL);
  70                         busy = true;
  71                 }
  72         }
  73         if (radeon_emitted(ctx->dma.cs, 0) &&
  74             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  75                                              resource->buf, rusage)) {
  76                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  77                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  78                         return NULL;
  79                 } else {
  80                         ctx->dma.flush(ctx, 0, NULL);
  81                         busy = true;
  82                 }
  83         }
  84
  85         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  86                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  87                         return NULL;
  88                 } else {
  89                         /* We will be wait for the GPU. Wait for any offloaded
  90                          * CS flush to complete to avoid busy-waiting in the winsys. */
  91                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  92                         if (ctx->dma.cs)
  93                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  94                 }
  95         }
  96
  97         /* Setting the CS to NULL will prevent doing checks we have done already. */
  98         return ctx->ws->buffer_map(resource->buf, NULL, usage);
  99 }
 100
 101 void si_init_resource_fields(struct r600_common_screen *rscreen,
 102                              struct r600_resource *res,
 103                              uint64_t size, unsigned alignment)
 104 {
 105         struct r600_texture *rtex = (struct r600_texture*)res;
 106
 107         res->bo_size = size;
 108         res->bo_alignment = alignment;
 109         res->flags = 0;
 110         res->texture_handle_allocated = false;
 111         res->image_handle_allocated = false;
 112
 113         switch (res->b.b.usage) {
 114         case PIPE_USAGE_STREAM:
 115                 res->flags = RADEON_FLAG_GTT_WC;
 116                 /* fall through */
 117         case PIPE_USAGE_STAGING:
 118                 /* Transfers are likely to occur more often with these
 119                  * resources. */
 120                 res->domains = RADEON_DOMAIN_GTT;
 121                 break;
 122         case PIPE_USAGE_DYNAMIC:
 123                 /* Older kernels didn't always flush the HDP cache before
 124                  * CS execution
 125                  */
 126                 if (rscreen->info.drm_major == 2 &&
 127                     rscreen->info.drm_minor < 40) {
 128                         res->domains = RADEON_DOMAIN_GTT;
 129                         res->flags |= RADEON_FLAG_GTT_WC;
 130                         break;
 131                 }
 132                 /* fall through */
 133         case PIPE_USAGE_DEFAULT:
 134         case PIPE_USAGE_IMMUTABLE:
 135         default:
 136                 /* Not listing GTT here improves performance in some
 137                  * apps. */
 138                 res->domains = RADEON_DOMAIN_VRAM;
 139                 res->flags |= RADEON_FLAG_GTT_WC;
 140                 break;
 141         }
 142
 143         if (res->b.b.target == PIPE_BUFFER &&
 144             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 145                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 146                 /* Use GTT for all persistent mappings with older
 147                  * kernels, because they didn't always flush the HDP
 148                  * cache before CS execution.
 149                  *
 150                  * Write-combined CPU mappings are fine, the kernel
 151                  * ensures all CPU writes finish before the GPU
 152                  * executes a command stream.
 153                  */
 154                 if (rscreen->info.drm_major == 2 &&
 155                     rscreen->info.drm_minor < 40)
 156                         res->domains = RADEON_DOMAIN_GTT;
 157         }
 158
 159         /* Tiled textures are unmappable. Always put them in VRAM. */
 160         if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 161             res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
 162                 res->domains = RADEON_DOMAIN_VRAM;
 163                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 164                          RADEON_FLAG_GTT_WC;
 165         }
 166
 167         /* Displayable and shareable surfaces are not suballocated. */
 168         if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 169                 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
 170         else
 171                 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 172
 173         /* If VRAM is just stolen system memory, allow both VRAM and
 174          * GTT, whichever has free space. If a buffer is evicted from
 175          * VRAM to GTT, it will stay there.
 176          *
 177          * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 178          * placements even with a low amount of stolen VRAM.
 179          */
 180         if (!rscreen->info.has_dedicated_vram &&
 181             (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
 182             res->domains == RADEON_DOMAIN_VRAM) {
 183                 res->domains = RADEON_DOMAIN_VRAM_GTT;
 184                 res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
 185         }
 186
 187         if (rscreen->debug_flags & DBG(NO_WC))
 188                 res->flags &= ~RADEON_FLAG_GTT_WC;
 189
 190         /* Set expected VRAM and GART usage for the buffer. */
 191         res->vram_usage = 0;
 192         res->gart_usage = 0;
 193
 194         if (res->domains & RADEON_DOMAIN_VRAM)
 195                 res->vram_usage = size;
 196         else if (res->domains & RADEON_DOMAIN_GTT)
 197                 res->gart_usage = size;
 198 }
 199
 200 bool si_alloc_resource(struct r600_common_screen *rscreen,
 201                        struct r600_resource *res)
 202 {
 203         struct pb_buffer *old_buf, *new_buf;
 204
 205         /* Allocate a new resource. */
 206         new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
 207                                              res->bo_alignment,
 208                                              res->domains, res->flags);
 209         if (!new_buf) {
 210                 return false;
 211         }
 212
 213         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 214          * NULL. This should prevent crashes with multiple contexts using
 215          * the same buffer where one of the contexts invalidates it while
 216          * the others are using it. */
 217         old_buf = res->buf;
 218         res->buf = new_buf; /* should be atomic */
 219
 220         if (rscreen->info.has_virtual_memory)
 221                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 222         else
 223                 res->gpu_address = 0;
 224
 225         pb_reference(&old_buf, NULL);
 226
 227         util_range_set_empty(&res->valid_buffer_range);
 228         res->TC_L2_dirty = false;
 229
 230         /* Print debug information. */
 231         if (rscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
 232                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 233                         res->gpu_address, res->gpu_address + res->buf->size,
 234                         res->buf->size);
 235         }
 236         return true;
 237 }
 238
 239 static void r600_buffer_destroy(struct pipe_screen *screen,
 240                                 struct pipe_resource *buf)
 241 {
 242         struct r600_resource *rbuffer = r600_resource(buf);
 243
 244         threaded_resource_deinit(buf);
 245         util_range_destroy(&rbuffer->valid_buffer_range);
 246         pb_reference(&rbuffer->buf, NULL);
 247         FREE(rbuffer);
 248 }
 249
 250 static bool
 251 r600_invalidate_buffer(struct r600_common_context *rctx,
 252                        struct r600_resource *rbuffer)
 253 {
 254         /* Shared buffers can't be reallocated. */
 255         if (rbuffer->b.is_shared)
 256                 return false;
 257
 258         /* Sparse buffers can't be reallocated. */
 259         if (rbuffer->flags & RADEON_FLAG_SPARSE)
 260                 return false;
 261
 262         /* In AMD_pinned_memory, the user pointer association only gets
 263          * broken when the buffer is explicitly re-allocated.
 264          */
 265         if (rbuffer->b.is_user_ptr)
 266                 return false;
 267
 268         /* Check if mapping this buffer would cause waiting for the GPU. */
 269         if (si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 270             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 271                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 272         } else {
 273                 util_range_set_empty(&rbuffer->valid_buffer_range);
 274         }
 275
 276         return true;
 277 }
 278
 279 /* Replace the storage of dst with src. */
 280 void si_replace_buffer_storage(struct pipe_context *ctx,
 281                                  struct pipe_resource *dst,
 282                                  struct pipe_resource *src)
 283 {
 284         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 285         struct r600_resource *rdst = r600_resource(dst);
 286         struct r600_resource *rsrc = r600_resource(src);
 287         uint64_t old_gpu_address = rdst->gpu_address;
 288
 289         pb_reference(&rdst->buf, rsrc->buf);
 290         rdst->gpu_address = rsrc->gpu_address;
 291         rdst->b.b.bind = rsrc->b.b.bind;
 292         rdst->flags = rsrc->flags;
 293
 294         assert(rdst->vram_usage == rsrc->vram_usage);
 295         assert(rdst->gart_usage == rsrc->gart_usage);
 296         assert(rdst->bo_size == rsrc->bo_size);
 297         assert(rdst->bo_alignment == rsrc->bo_alignment);
 298         assert(rdst->domains == rsrc->domains);
 299
 300         rctx->rebind_buffer(ctx, dst, old_gpu_address);
 301 }
 302
 303 void si_invalidate_resource(struct pipe_context *ctx,
 304                             struct pipe_resource *resource)
 305 {
 306         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 307         struct r600_resource *rbuffer = r600_resource(resource);
 308
 309         /* We currently only do anyting here for buffers */
 310         if (resource->target == PIPE_BUFFER)
 311                 (void)r600_invalidate_buffer(rctx, rbuffer);
 312 }
 313
 314 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 315                                       struct pipe_resource *resource,
 316                                       unsigned usage,
 317                                       const struct pipe_box *box,
 318                                       struct pipe_transfer **ptransfer,
 319                                       void *data, struct r600_resource *staging,
 320                                       unsigned offset)
 321 {
 322         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 323         struct r600_transfer *transfer;
 324
 325         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 326                 transfer = slab_alloc(&rctx->pool_transfers_unsync);
 327         else
 328                 transfer = slab_alloc(&rctx->pool_transfers);
 329
 330         transfer->b.b.resource = NULL;
 331         pipe_resource_reference(&transfer->b.b.resource, resource);
 332         transfer->b.b.level = 0;
 333         transfer->b.b.usage = usage;
 334         transfer->b.b.box = *box;
 335         transfer->b.b.stride = 0;
 336         transfer->b.b.layer_stride = 0;
 337         transfer->b.staging = NULL;
 338         transfer->offset = offset;
 339         transfer->staging = staging;
 340         *ptransfer = &transfer->b.b;
 341         return data;
 342 }
 343
 344 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 345                                      unsigned dstx, unsigned srcx, unsigned size)
 346 {
 347         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 348
 349         return rctx->screen->has_cp_dma ||
 350                (dword_aligned && (rctx->dma.cs ||
 351                                   rctx->screen->has_streamout));
 352
 353 }
 354
 355 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 356                                       struct pipe_resource *resource,
 357                                       unsigned level,
 358                                       unsigned usage,
 359                                       const struct pipe_box *box,
 360                                       struct pipe_transfer **ptransfer)
 361 {
 362         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 363         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 364         struct r600_resource *rbuffer = r600_resource(resource);
 365         uint8_t *data;
 366
 367         assert(box->x + box->width <= resource->width0);
 368
 369         /* From GL_AMD_pinned_memory issues:
 370          *
 371          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 372          *        same system address which was specified at creation time?
 373          *
 374          *        RESOLVED: NO. The GL implementation might return a different
 375          *        virtual mapping of that memory, although the same physical
 376          *        page will be used.
 377          *
 378          * So don't ever use staging buffers.
 379          */
 380         if (rbuffer->b.is_user_ptr)
 381                 usage |= PIPE_TRANSFER_PERSISTENT;
 382
 383         /* See if the buffer range being mapped has never been initialized,
 384          * in which case it can be mapped unsynchronized. */
 385         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 386                        TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
 387             usage & PIPE_TRANSFER_WRITE &&
 388             !rbuffer->b.is_shared &&
 389             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 390                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 391         }
 392
 393         /* If discarding the entire range, discard the whole resource instead. */
 394         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 395             box->x == 0 && box->width == resource->width0) {
 396                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 397         }
 398
 399         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 400             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 401                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 402                 assert(usage & PIPE_TRANSFER_WRITE);
 403
 404                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 405                         /* At this point, the buffer is always idle. */
 406                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 407                 } else {
 408                         /* Fall back to a temporary buffer. */
 409                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 410                 }
 411         }
 412
 413         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 414             !(rscreen->debug_flags & DBG(NO_DISCARD_RANGE)) &&
 415             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 416                          PIPE_TRANSFER_PERSISTENT)) &&
 417               r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
 418              (rbuffer->flags & RADEON_FLAG_SPARSE))) {
 419                 assert(usage & PIPE_TRANSFER_WRITE);
 420
 421                 /* Check if mapping this buffer would cause waiting for the GPU.
 422                  */
 423                 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
 424                     si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 425                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 426                         /* Do a wait-free write-only transfer using a temporary buffer. */
 427                         unsigned offset;
 428                         struct r600_resource *staging = NULL;
 429
 430                         u_upload_alloc(ctx->stream_uploader, 0,
 431                                        box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 432                                        rctx->screen->info.tcc_cache_line_size,
 433                                        &offset, (struct pipe_resource**)&staging,
 434                                        (void**)&data);
 435
 436                         if (staging) {
 437                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 438                                 return r600_buffer_get_transfer(ctx, resource, usage, box,
 439                                                                 ptransfer, data, staging, offset);
 440                         } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 441                                 return NULL;
 442                         }
 443                 } else {
 444                         /* At this point, the buffer is always idle (we checked it above). */
 445                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 446                 }
 447         }
 448         /* Use a staging buffer in cached GTT for reads. */
 449         else if (((usage & PIPE_TRANSFER_READ) &&
 450                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 451                   (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 452                    rbuffer->flags & RADEON_FLAG_GTT_WC) &&
 453                   r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
 454                  (rbuffer->flags & RADEON_FLAG_SPARSE)) {
 455                 struct r600_resource *staging;
 456
 457                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 458                 staging = (struct r600_resource*) pipe_buffer_create(
 459                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 460                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 461                 if (staging) {
 462                         /* Copy the VRAM buffer to the staging buffer. */
 463                         rctx->dma_copy(ctx, &staging->b.b, 0,
 464                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 465                                        0, 0, resource, 0, box);
 466
 467                         data = si_buffer_map_sync_with_rings(rctx, staging,
 468                                                                usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 469                         if (!data) {
 470                                 r600_resource_reference(&staging, NULL);
 471                                 return NULL;
 472                         }
 473                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 474
 475                         return r600_buffer_get_transfer(ctx, resource, usage, box,
 476                                                         ptransfer, data, staging, 0);
 477                 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 478                         return NULL;
 479                 }
 480         }
 481
 482         data = si_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 483         if (!data) {
 484                 return NULL;
 485         }
 486         data += box->x;
 487
 488         return r600_buffer_get_transfer(ctx, resource, usage, box,
 489                                         ptransfer, data, NULL, 0);
 490 }
 491
 492 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 493                                         struct pipe_transfer *transfer,
 494                                         const struct pipe_box *box)
 495 {
 496         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 497         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 498
 499         if (rtransfer->staging) {
 500                 struct pipe_resource *dst, *src;
 501                 unsigned soffset;
 502                 struct pipe_box dma_box;
 503
 504                 dst = transfer->resource;
 505                 src = &rtransfer->staging->b.b;
 506                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 507
 508                 u_box_1d(soffset, box->width, &dma_box);
 509
 510                 /* Copy the staging buffer into the original one. */
 511                 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 512         }
 513
 514         util_range_add(&rbuffer->valid_buffer_range, box->x,
 515                        box->x + box->width);
 516 }
 517
 518 static void r600_buffer_flush_region(struct pipe_context *ctx,
 519                                      struct pipe_transfer *transfer,
 520                                      const struct pipe_box *rel_box)
 521 {
 522         unsigned required_usage = PIPE_TRANSFER_WRITE |
 523                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 524
 525         if ((transfer->usage & required_usage) == required_usage) {
 526                 struct pipe_box box;
 527
 528                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 529                 r600_buffer_do_flush_region(ctx, transfer, &box);
 530         }
 531 }
 532
 533 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 534                                        struct pipe_transfer *transfer)
 535 {
 536         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 537         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 538
 539         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 540             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 541                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 542
 543         r600_resource_reference(&rtransfer->staging, NULL);
 544         assert(rtransfer->b.staging == NULL); /* for threaded context only */
 545         pipe_resource_reference(&transfer->resource, NULL);
 546
 547         /* Don't use pool_transfers_unsync. We are always in the driver
 548          * thread. */
 549         slab_free(&rctx->pool_transfers, transfer);
 550 }
 551
 552 void si_buffer_subdata(struct pipe_context *ctx,
 553                        struct pipe_resource *buffer,
 554                        unsigned usage, unsigned offset,
 555                        unsigned size, const void *data)
 556 {
 557         struct pipe_transfer *transfer = NULL;
 558         struct pipe_box box;
 559         uint8_t *map = NULL;
 560
 561         u_box_1d(offset, size, &box);
 562         map = r600_buffer_transfer_map(ctx, buffer, 0,
 563                                        PIPE_TRANSFER_WRITE |
 564                                        PIPE_TRANSFER_DISCARD_RANGE |
 565                                        usage,
 566                                        &box, &transfer);
 567         if (!map)
 568                 return;
 569
 570         memcpy(map, data, size);
 571         r600_buffer_transfer_unmap(ctx, transfer);
 572 }
 573
 574 static const struct u_resource_vtbl r600_buffer_vtbl =
 575 {
 576         NULL,                           /* get_handle */
 577         r600_buffer_destroy,            /* resource_destroy */
 578         r600_buffer_transfer_map,       /* transfer_map */
 579         r600_buffer_flush_region,       /* transfer_flush_region */
 580         r600_buffer_transfer_unmap,     /* transfer_unmap */
 581 };
 582
 583 static struct r600_resource *
 584 r600_alloc_buffer_struct(struct pipe_screen *screen,
 585                          const struct pipe_resource *templ)
 586 {
 587         struct r600_resource *rbuffer;
 588
 589         rbuffer = MALLOC_STRUCT(r600_resource);
 590
 591         rbuffer->b.b = *templ;
 592         rbuffer->b.b.next = NULL;
 593         pipe_reference_init(&rbuffer->b.b.reference, 1);
 594         rbuffer->b.b.screen = screen;
 595
 596         rbuffer->b.vtbl = &r600_buffer_vtbl;
 597         threaded_resource_init(&rbuffer->b.b);
 598
 599         rbuffer->buf = NULL;
 600         rbuffer->bind_history = 0;
 601         rbuffer->TC_L2_dirty = false;
 602         util_range_init(&rbuffer->valid_buffer_range);
 603         return rbuffer;
 604 }
 605
 606 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 607                                        const struct pipe_resource *templ,
 608                                        unsigned alignment)
 609 {
 610         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 611         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 612
 613         si_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
 614
 615         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 616                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 617
 618         if (!si_alloc_resource(rscreen, rbuffer)) {
 619                 FREE(rbuffer);
 620                 return NULL;
 621         }
 622         return &rbuffer->b.b;
 623 }
 624
 625 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 626                                                unsigned flags,
 627                                                unsigned usage,
 628                                                unsigned size,
 629                                                unsigned alignment)
 630 {
 631         struct pipe_resource buffer;
 632
 633         memset(&buffer, 0, sizeof buffer);
 634         buffer.target = PIPE_BUFFER;
 635         buffer.format = PIPE_FORMAT_R8_UNORM;
 636         buffer.bind = 0;
 637         buffer.usage = usage;
 638         buffer.flags = flags;
 639         buffer.width0 = size;
 640         buffer.height0 = 1;
 641         buffer.depth0 = 1;
 642         buffer.array_size = 1;
 643         return si_buffer_create(screen, &buffer, alignment);
 644 }
 645
 646 struct pipe_resource *
 647 si_buffer_from_user_memory(struct pipe_screen *screen,
 648                            const struct pipe_resource *templ,
 649                            void *user_memory)
 650 {
 651         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 652         struct radeon_winsys *ws = rscreen->ws;
 653         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 654
 655         rbuffer->domains = RADEON_DOMAIN_GTT;
 656         rbuffer->flags = 0;
 657         rbuffer->b.is_user_ptr = true;
 658         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 659         util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
 660
 661         /* Convert a user pointer to a buffer. */
 662         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 663         if (!rbuffer->buf) {
 664                 FREE(rbuffer);
 665                 return NULL;
 666         }
 667
 668         if (rscreen->info.has_virtual_memory)
 669                 rbuffer->gpu_address =
 670                         ws->buffer_get_virtual_address(rbuffer->buf);
 671         else
 672                 rbuffer->gpu_address = 0;
 673
 674         rbuffer->vram_usage = 0;
 675         rbuffer->gart_usage = templ->width0;
 676
 677         return &rbuffer->b.b;
 678 }