src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                    struct pb_buffer *buf,
  35                                    enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  38                 return true;
  39         }
  40         if (radeon_emitted(ctx->dma.cs, 0) &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  42                 return true;
  43         }
  44         return false;
  45 }
  46
  47 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                     struct r600_resource *resource,
  49                                     unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  55
  56         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  57                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  58         }
  59
  60         if (!(usage & PIPE_TRANSFER_WRITE)) {
  61                 /* have to wait for the last write */
  62                 rusage = RADEON_USAGE_WRITE;
  63         }
  64
  65         if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
  66             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  67                                              resource->buf, rusage)) {
  68                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  69                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  70                         return NULL;
  71                 } else {
  72                         ctx->gfx.flush(ctx, 0, NULL);
  73                         busy = true;
  74                 }
  75         }
  76         if (radeon_emitted(ctx->dma.cs, 0) &&
  77             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  78                                              resource->buf, rusage)) {
  79                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  80                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  81                         return NULL;
  82                 } else {
  83                         ctx->dma.flush(ctx, 0, NULL);
  84                         busy = true;
  85                 }
  86         }
  87
  88         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  89                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  90                         return NULL;
  91                 } else {
  92                         /* We will be wait for the GPU. Wait for any offloaded
  93                          * CS flush to complete to avoid busy-waiting in the winsys. */
  94                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  95                         if (ctx->dma.cs)
  96                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  97                 }
  98         }
  99
 100         /* Setting the CS to NULL will prevent doing checks we have done already. */
 101         return ctx->ws->buffer_map(resource->buf, NULL, usage);
 102 }
 103
 104 void si_init_resource_fields(struct r600_common_screen *rscreen,
 105                              struct r600_resource *res,
 106                              uint64_t size, unsigned alignment)
 107 {
 108         struct r600_texture *rtex = (struct r600_texture*)res;
 109
 110         res->bo_size = size;
 111         res->bo_alignment = alignment;
 112         res->flags = 0;
 113         res->texture_handle_allocated = false;
 114         res->image_handle_allocated = false;
 115
 116         switch (res->b.b.usage) {
 117         case PIPE_USAGE_STREAM:
 118                 res->flags = RADEON_FLAG_GTT_WC;
 119                 /* fall through */
 120         case PIPE_USAGE_STAGING:
 121                 /* Transfers are likely to occur more often with these
 122                  * resources. */
 123                 res->domains = RADEON_DOMAIN_GTT;
 124                 break;
 125         case PIPE_USAGE_DYNAMIC:
 126                 /* Older kernels didn't always flush the HDP cache before
 127                  * CS execution
 128                  */
 129                 if (rscreen->info.drm_major == 2 &&
 130                     rscreen->info.drm_minor < 40) {
 131                         res->domains = RADEON_DOMAIN_GTT;
 132                         res->flags |= RADEON_FLAG_GTT_WC;
 133                         break;
 134                 }
 135                 /* fall through */
 136         case PIPE_USAGE_DEFAULT:
 137         case PIPE_USAGE_IMMUTABLE:
 138         default:
 139                 /* Not listing GTT here improves performance in some
 140                  * apps. */
 141                 res->domains = RADEON_DOMAIN_VRAM;
 142                 res->flags |= RADEON_FLAG_GTT_WC;
 143                 break;
 144         }
 145
 146         if (res->b.b.target == PIPE_BUFFER &&
 147             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 148                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 149                 /* Use GTT for all persistent mappings with older
 150                  * kernels, because they didn't always flush the HDP
 151                  * cache before CS execution.
 152                  *
 153                  * Write-combined CPU mappings are fine, the kernel
 154                  * ensures all CPU writes finish before the GPU
 155                  * executes a command stream.
 156                  */
 157                 if (rscreen->info.drm_major == 2 &&
 158                     rscreen->info.drm_minor < 40)
 159                         res->domains = RADEON_DOMAIN_GTT;
 160         }
 161
 162         /* Tiled textures are unmappable. Always put them in VRAM. */
 163         if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 164             res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
 165                 res->domains = RADEON_DOMAIN_VRAM;
 166                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 167                          RADEON_FLAG_GTT_WC;
 168         }
 169
 170         /* Only displayable single-sample textures can be shared between
 171          * processes. */
 172         if (!(res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT)) &&
 173             (res->b.b.target == PIPE_BUFFER ||
 174              res->b.b.nr_samples >= 2 ||
 175              rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY))
 176                 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 177
 178         /* If VRAM is just stolen system memory, allow both VRAM and
 179          * GTT, whichever has free space. If a buffer is evicted from
 180          * VRAM to GTT, it will stay there.
 181          *
 182          * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 183          * placements even with a low amount of stolen VRAM.
 184          */
 185         if (!rscreen->info.has_dedicated_vram &&
 186             (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
 187             res->domains == RADEON_DOMAIN_VRAM) {
 188                 res->domains = RADEON_DOMAIN_VRAM_GTT;
 189                 res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
 190         }
 191
 192         if (rscreen->debug_flags & DBG_NO_WC)
 193                 res->flags &= ~RADEON_FLAG_GTT_WC;
 194
 195         if (res->b.b.bind & PIPE_BIND_SHARED)
 196                 res->flags |= RADEON_FLAG_NO_SUBALLOC;
 197
 198         /* Set expected VRAM and GART usage for the buffer. */
 199         res->vram_usage = 0;
 200         res->gart_usage = 0;
 201
 202         if (res->domains & RADEON_DOMAIN_VRAM)
 203                 res->vram_usage = size;
 204         else if (res->domains & RADEON_DOMAIN_GTT)
 205                 res->gart_usage = size;
 206 }
 207
 208 bool si_alloc_resource(struct r600_common_screen *rscreen,
 209                        struct r600_resource *res)
 210 {
 211         struct pb_buffer *old_buf, *new_buf;
 212
 213         /* Allocate a new resource. */
 214         new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
 215                                              res->bo_alignment,
 216                                              res->domains, res->flags);
 217         if (!new_buf) {
 218                 return false;
 219         }
 220
 221         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 222          * NULL. This should prevent crashes with multiple contexts using
 223          * the same buffer where one of the contexts invalidates it while
 224          * the others are using it. */
 225         old_buf = res->buf;
 226         res->buf = new_buf; /* should be atomic */
 227
 228         if (rscreen->info.has_virtual_memory)
 229                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 230         else
 231                 res->gpu_address = 0;
 232
 233         pb_reference(&old_buf, NULL);
 234
 235         util_range_set_empty(&res->valid_buffer_range);
 236         res->TC_L2_dirty = false;
 237
 238         /* Print debug information. */
 239         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 240                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 241                         res->gpu_address, res->gpu_address + res->buf->size,
 242                         res->buf->size);
 243         }
 244         return true;
 245 }
 246
 247 static void r600_buffer_destroy(struct pipe_screen *screen,
 248                                 struct pipe_resource *buf)
 249 {
 250         struct r600_resource *rbuffer = r600_resource(buf);
 251
 252         threaded_resource_deinit(buf);
 253         util_range_destroy(&rbuffer->valid_buffer_range);
 254         pb_reference(&rbuffer->buf, NULL);
 255         FREE(rbuffer);
 256 }
 257
 258 static bool
 259 r600_invalidate_buffer(struct r600_common_context *rctx,
 260                        struct r600_resource *rbuffer)
 261 {
 262         /* Shared buffers can't be reallocated. */
 263         if (rbuffer->b.is_shared)
 264                 return false;
 265
 266         /* Sparse buffers can't be reallocated. */
 267         if (rbuffer->flags & RADEON_FLAG_SPARSE)
 268                 return false;
 269
 270         /* In AMD_pinned_memory, the user pointer association only gets
 271          * broken when the buffer is explicitly re-allocated.
 272          */
 273         if (rbuffer->b.is_user_ptr)
 274                 return false;
 275
 276         /* Check if mapping this buffer would cause waiting for the GPU. */
 277         if (si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 278             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 279                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 280         } else {
 281                 util_range_set_empty(&rbuffer->valid_buffer_range);
 282         }
 283
 284         return true;
 285 }
 286
 287 /* Replace the storage of dst with src. */
 288 void si_replace_buffer_storage(struct pipe_context *ctx,
 289                                  struct pipe_resource *dst,
 290                                  struct pipe_resource *src)
 291 {
 292         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 293         struct r600_resource *rdst = r600_resource(dst);
 294         struct r600_resource *rsrc = r600_resource(src);
 295         uint64_t old_gpu_address = rdst->gpu_address;
 296
 297         pb_reference(&rdst->buf, rsrc->buf);
 298         rdst->gpu_address = rsrc->gpu_address;
 299         rdst->b.b.bind = rsrc->b.b.bind;
 300         rdst->flags = rsrc->flags;
 301
 302         assert(rdst->vram_usage == rsrc->vram_usage);
 303         assert(rdst->gart_usage == rsrc->gart_usage);
 304         assert(rdst->bo_size == rsrc->bo_size);
 305         assert(rdst->bo_alignment == rsrc->bo_alignment);
 306         assert(rdst->domains == rsrc->domains);
 307
 308         rctx->rebind_buffer(ctx, dst, old_gpu_address);
 309 }
 310
 311 void si_invalidate_resource(struct pipe_context *ctx,
 312                             struct pipe_resource *resource)
 313 {
 314         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 315         struct r600_resource *rbuffer = r600_resource(resource);
 316
 317         /* We currently only do anyting here for buffers */
 318         if (resource->target == PIPE_BUFFER)
 319                 (void)r600_invalidate_buffer(rctx, rbuffer);
 320 }
 321
 322 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 323                                       struct pipe_resource *resource,
 324                                       unsigned usage,
 325                                       const struct pipe_box *box,
 326                                       struct pipe_transfer **ptransfer,
 327                                       void *data, struct r600_resource *staging,
 328                                       unsigned offset)
 329 {
 330         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 331         struct r600_transfer *transfer;
 332
 333         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 334                 transfer = slab_alloc(&rctx->pool_transfers_unsync);
 335         else
 336                 transfer = slab_alloc(&rctx->pool_transfers);
 337
 338         transfer->b.b.resource = NULL;
 339         pipe_resource_reference(&transfer->b.b.resource, resource);
 340         transfer->b.b.level = 0;
 341         transfer->b.b.usage = usage;
 342         transfer->b.b.box = *box;
 343         transfer->b.b.stride = 0;
 344         transfer->b.b.layer_stride = 0;
 345         transfer->b.staging = NULL;
 346         transfer->offset = offset;
 347         transfer->staging = staging;
 348         *ptransfer = &transfer->b.b;
 349         return data;
 350 }
 351
 352 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 353                                      unsigned dstx, unsigned srcx, unsigned size)
 354 {
 355         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 356
 357         return rctx->screen->has_cp_dma ||
 358                (dword_aligned && (rctx->dma.cs ||
 359                                   rctx->screen->has_streamout));
 360
 361 }
 362
 363 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 364                                       struct pipe_resource *resource,
 365                                       unsigned level,
 366                                       unsigned usage,
 367                                       const struct pipe_box *box,
 368                                       struct pipe_transfer **ptransfer)
 369 {
 370         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 371         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 372         struct r600_resource *rbuffer = r600_resource(resource);
 373         uint8_t *data;
 374
 375         assert(box->x + box->width <= resource->width0);
 376
 377         /* From GL_AMD_pinned_memory issues:
 378          *
 379          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 380          *        same system address which was specified at creation time?
 381          *
 382          *        RESOLVED: NO. The GL implementation might return a different
 383          *        virtual mapping of that memory, although the same physical
 384          *        page will be used.
 385          *
 386          * So don't ever use staging buffers.
 387          */
 388         if (rbuffer->b.is_user_ptr)
 389                 usage |= PIPE_TRANSFER_PERSISTENT;
 390
 391         /* See if the buffer range being mapped has never been initialized,
 392          * in which case it can be mapped unsynchronized. */
 393         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 394                        TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
 395             usage & PIPE_TRANSFER_WRITE &&
 396             !rbuffer->b.is_shared &&
 397             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 398                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 399         }
 400
 401         /* If discarding the entire range, discard the whole resource instead. */
 402         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 403             box->x == 0 && box->width == resource->width0) {
 404                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 405         }
 406
 407         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 408             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 409                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 410                 assert(usage & PIPE_TRANSFER_WRITE);
 411
 412                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 413                         /* At this point, the buffer is always idle. */
 414                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 415                 } else {
 416                         /* Fall back to a temporary buffer. */
 417                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 418                 }
 419         }
 420
 421         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 422             !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 423             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 424                          PIPE_TRANSFER_PERSISTENT)) &&
 425               r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
 426              (rbuffer->flags & RADEON_FLAG_SPARSE))) {
 427                 assert(usage & PIPE_TRANSFER_WRITE);
 428
 429                 /* Check if mapping this buffer would cause waiting for the GPU.
 430                  */
 431                 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
 432                     si_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 433                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 434                         /* Do a wait-free write-only transfer using a temporary buffer. */
 435                         unsigned offset;
 436                         struct r600_resource *staging = NULL;
 437
 438                         u_upload_alloc(ctx->stream_uploader, 0,
 439                                        box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 440                                        rctx->screen->info.tcc_cache_line_size,
 441                                        &offset, (struct pipe_resource**)&staging,
 442                                        (void**)&data);
 443
 444                         if (staging) {
 445                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 446                                 return r600_buffer_get_transfer(ctx, resource, usage, box,
 447                                                                 ptransfer, data, staging, offset);
 448                         } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 449                                 return NULL;
 450                         }
 451                 } else {
 452                         /* At this point, the buffer is always idle (we checked it above). */
 453                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 454                 }
 455         }
 456         /* Use a staging buffer in cached GTT for reads. */
 457         else if (((usage & PIPE_TRANSFER_READ) &&
 458                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 459                   (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 460                    rbuffer->flags & RADEON_FLAG_GTT_WC) &&
 461                   r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
 462                  (rbuffer->flags & RADEON_FLAG_SPARSE)) {
 463                 struct r600_resource *staging;
 464
 465                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 466                 staging = (struct r600_resource*) pipe_buffer_create(
 467                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 468                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 469                 if (staging) {
 470                         /* Copy the VRAM buffer to the staging buffer. */
 471                         rctx->dma_copy(ctx, &staging->b.b, 0,
 472                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 473                                        0, 0, resource, 0, box);
 474
 475                         data = si_buffer_map_sync_with_rings(rctx, staging,
 476                                                                usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 477                         if (!data) {
 478                                 r600_resource_reference(&staging, NULL);
 479                                 return NULL;
 480                         }
 481                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 482
 483                         return r600_buffer_get_transfer(ctx, resource, usage, box,
 484                                                         ptransfer, data, staging, 0);
 485                 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 486                         return NULL;
 487                 }
 488         }
 489
 490         data = si_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 491         if (!data) {
 492                 return NULL;
 493         }
 494         data += box->x;
 495
 496         return r600_buffer_get_transfer(ctx, resource, usage, box,
 497                                         ptransfer, data, NULL, 0);
 498 }
 499
 500 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 501                                         struct pipe_transfer *transfer,
 502                                         const struct pipe_box *box)
 503 {
 504         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 505         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 506
 507         if (rtransfer->staging) {
 508                 struct pipe_resource *dst, *src;
 509                 unsigned soffset;
 510                 struct pipe_box dma_box;
 511
 512                 dst = transfer->resource;
 513                 src = &rtransfer->staging->b.b;
 514                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 515
 516                 u_box_1d(soffset, box->width, &dma_box);
 517
 518                 /* Copy the staging buffer into the original one. */
 519                 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 520         }
 521
 522         util_range_add(&rbuffer->valid_buffer_range, box->x,
 523                        box->x + box->width);
 524 }
 525
 526 static void r600_buffer_flush_region(struct pipe_context *ctx,
 527                                      struct pipe_transfer *transfer,
 528                                      const struct pipe_box *rel_box)
 529 {
 530         unsigned required_usage = PIPE_TRANSFER_WRITE |
 531                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 532
 533         if ((transfer->usage & required_usage) == required_usage) {
 534                 struct pipe_box box;
 535
 536                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 537                 r600_buffer_do_flush_region(ctx, transfer, &box);
 538         }
 539 }
 540
 541 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 542                                        struct pipe_transfer *transfer)
 543 {
 544         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 545         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 546
 547         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 548             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 549                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 550
 551         r600_resource_reference(&rtransfer->staging, NULL);
 552         assert(rtransfer->b.staging == NULL); /* for threaded context only */
 553         pipe_resource_reference(&transfer->resource, NULL);
 554
 555         /* Don't use pool_transfers_unsync. We are always in the driver
 556          * thread. */
 557         slab_free(&rctx->pool_transfers, transfer);
 558 }
 559
 560 void si_buffer_subdata(struct pipe_context *ctx,
 561                        struct pipe_resource *buffer,
 562                        unsigned usage, unsigned offset,
 563                        unsigned size, const void *data)
 564 {
 565         struct pipe_transfer *transfer = NULL;
 566         struct pipe_box box;
 567         uint8_t *map = NULL;
 568
 569         u_box_1d(offset, size, &box);
 570         map = r600_buffer_transfer_map(ctx, buffer, 0,
 571                                        PIPE_TRANSFER_WRITE |
 572                                        PIPE_TRANSFER_DISCARD_RANGE |
 573                                        usage,
 574                                        &box, &transfer);
 575         if (!map)
 576                 return;
 577
 578         memcpy(map, data, size);
 579         r600_buffer_transfer_unmap(ctx, transfer);
 580 }
 581
 582 static const struct u_resource_vtbl r600_buffer_vtbl =
 583 {
 584         NULL,                           /* get_handle */
 585         r600_buffer_destroy,            /* resource_destroy */
 586         r600_buffer_transfer_map,       /* transfer_map */
 587         r600_buffer_flush_region,       /* transfer_flush_region */
 588         r600_buffer_transfer_unmap,     /* transfer_unmap */
 589 };
 590
 591 static struct r600_resource *
 592 r600_alloc_buffer_struct(struct pipe_screen *screen,
 593                          const struct pipe_resource *templ)
 594 {
 595         struct r600_resource *rbuffer;
 596
 597         rbuffer = MALLOC_STRUCT(r600_resource);
 598
 599         rbuffer->b.b = *templ;
 600         rbuffer->b.b.next = NULL;
 601         pipe_reference_init(&rbuffer->b.b.reference, 1);
 602         rbuffer->b.b.screen = screen;
 603
 604         rbuffer->b.vtbl = &r600_buffer_vtbl;
 605         threaded_resource_init(&rbuffer->b.b);
 606
 607         rbuffer->buf = NULL;
 608         rbuffer->bind_history = 0;
 609         rbuffer->TC_L2_dirty = false;
 610         util_range_init(&rbuffer->valid_buffer_range);
 611         return rbuffer;
 612 }
 613
 614 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 615                                        const struct pipe_resource *templ,
 616                                        unsigned alignment)
 617 {
 618         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 619         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 620
 621         si_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
 622
 623         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 624                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 625
 626         if (!si_alloc_resource(rscreen, rbuffer)) {
 627                 FREE(rbuffer);
 628                 return NULL;
 629         }
 630         return &rbuffer->b.b;
 631 }
 632
 633 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 634                                                unsigned flags,
 635                                                unsigned usage,
 636                                                unsigned size,
 637                                                unsigned alignment)
 638 {
 639         struct pipe_resource buffer;
 640
 641         memset(&buffer, 0, sizeof buffer);
 642         buffer.target = PIPE_BUFFER;
 643         buffer.format = PIPE_FORMAT_R8_UNORM;
 644         buffer.bind = 0;
 645         buffer.usage = usage;
 646         buffer.flags = flags;
 647         buffer.width0 = size;
 648         buffer.height0 = 1;
 649         buffer.depth0 = 1;
 650         buffer.array_size = 1;
 651         return si_buffer_create(screen, &buffer, alignment);
 652 }
 653
 654 struct pipe_resource *
 655 si_buffer_from_user_memory(struct pipe_screen *screen,
 656                            const struct pipe_resource *templ,
 657                            void *user_memory)
 658 {
 659         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 660         struct radeon_winsys *ws = rscreen->ws;
 661         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 662
 663         rbuffer->domains = RADEON_DOMAIN_GTT;
 664         rbuffer->flags = 0;
 665         rbuffer->b.is_user_ptr = true;
 666         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 667         util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
 668
 669         /* Convert a user pointer to a buffer. */
 670         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 671         if (!rbuffer->buf) {
 672                 FREE(rbuffer);
 673                 return NULL;
 674         }
 675
 676         if (rscreen->info.has_virtual_memory)
 677                 rbuffer->gpu_address =
 678                         ws->buffer_get_virtual_address(rbuffer->buf);
 679         else
 680                 rbuffer->gpu_address = 0;
 681
 682         rbuffer->vram_usage = 0;
 683         rbuffer->gart_usage = templ->width0;
 684
 685         return &rbuffer->b.b;
 686 }