2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_memory.h"
26 #include "util/u_upload_mgr.h"
30 bool si_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
31 struct pb_buffer
*buf
,
32 enum radeon_bo_usage usage
)
34 if (ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, buf
, usage
)) {
37 if (radeon_emitted(ctx
->dma
.cs
, 0) &&
38 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, buf
, usage
)) {
44 void *si_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
45 struct r600_resource
*resource
,
48 enum radeon_bo_usage rusage
= RADEON_USAGE_READWRITE
;
51 assert(!(resource
->flags
& RADEON_FLAG_SPARSE
));
53 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
54 return ctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
57 if (!(usage
& PIPE_TRANSFER_WRITE
)) {
58 /* have to wait for the last write */
59 rusage
= RADEON_USAGE_WRITE
;
62 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
63 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
,
64 resource
->buf
, rusage
)) {
65 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
66 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
69 ctx
->gfx
.flush(ctx
, 0, NULL
);
73 if (radeon_emitted(ctx
->dma
.cs
, 0) &&
74 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
,
75 resource
->buf
, rusage
)) {
76 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
77 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
80 ctx
->dma
.flush(ctx
, 0, NULL
);
85 if (busy
|| !ctx
->ws
->buffer_wait(resource
->buf
, 0, rusage
)) {
86 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
89 /* We will be wait for the GPU. Wait for any offloaded
90 * CS flush to complete to avoid busy-waiting in the winsys. */
91 ctx
->ws
->cs_sync_flush(ctx
->gfx
.cs
);
93 ctx
->ws
->cs_sync_flush(ctx
->dma
.cs
);
97 /* Setting the CS to NULL will prevent doing checks we have done already. */
98 return ctx
->ws
->buffer_map(resource
->buf
, NULL
, usage
);
101 void si_init_resource_fields(struct r600_common_screen
*rscreen
,
102 struct r600_resource
*res
,
103 uint64_t size
, unsigned alignment
)
105 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
108 res
->bo_alignment
= alignment
;
110 res
->texture_handle_allocated
= false;
111 res
->image_handle_allocated
= false;
113 switch (res
->b
.b
.usage
) {
114 case PIPE_USAGE_STREAM
:
115 res
->flags
= RADEON_FLAG_GTT_WC
;
117 case PIPE_USAGE_STAGING
:
118 /* Transfers are likely to occur more often with these
120 res
->domains
= RADEON_DOMAIN_GTT
;
122 case PIPE_USAGE_DYNAMIC
:
123 /* Older kernels didn't always flush the HDP cache before
126 if (rscreen
->info
.drm_major
== 2 &&
127 rscreen
->info
.drm_minor
< 40) {
128 res
->domains
= RADEON_DOMAIN_GTT
;
129 res
->flags
|= RADEON_FLAG_GTT_WC
;
133 case PIPE_USAGE_DEFAULT
:
134 case PIPE_USAGE_IMMUTABLE
:
136 /* Not listing GTT here improves performance in some
138 res
->domains
= RADEON_DOMAIN_VRAM
;
139 res
->flags
|= RADEON_FLAG_GTT_WC
;
143 if (res
->b
.b
.target
== PIPE_BUFFER
&&
144 res
->b
.b
.flags
& (PIPE_RESOURCE_FLAG_MAP_PERSISTENT
|
145 PIPE_RESOURCE_FLAG_MAP_COHERENT
)) {
146 /* Use GTT for all persistent mappings with older
147 * kernels, because they didn't always flush the HDP
148 * cache before CS execution.
150 * Write-combined CPU mappings are fine, the kernel
151 * ensures all CPU writes finish before the GPU
152 * executes a command stream.
154 if (rscreen
->info
.drm_major
== 2 &&
155 rscreen
->info
.drm_minor
< 40)
156 res
->domains
= RADEON_DOMAIN_GTT
;
159 /* Tiled textures are unmappable. Always put them in VRAM. */
160 if ((res
->b
.b
.target
!= PIPE_BUFFER
&& !rtex
->surface
.is_linear
) ||
161 res
->flags
& R600_RESOURCE_FLAG_UNMAPPABLE
) {
162 res
->domains
= RADEON_DOMAIN_VRAM
;
163 res
->flags
|= RADEON_FLAG_NO_CPU_ACCESS
|
167 /* Displayable and shareable surfaces are not suballocated. */
168 if (res
->b
.b
.bind
& (PIPE_BIND_SHARED
| PIPE_BIND_SCANOUT
))
169 res
->flags
|= RADEON_FLAG_NO_SUBALLOC
; /* shareable */
171 res
->flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
173 /* If VRAM is just stolen system memory, allow both VRAM and
174 * GTT, whichever has free space. If a buffer is evicted from
175 * VRAM to GTT, it will stay there.
177 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
178 * placements even with a low amount of stolen VRAM.
180 if (!rscreen
->info
.has_dedicated_vram
&&
181 (rscreen
->info
.drm_major
< 3 || rscreen
->info
.drm_minor
< 6) &&
182 res
->domains
== RADEON_DOMAIN_VRAM
) {
183 res
->domains
= RADEON_DOMAIN_VRAM_GTT
;
184 res
->flags
&= ~RADEON_FLAG_NO_CPU_ACCESS
; /* disallowed with VRAM_GTT */
187 if (rscreen
->debug_flags
& DBG(NO_WC
))
188 res
->flags
&= ~RADEON_FLAG_GTT_WC
;
190 /* Set expected VRAM and GART usage for the buffer. */
194 if (res
->domains
& RADEON_DOMAIN_VRAM
) {
195 res
->vram_usage
= size
;
197 res
->max_forced_staging_uploads
=
198 res
->b
.max_forced_staging_uploads
=
199 rscreen
->info
.has_dedicated_vram
&&
200 size
>= rscreen
->info
.vram_vis_size
/ 4 ? 1 : 0;
201 } else if (res
->domains
& RADEON_DOMAIN_GTT
) {
202 res
->gart_usage
= size
;
206 bool si_alloc_resource(struct r600_common_screen
*rscreen
,
207 struct r600_resource
*res
)
209 struct pb_buffer
*old_buf
, *new_buf
;
211 /* Allocate a new resource. */
212 new_buf
= rscreen
->ws
->buffer_create(rscreen
->ws
, res
->bo_size
,
214 res
->domains
, res
->flags
);
219 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
220 * NULL. This should prevent crashes with multiple contexts using
221 * the same buffer where one of the contexts invalidates it while
222 * the others are using it. */
224 res
->buf
= new_buf
; /* should be atomic */
226 if (rscreen
->info
.has_virtual_memory
)
227 res
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(res
->buf
);
229 res
->gpu_address
= 0;
231 pb_reference(&old_buf
, NULL
);
233 util_range_set_empty(&res
->valid_buffer_range
);
234 res
->TC_L2_dirty
= false;
236 /* Print debug information. */
237 if (rscreen
->debug_flags
& DBG(VM
) && res
->b
.b
.target
== PIPE_BUFFER
) {
238 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Buffer %"PRIu64
" bytes\n",
239 res
->gpu_address
, res
->gpu_address
+ res
->buf
->size
,
245 static void r600_buffer_destroy(struct pipe_screen
*screen
,
246 struct pipe_resource
*buf
)
248 struct r600_resource
*rbuffer
= r600_resource(buf
);
250 threaded_resource_deinit(buf
);
251 util_range_destroy(&rbuffer
->valid_buffer_range
);
252 pb_reference(&rbuffer
->buf
, NULL
);
257 r600_invalidate_buffer(struct r600_common_context
*rctx
,
258 struct r600_resource
*rbuffer
)
260 /* Shared buffers can't be reallocated. */
261 if (rbuffer
->b
.is_shared
)
264 /* Sparse buffers can't be reallocated. */
265 if (rbuffer
->flags
& RADEON_FLAG_SPARSE
)
268 /* In AMD_pinned_memory, the user pointer association only gets
269 * broken when the buffer is explicitly re-allocated.
271 if (rbuffer
->b
.is_user_ptr
)
274 /* Check if mapping this buffer would cause waiting for the GPU. */
275 if (si_rings_is_buffer_referenced(rctx
, rbuffer
->buf
, RADEON_USAGE_READWRITE
) ||
276 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
277 rctx
->invalidate_buffer(&rctx
->b
, &rbuffer
->b
.b
);
279 util_range_set_empty(&rbuffer
->valid_buffer_range
);
285 /* Replace the storage of dst with src. */
286 void si_replace_buffer_storage(struct pipe_context
*ctx
,
287 struct pipe_resource
*dst
,
288 struct pipe_resource
*src
)
290 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
291 struct r600_resource
*rdst
= r600_resource(dst
);
292 struct r600_resource
*rsrc
= r600_resource(src
);
293 uint64_t old_gpu_address
= rdst
->gpu_address
;
295 pb_reference(&rdst
->buf
, rsrc
->buf
);
296 rdst
->gpu_address
= rsrc
->gpu_address
;
297 rdst
->b
.b
.bind
= rsrc
->b
.b
.bind
;
298 rdst
->b
.max_forced_staging_uploads
= rsrc
->b
.max_forced_staging_uploads
;
299 rdst
->max_forced_staging_uploads
= rsrc
->max_forced_staging_uploads
;
300 rdst
->flags
= rsrc
->flags
;
302 assert(rdst
->vram_usage
== rsrc
->vram_usage
);
303 assert(rdst
->gart_usage
== rsrc
->gart_usage
);
304 assert(rdst
->bo_size
== rsrc
->bo_size
);
305 assert(rdst
->bo_alignment
== rsrc
->bo_alignment
);
306 assert(rdst
->domains
== rsrc
->domains
);
308 rctx
->rebind_buffer(ctx
, dst
, old_gpu_address
);
311 void si_invalidate_resource(struct pipe_context
*ctx
,
312 struct pipe_resource
*resource
)
314 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
315 struct r600_resource
*rbuffer
= r600_resource(resource
);
317 /* We currently only do anyting here for buffers */
318 if (resource
->target
== PIPE_BUFFER
)
319 (void)r600_invalidate_buffer(rctx
, rbuffer
);
322 static void *r600_buffer_get_transfer(struct pipe_context
*ctx
,
323 struct pipe_resource
*resource
,
325 const struct pipe_box
*box
,
326 struct pipe_transfer
**ptransfer
,
327 void *data
, struct r600_resource
*staging
,
330 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
331 struct r600_transfer
*transfer
;
333 if (usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
)
334 transfer
= slab_alloc(&rctx
->pool_transfers_unsync
);
336 transfer
= slab_alloc(&rctx
->pool_transfers
);
338 transfer
->b
.b
.resource
= NULL
;
339 pipe_resource_reference(&transfer
->b
.b
.resource
, resource
);
340 transfer
->b
.b
.level
= 0;
341 transfer
->b
.b
.usage
= usage
;
342 transfer
->b
.b
.box
= *box
;
343 transfer
->b
.b
.stride
= 0;
344 transfer
->b
.b
.layer_stride
= 0;
345 transfer
->b
.staging
= NULL
;
346 transfer
->offset
= offset
;
347 transfer
->staging
= staging
;
348 *ptransfer
= &transfer
->b
.b
;
352 static void *r600_buffer_transfer_map(struct pipe_context
*ctx
,
353 struct pipe_resource
*resource
,
356 const struct pipe_box
*box
,
357 struct pipe_transfer
**ptransfer
)
359 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
360 struct r600_resource
*rbuffer
= r600_resource(resource
);
363 assert(box
->x
+ box
->width
<= resource
->width0
);
365 /* From GL_AMD_pinned_memory issues:
367 * 4) Is glMapBuffer on a shared buffer guaranteed to return the
368 * same system address which was specified at creation time?
370 * RESOLVED: NO. The GL implementation might return a different
371 * virtual mapping of that memory, although the same physical
374 * So don't ever use staging buffers.
376 if (rbuffer
->b
.is_user_ptr
)
377 usage
|= PIPE_TRANSFER_PERSISTENT
;
379 /* See if the buffer range being mapped has never been initialized,
380 * in which case it can be mapped unsynchronized. */
381 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
382 TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
)) &&
383 usage
& PIPE_TRANSFER_WRITE
&&
384 !rbuffer
->b
.is_shared
&&
385 !util_ranges_intersect(&rbuffer
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
)) {
386 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
389 /* If discarding the entire range, discard the whole resource instead. */
390 if (usage
& PIPE_TRANSFER_DISCARD_RANGE
&&
391 box
->x
== 0 && box
->width
== resource
->width0
) {
392 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
395 /* If a buffer in VRAM is too large and the range is discarded, don't
396 * map it directly. This makes sure that the buffer stays in VRAM.
398 bool force_discard_range
= false;
399 if (usage
& (PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
400 PIPE_TRANSFER_DISCARD_RANGE
) &&
401 !(usage
& PIPE_TRANSFER_PERSISTENT
) &&
402 /* Try not to decrement the counter if it's not positive. Still racy,
403 * but it makes it harder to wrap the counter from INT_MIN to INT_MAX. */
404 rbuffer
->max_forced_staging_uploads
> 0 &&
405 p_atomic_dec_return(&rbuffer
->max_forced_staging_uploads
) >= 0) {
406 usage
&= ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
|
407 PIPE_TRANSFER_UNSYNCHRONIZED
);
408 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
409 force_discard_range
= true;
412 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
&&
413 !(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
414 TC_TRANSFER_MAP_NO_INVALIDATE
))) {
415 assert(usage
& PIPE_TRANSFER_WRITE
);
417 if (r600_invalidate_buffer(rctx
, rbuffer
)) {
418 /* At this point, the buffer is always idle. */
419 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
421 /* Fall back to a temporary buffer. */
422 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
426 if ((usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
427 ((!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
428 PIPE_TRANSFER_PERSISTENT
))) ||
429 (rbuffer
->flags
& RADEON_FLAG_SPARSE
))) {
430 assert(usage
& PIPE_TRANSFER_WRITE
);
432 /* Check if mapping this buffer would cause waiting for the GPU.
434 if (rbuffer
->flags
& RADEON_FLAG_SPARSE
||
435 force_discard_range
||
436 si_rings_is_buffer_referenced(rctx
, rbuffer
->buf
, RADEON_USAGE_READWRITE
) ||
437 !rctx
->ws
->buffer_wait(rbuffer
->buf
, 0, RADEON_USAGE_READWRITE
)) {
438 /* Do a wait-free write-only transfer using a temporary buffer. */
440 struct r600_resource
*staging
= NULL
;
442 u_upload_alloc(ctx
->stream_uploader
, 0,
443 box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
),
444 rctx
->screen
->info
.tcc_cache_line_size
,
445 &offset
, (struct pipe_resource
**)&staging
,
449 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
450 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
451 ptransfer
, data
, staging
, offset
);
452 } else if (rbuffer
->flags
& RADEON_FLAG_SPARSE
) {
456 /* At this point, the buffer is always idle (we checked it above). */
457 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
460 /* Use a staging buffer in cached GTT for reads. */
461 else if (((usage
& PIPE_TRANSFER_READ
) &&
462 !(usage
& PIPE_TRANSFER_PERSISTENT
) &&
463 (rbuffer
->domains
& RADEON_DOMAIN_VRAM
||
464 rbuffer
->flags
& RADEON_FLAG_GTT_WC
)) ||
465 (rbuffer
->flags
& RADEON_FLAG_SPARSE
)) {
466 struct r600_resource
*staging
;
468 assert(!(usage
& TC_TRANSFER_MAP_THREADED_UNSYNC
));
469 staging
= (struct r600_resource
*) pipe_buffer_create(
470 ctx
->screen
, 0, PIPE_USAGE_STAGING
,
471 box
->width
+ (box
->x
% R600_MAP_BUFFER_ALIGNMENT
));
473 /* Copy the VRAM buffer to the staging buffer. */
474 rctx
->dma_copy(ctx
, &staging
->b
.b
, 0,
475 box
->x
% R600_MAP_BUFFER_ALIGNMENT
,
476 0, 0, resource
, 0, box
);
478 data
= si_buffer_map_sync_with_rings(rctx
, staging
,
479 usage
& ~PIPE_TRANSFER_UNSYNCHRONIZED
);
481 r600_resource_reference(&staging
, NULL
);
484 data
+= box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
486 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
487 ptransfer
, data
, staging
, 0);
488 } else if (rbuffer
->flags
& RADEON_FLAG_SPARSE
) {
493 data
= si_buffer_map_sync_with_rings(rctx
, rbuffer
, usage
);
499 return r600_buffer_get_transfer(ctx
, resource
, usage
, box
,
500 ptransfer
, data
, NULL
, 0);
503 static void r600_buffer_do_flush_region(struct pipe_context
*ctx
,
504 struct pipe_transfer
*transfer
,
505 const struct pipe_box
*box
)
507 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
508 struct r600_resource
*rbuffer
= r600_resource(transfer
->resource
);
510 if (rtransfer
->staging
) {
511 struct pipe_resource
*dst
, *src
;
513 struct pipe_box dma_box
;
515 dst
= transfer
->resource
;
516 src
= &rtransfer
->staging
->b
.b
;
517 soffset
= rtransfer
->offset
+ box
->x
% R600_MAP_BUFFER_ALIGNMENT
;
519 u_box_1d(soffset
, box
->width
, &dma_box
);
521 /* Copy the staging buffer into the original one. */
522 ctx
->resource_copy_region(ctx
, dst
, 0, box
->x
, 0, 0, src
, 0, &dma_box
);
525 util_range_add(&rbuffer
->valid_buffer_range
, box
->x
,
526 box
->x
+ box
->width
);
529 static void r600_buffer_flush_region(struct pipe_context
*ctx
,
530 struct pipe_transfer
*transfer
,
531 const struct pipe_box
*rel_box
)
533 unsigned required_usage
= PIPE_TRANSFER_WRITE
|
534 PIPE_TRANSFER_FLUSH_EXPLICIT
;
536 if ((transfer
->usage
& required_usage
) == required_usage
) {
539 u_box_1d(transfer
->box
.x
+ rel_box
->x
, rel_box
->width
, &box
);
540 r600_buffer_do_flush_region(ctx
, transfer
, &box
);
544 static void r600_buffer_transfer_unmap(struct pipe_context
*ctx
,
545 struct pipe_transfer
*transfer
)
547 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
548 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
550 if (transfer
->usage
& PIPE_TRANSFER_WRITE
&&
551 !(transfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
))
552 r600_buffer_do_flush_region(ctx
, transfer
, &transfer
->box
);
554 r600_resource_reference(&rtransfer
->staging
, NULL
);
555 assert(rtransfer
->b
.staging
== NULL
); /* for threaded context only */
556 pipe_resource_reference(&transfer
->resource
, NULL
);
558 /* Don't use pool_transfers_unsync. We are always in the driver
560 slab_free(&rctx
->pool_transfers
, transfer
);
563 void si_buffer_subdata(struct pipe_context
*ctx
,
564 struct pipe_resource
*buffer
,
565 unsigned usage
, unsigned offset
,
566 unsigned size
, const void *data
)
568 struct pipe_transfer
*transfer
= NULL
;
572 u_box_1d(offset
, size
, &box
);
573 map
= r600_buffer_transfer_map(ctx
, buffer
, 0,
574 PIPE_TRANSFER_WRITE
|
575 PIPE_TRANSFER_DISCARD_RANGE
|
581 memcpy(map
, data
, size
);
582 r600_buffer_transfer_unmap(ctx
, transfer
);
585 static const struct u_resource_vtbl r600_buffer_vtbl
=
587 NULL
, /* get_handle */
588 r600_buffer_destroy
, /* resource_destroy */
589 r600_buffer_transfer_map
, /* transfer_map */
590 r600_buffer_flush_region
, /* transfer_flush_region */
591 r600_buffer_transfer_unmap
, /* transfer_unmap */
594 static struct r600_resource
*
595 r600_alloc_buffer_struct(struct pipe_screen
*screen
,
596 const struct pipe_resource
*templ
)
598 struct r600_resource
*rbuffer
;
600 rbuffer
= MALLOC_STRUCT(r600_resource
);
602 rbuffer
->b
.b
= *templ
;
603 rbuffer
->b
.b
.next
= NULL
;
604 pipe_reference_init(&rbuffer
->b
.b
.reference
, 1);
605 rbuffer
->b
.b
.screen
= screen
;
607 rbuffer
->b
.vtbl
= &r600_buffer_vtbl
;
608 threaded_resource_init(&rbuffer
->b
.b
);
611 rbuffer
->bind_history
= 0;
612 rbuffer
->TC_L2_dirty
= false;
613 util_range_init(&rbuffer
->valid_buffer_range
);
617 struct pipe_resource
*si_buffer_create(struct pipe_screen
*screen
,
618 const struct pipe_resource
*templ
,
621 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
622 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
624 si_init_resource_fields(rscreen
, rbuffer
, templ
->width0
, alignment
);
626 if (templ
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
627 rbuffer
->flags
|= RADEON_FLAG_SPARSE
;
629 if (!si_alloc_resource(rscreen
, rbuffer
)) {
633 return &rbuffer
->b
.b
;
636 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
642 struct pipe_resource buffer
;
644 memset(&buffer
, 0, sizeof buffer
);
645 buffer
.target
= PIPE_BUFFER
;
646 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
648 buffer
.usage
= usage
;
649 buffer
.flags
= flags
;
650 buffer
.width0
= size
;
653 buffer
.array_size
= 1;
654 return si_buffer_create(screen
, &buffer
, alignment
);
657 struct pipe_resource
*
658 si_buffer_from_user_memory(struct pipe_screen
*screen
,
659 const struct pipe_resource
*templ
,
662 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
663 struct radeon_winsys
*ws
= rscreen
->ws
;
664 struct r600_resource
*rbuffer
= r600_alloc_buffer_struct(screen
, templ
);
666 rbuffer
->domains
= RADEON_DOMAIN_GTT
;
668 rbuffer
->b
.is_user_ptr
= true;
669 util_range_add(&rbuffer
->valid_buffer_range
, 0, templ
->width0
);
670 util_range_add(&rbuffer
->b
.valid_buffer_range
, 0, templ
->width0
);
672 /* Convert a user pointer to a buffer. */
673 rbuffer
->buf
= ws
->buffer_from_ptr(ws
, user_memory
, templ
->width0
);
679 if (rscreen
->info
.has_virtual_memory
)
680 rbuffer
->gpu_address
=
681 ws
->buffer_get_virtual_address(rbuffer
->buf
);
683 rbuffer
->gpu_address
= 0;
685 rbuffer
->vram_usage
= 0;
686 rbuffer
->gart_usage
= templ
->width0
;
688 return &rbuffer
->b
.b
;