src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                         struct radeon_winsys_cs_handle *buf,
  35                                         enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
  38                 return TRUE;
  39         }
  40         if (ctx->rings.dma.cs && ctx->rings.dma.cs->cdw &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
  42                 return TRUE;
  43         }
  44         return FALSE;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  55                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
  56         }
  57
  58         if (!(usage & PIPE_TRANSFER_WRITE)) {
  59                 /* have to wait for the last write */
  60                 rusage = RADEON_USAGE_WRITE;
  61         }
  62
  63         if (ctx->rings.gfx.cs->cdw != ctx->initial_gfx_cs_size &&
  64             ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs,
  65                                              resource->cs_buf, rusage)) {
  66                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  67                         ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  68                         return NULL;
  69                 } else {
  70                         ctx->rings.gfx.flush(ctx, 0, NULL);
  71                         busy = true;
  72                 }
  73         }
  74         if (ctx->rings.dma.cs &&
  75             ctx->rings.dma.cs->cdw &&
  76             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs,
  77                                              resource->cs_buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  80                         return NULL;
  81                 } else {
  82                         ctx->rings.dma.flush(ctx, 0, NULL);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || ctx->ws->buffer_is_busy(resource->buf, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
  94                         if (ctx->rings.dma.cs)
  95                                 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
 101 }
 102
 103 bool r600_init_resource(struct r600_common_screen *rscreen,
 104                         struct r600_resource *res,
 105                         unsigned size, unsigned alignment,
 106                         bool use_reusable_pool)
 107 {
 108         struct r600_texture *rtex = (struct r600_texture*)res;
 109         struct pb_buffer *old_buf, *new_buf;
 110
 111         switch (res->b.b.usage) {
 112         case PIPE_USAGE_STAGING:
 113         case PIPE_USAGE_DYNAMIC:
 114         case PIPE_USAGE_STREAM:
 115                 /* Transfers are likely to occur more often with these resources. */
 116                 res->domains = RADEON_DOMAIN_GTT;
 117                 break;
 118         case PIPE_USAGE_DEFAULT:
 119         case PIPE_USAGE_IMMUTABLE:
 120         default:
 121                 /* Not listing GTT here improves performance in some apps. */
 122                 res->domains = RADEON_DOMAIN_VRAM;
 123                 break;
 124         }
 125
 126         /* Use GTT for all persistent mappings, because they are
 127          * always cached and coherent. */
 128         if (res->b.b.target == PIPE_BUFFER &&
 129             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 130                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 131                 res->domains = RADEON_DOMAIN_GTT;
 132         }
 133
 134         /* Tiled textures are unmappable. Always put them in VRAM. */
 135         if (res->b.b.target != PIPE_BUFFER &&
 136             rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
 137                 res->domains = RADEON_DOMAIN_VRAM;
 138         }
 139
 140         /* Allocate a new resource. */
 141         new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
 142                                              use_reusable_pool,
 143                                              res->domains);
 144         if (!new_buf) {
 145                 return false;
 146         }
 147
 148         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 149          * NULL. This should prevent crashes with multiple contexts using
 150          * the same buffer where one of the contexts invalidates it while
 151          * the others are using it. */
 152         old_buf = res->buf;
 153         res->cs_buf = rscreen->ws->buffer_get_cs_handle(new_buf); /* should be atomic */
 154         res->buf = new_buf; /* should be atomic */
 155         pb_reference(&old_buf, NULL);
 156
 157         util_range_set_empty(&res->valid_buffer_range);
 158
 159         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 160                 fprintf(stderr, "VM start=0x%"PRIu64"  end=0x%"PRIu64" | Buffer %u bytes\n",
 161                         r600_resource_va(&rscreen->b, &res->b.b),
 162                         r600_resource_va(&rscreen->b, &res->b.b) + res->buf->size,
 163                         res->buf->size);
 164         }
 165         return true;
 166 }
 167
 168 static void r600_buffer_destroy(struct pipe_screen *screen,
 169                                 struct pipe_resource *buf)
 170 {
 171         struct r600_resource *rbuffer = r600_resource(buf);
 172
 173         util_range_destroy(&rbuffer->valid_buffer_range);
 174         pb_reference(&rbuffer->buf, NULL);
 175         FREE(rbuffer);
 176 }
 177
 178 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 179                                       struct pipe_resource *resource,
 180                                       unsigned level,
 181                                       unsigned usage,
 182                                       const struct pipe_box *box,
 183                                       struct pipe_transfer **ptransfer,
 184                                       void *data, struct r600_resource *staging,
 185                                       unsigned offset)
 186 {
 187         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 188         struct r600_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
 189
 190         transfer->transfer.resource = resource;
 191         transfer->transfer.level = level;
 192         transfer->transfer.usage = usage;
 193         transfer->transfer.box = *box;
 194         transfer->transfer.stride = 0;
 195         transfer->transfer.layer_stride = 0;
 196         transfer->offset = offset;
 197         transfer->staging = staging;
 198         *ptransfer = &transfer->transfer;
 199         return data;
 200 }
 201
 202 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 203                                      unsigned dstx, unsigned srcx, unsigned size)
 204 {
 205         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 206
 207         return rctx->screen->has_cp_dma ||
 208                (dword_aligned && (rctx->rings.dma.cs ||
 209                                   rctx->screen->has_streamout));
 210
 211 }
 212
 213 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 214                                       struct pipe_resource *resource,
 215                                       unsigned level,
 216                                       unsigned usage,
 217                                       const struct pipe_box *box,
 218                                       struct pipe_transfer **ptransfer)
 219 {
 220         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 221         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 222         struct r600_resource *rbuffer = r600_resource(resource);
 223         uint8_t *data;
 224
 225         assert(box->x + box->width <= resource->width0);
 226
 227         /* See if the buffer range being mapped has never been initialized,
 228          * in which case it can be mapped unsynchronized. */
 229         if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 230             usage & PIPE_TRANSFER_WRITE &&
 231             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 232                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 233         }
 234
 235         /* If discarding the entire range, discard the whole resource instead. */
 236         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 237             box->x == 0 && box->width == resource->width0) {
 238                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 239         }
 240
 241         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 242             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 243                 assert(usage & PIPE_TRANSFER_WRITE);
 244
 245                 /* Check if mapping this buffer would cause waiting for the GPU. */
 246                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 247                     rctx->ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
 248                         rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 249                 }
 250                 /* At this point, the buffer is always idle. */
 251                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 252         }
 253         else if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 254                  !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 255                  !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 256                  r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) {
 257                 assert(usage & PIPE_TRANSFER_WRITE);
 258
 259                 /* Check if mapping this buffer would cause waiting for the GPU. */
 260                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 261                     rctx->ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
 262                         /* Do a wait-free write-only transfer using a temporary buffer. */
 263                         unsigned offset;
 264                         struct r600_resource *staging = NULL;
 265
 266                         u_upload_alloc(rctx->uploader, 0, box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 267                                        &offset, (struct pipe_resource**)&staging, (void**)&data);
 268
 269                         if (staging) {
 270                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 271                                 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 272                                                                 ptransfer, data, staging, offset);
 273                         } else {
 274                                 return NULL; /* error, shouldn't occur though */
 275                         }
 276                 }
 277                 /* At this point, the buffer is always idle (we checked it above). */
 278                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 279         }
 280         /* Using a staging buffer in GTT for larger reads is much faster. */
 281         else if ((usage & PIPE_TRANSFER_READ) &&
 282                  !(usage & PIPE_TRANSFER_WRITE) &&
 283                  rbuffer->domains == RADEON_DOMAIN_VRAM &&
 284                  r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) {
 285                 unsigned offset;
 286                 struct r600_resource *staging = NULL;
 287
 288                 u_upload_alloc(rctx->uploader, 0,
 289                                box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 290                                &offset, (struct pipe_resource**)&staging, (void**)&data);
 291
 292                 if (staging) {
 293                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 294
 295                         /* Copy the VRAM buffer to the staging buffer. */
 296                         rctx->dma_copy(ctx, &staging->b.b, 0,
 297                                        offset + box->x % R600_MAP_BUFFER_ALIGNMENT,
 298                                        0, 0, resource, level, box);
 299
 300                         /* Just do the synchronization. The buffer is mapped already. */
 301                         r600_buffer_map_sync_with_rings(rctx, staging, PIPE_TRANSFER_READ);
 302
 303                         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 304                                                         ptransfer, data, staging, offset);
 305                 }
 306         }
 307
 308         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 309         if (!data) {
 310                 return NULL;
 311         }
 312         data += box->x;
 313
 314         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 315                                         ptransfer, data, NULL, 0);
 316 }
 317
 318 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 319                                        struct pipe_transfer *transfer)
 320 {
 321         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 322         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 323         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 324
 325         if (rtransfer->staging) {
 326                 if (rtransfer->transfer.usage & PIPE_TRANSFER_WRITE) {
 327                         struct pipe_resource *dst, *src;
 328                         unsigned soffset, doffset, size;
 329                         struct pipe_box box;
 330
 331                         dst = transfer->resource;
 332                         src = &rtransfer->staging->b.b;
 333                         size = transfer->box.width;
 334                         doffset = transfer->box.x;
 335                         soffset = rtransfer->offset + transfer->box.x % R600_MAP_BUFFER_ALIGNMENT;
 336
 337                         u_box_1d(soffset, size, &box);
 338
 339                         /* Copy the staging buffer into the original one. */
 340                         rctx->dma_copy(ctx, dst, 0, doffset, 0, 0, src, 0, &box);
 341                 }
 342                 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
 343         }
 344
 345         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 346                 util_range_add(&rbuffer->valid_buffer_range, transfer->box.x,
 347                                transfer->box.x + transfer->box.width);
 348         }
 349         util_slab_free(&rctx->pool_transfers, transfer);
 350 }
 351
 352 static const struct u_resource_vtbl r600_buffer_vtbl =
 353 {
 354         NULL,                           /* get_handle */
 355         r600_buffer_destroy,            /* resource_destroy */
 356         r600_buffer_transfer_map,       /* transfer_map */
 357         NULL,                           /* transfer_flush_region */
 358         r600_buffer_transfer_unmap,     /* transfer_unmap */
 359         NULL                            /* transfer_inline_write */
 360 };
 361
 362 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 363                                          const struct pipe_resource *templ,
 364                                          unsigned alignment)
 365 {
 366         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 367         struct r600_resource *rbuffer;
 368
 369         rbuffer = MALLOC_STRUCT(r600_resource);
 370
 371         rbuffer->b.b = *templ;
 372         pipe_reference_init(&rbuffer->b.b.reference, 1);
 373         rbuffer->b.b.screen = screen;
 374         rbuffer->b.vtbl = &r600_buffer_vtbl;
 375         rbuffer->buf = NULL;
 376         util_range_init(&rbuffer->valid_buffer_range);
 377
 378         if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE)) {
 379                 FREE(rbuffer);
 380                 return NULL;
 381         }
 382         return &rbuffer->b.b;
 383 }