src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                      struct pb_buffer *buf,
  35                                      enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  38                 return true;
  39         }
  40         if (radeon_emitted(ctx->dma.cs, 0) &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  42                 return true;
  43         }
  44         return false;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  55                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  56         }
  57
  58         if (!(usage & PIPE_TRANSFER_WRITE)) {
  59                 /* have to wait for the last write */
  60                 rusage = RADEON_USAGE_WRITE;
  61         }
  62
  63         if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
  64             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  65                                              resource->buf, rusage)) {
  66                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  67                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  68                         return NULL;
  69                 } else {
  70                         ctx->gfx.flush(ctx, 0, NULL);
  71                         busy = true;
  72                 }
  73         }
  74         if (radeon_emitted(ctx->dma.cs, 0) &&
  75             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  76                                              resource->buf, rusage)) {
  77                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  78                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  79                         return NULL;
  80                 } else {
  81                         ctx->dma.flush(ctx, 0, NULL);
  82                         busy = true;
  83                 }
  84         }
  85
  86         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  87                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  88                         return NULL;
  89                 } else {
  90                         /* We will be wait for the GPU. Wait for any offloaded
  91                          * CS flush to complete to avoid busy-waiting in the winsys. */
  92                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  93                         if (ctx->dma.cs)
  94                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  95                 }
  96         }
  97
  98         /* Setting the CS to NULL will prevent doing checks we have done already. */
  99         return ctx->ws->buffer_map(resource->buf, NULL, usage);
 100 }
 101
 102 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 103                                struct r600_resource *res,
 104                                uint64_t size, unsigned alignment)
 105 {
 106         struct r600_texture *rtex = (struct r600_texture*)res;
 107
 108         res->bo_size = size;
 109         res->bo_alignment = alignment;
 110         res->flags = 0;
 111
 112         switch (res->b.b.usage) {
 113         case PIPE_USAGE_STREAM:
 114                 res->flags = RADEON_FLAG_GTT_WC;
 115                 /* fall through */
 116         case PIPE_USAGE_STAGING:
 117                 /* Transfers are likely to occur more often with these
 118                  * resources. */
 119                 res->domains = RADEON_DOMAIN_GTT;
 120                 break;
 121         case PIPE_USAGE_DYNAMIC:
 122                 /* Older kernels didn't always flush the HDP cache before
 123                  * CS execution
 124                  */
 125                 if (rscreen->info.drm_major == 2 &&
 126                     rscreen->info.drm_minor < 40) {
 127                         res->domains = RADEON_DOMAIN_GTT;
 128                         res->flags |= RADEON_FLAG_GTT_WC;
 129                         break;
 130                 }
 131                 res->flags |= RADEON_FLAG_CPU_ACCESS;
 132                 /* fall through */
 133         case PIPE_USAGE_DEFAULT:
 134         case PIPE_USAGE_IMMUTABLE:
 135         default:
 136                 /* Not listing GTT here improves performance in some
 137                  * apps. */
 138                 res->domains = RADEON_DOMAIN_VRAM;
 139                 res->flags |= RADEON_FLAG_GTT_WC;
 140                 break;
 141         }
 142
 143         if (res->b.b.target == PIPE_BUFFER &&
 144             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 145                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 146                 /* Use GTT for all persistent mappings with older
 147                  * kernels, because they didn't always flush the HDP
 148                  * cache before CS execution.
 149                  *
 150                  * Write-combined CPU mappings are fine, the kernel
 151                  * ensures all CPU writes finish before the GPU
 152                  * executes a command stream.
 153                  */
 154                 if (rscreen->info.drm_major == 2 &&
 155                     rscreen->info.drm_minor < 40)
 156                         res->domains = RADEON_DOMAIN_GTT;
 157                 else if (res->domains & RADEON_DOMAIN_VRAM)
 158                         res->flags |= RADEON_FLAG_CPU_ACCESS;
 159         }
 160
 161         /* Tiled textures are unmappable. Always put them in VRAM. */
 162         if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 163             res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
 164                 res->domains = RADEON_DOMAIN_VRAM;
 165                 res->flags &= ~RADEON_FLAG_CPU_ACCESS;
 166                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 167                          RADEON_FLAG_GTT_WC;
 168         }
 169
 170         /* If VRAM is just stolen system memory, allow both VRAM and
 171          * GTT, whichever has free space. If a buffer is evicted from
 172          * VRAM to GTT, it will stay there.
 173          *
 174          * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 175          * placements even with a low amount of stolen VRAM.
 176          */
 177         if (!rscreen->info.has_dedicated_vram &&
 178             (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
 179             res->domains == RADEON_DOMAIN_VRAM)
 180                 res->domains = RADEON_DOMAIN_VRAM_GTT;
 181
 182         if (rscreen->debug_flags & DBG_NO_WC)
 183                 res->flags &= ~RADEON_FLAG_GTT_WC;
 184
 185         /* Set expected VRAM and GART usage for the buffer. */
 186         res->vram_usage = 0;
 187         res->gart_usage = 0;
 188
 189         if (res->domains & RADEON_DOMAIN_VRAM)
 190                 res->vram_usage = size;
 191         else if (res->domains & RADEON_DOMAIN_GTT)
 192                 res->gart_usage = size;
 193 }
 194
 195 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 196                          struct r600_resource *res)
 197 {
 198         struct pb_buffer *old_buf, *new_buf;
 199
 200         /* Allocate a new resource. */
 201         new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
 202                                              res->bo_alignment,
 203                                              res->domains, res->flags);
 204         if (!new_buf) {
 205                 return false;
 206         }
 207
 208         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 209          * NULL. This should prevent crashes with multiple contexts using
 210          * the same buffer where one of the contexts invalidates it while
 211          * the others are using it. */
 212         old_buf = res->buf;
 213         res->buf = new_buf; /* should be atomic */
 214
 215         if (rscreen->info.has_virtual_memory)
 216                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 217         else
 218                 res->gpu_address = 0;
 219
 220         pb_reference(&old_buf, NULL);
 221
 222         util_range_set_empty(&res->valid_buffer_range);
 223         res->TC_L2_dirty = false;
 224
 225         /* Print debug information. */
 226         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 227                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 228                         res->gpu_address, res->gpu_address + res->buf->size,
 229                         res->buf->size);
 230         }
 231         return true;
 232 }
 233
 234 static void r600_buffer_destroy(struct pipe_screen *screen,
 235                                 struct pipe_resource *buf)
 236 {
 237         struct r600_resource *rbuffer = r600_resource(buf);
 238
 239         util_range_destroy(&rbuffer->valid_buffer_range);
 240         pb_reference(&rbuffer->buf, NULL);
 241         FREE(rbuffer);
 242 }
 243
 244 static bool
 245 r600_invalidate_buffer(struct r600_common_context *rctx,
 246                        struct r600_resource *rbuffer)
 247 {
 248         /* Shared buffers can't be reallocated. */
 249         if (rbuffer->is_shared)
 250                 return false;
 251
 252         /* In AMD_pinned_memory, the user pointer association only gets
 253          * broken when the buffer is explicitly re-allocated.
 254          */
 255         if (rctx->ws->buffer_is_user_ptr(rbuffer->buf))
 256                 return false;
 257
 258         /* Check if mapping this buffer would cause waiting for the GPU. */
 259         if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 260             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 261                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 262         } else {
 263                 util_range_set_empty(&rbuffer->valid_buffer_range);
 264         }
 265
 266         return true;
 267 }
 268
 269 void r600_invalidate_resource(struct pipe_context *ctx,
 270                               struct pipe_resource *resource)
 271 {
 272         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 273         struct r600_resource *rbuffer = r600_resource(resource);
 274
 275         /* We currently only do anyting here for buffers */
 276         if (resource->target == PIPE_BUFFER)
 277                 (void)r600_invalidate_buffer(rctx, rbuffer);
 278 }
 279
 280 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 281                                       struct pipe_resource *resource,
 282                                       unsigned usage,
 283                                       const struct pipe_box *box,
 284                                       struct pipe_transfer **ptransfer,
 285                                       void *data, struct r600_resource *staging,
 286                                       unsigned offset)
 287 {
 288         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 289         struct r600_transfer *transfer = slab_alloc(&rctx->pool_transfers);
 290
 291         transfer->transfer.resource = NULL;
 292         pipe_resource_reference(&transfer->transfer.resource, resource);
 293         transfer->transfer.level = 0;
 294         transfer->transfer.usage = usage;
 295         transfer->transfer.box = *box;
 296         transfer->transfer.stride = 0;
 297         transfer->transfer.layer_stride = 0;
 298         transfer->offset = offset;
 299         transfer->staging = staging;
 300         *ptransfer = &transfer->transfer;
 301         return data;
 302 }
 303
 304 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 305                                      unsigned dstx, unsigned srcx, unsigned size)
 306 {
 307         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 308
 309         return rctx->screen->has_cp_dma ||
 310                (dword_aligned && (rctx->dma.cs ||
 311                                   rctx->screen->has_streamout));
 312
 313 }
 314
 315 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 316                                       struct pipe_resource *resource,
 317                                       unsigned level,
 318                                       unsigned usage,
 319                                       const struct pipe_box *box,
 320                                       struct pipe_transfer **ptransfer)
 321 {
 322         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 323         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 324         struct r600_resource *rbuffer = r600_resource(resource);
 325         uint8_t *data;
 326
 327         assert(box->x + box->width <= resource->width0);
 328
 329         /* See if the buffer range being mapped has never been initialized,
 330          * in which case it can be mapped unsynchronized. */
 331         if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 332             usage & PIPE_TRANSFER_WRITE &&
 333             !rbuffer->is_shared &&
 334             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 335                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 336         }
 337
 338         /* If discarding the entire range, discard the whole resource instead. */
 339         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 340             box->x == 0 && box->width == resource->width0) {
 341                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 342         }
 343
 344         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 345             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 346                 assert(usage & PIPE_TRANSFER_WRITE);
 347
 348                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 349                         /* At this point, the buffer is always idle. */
 350                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 351                 } else {
 352                         /* Fall back to a temporary buffer. */
 353                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 354                 }
 355         }
 356
 357         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 358             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 359                        PIPE_TRANSFER_PERSISTENT)) &&
 360             !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 361             r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) {
 362                 assert(usage & PIPE_TRANSFER_WRITE);
 363
 364                 /* Check if mapping this buffer would cause waiting for the GPU. */
 365                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 366                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 367                         /* Do a wait-free write-only transfer using a temporary buffer. */
 368                         unsigned offset;
 369                         struct r600_resource *staging = NULL;
 370
 371                         u_upload_alloc(ctx->stream_uploader, 0,
 372                                        box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 373                                        rctx->screen->info.tcc_cache_line_size,
 374                                        &offset, (struct pipe_resource**)&staging,
 375                                        (void**)&data);
 376
 377                         if (staging) {
 378                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 379                                 return r600_buffer_get_transfer(ctx, resource, usage, box,
 380                                                                 ptransfer, data, staging, offset);
 381                         }
 382                 } else {
 383                         /* At this point, the buffer is always idle (we checked it above). */
 384                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 385                 }
 386         }
 387         /* Use a staging buffer in cached GTT for reads. */
 388         else if ((usage & PIPE_TRANSFER_READ) &&
 389                  !(usage & PIPE_TRANSFER_PERSISTENT) &&
 390                  (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 391                   rbuffer->flags & RADEON_FLAG_GTT_WC) &&
 392                  r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) {
 393                 struct r600_resource *staging;
 394
 395                 staging = (struct r600_resource*) pipe_buffer_create(
 396                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 397                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 398                 if (staging) {
 399                         /* Copy the VRAM buffer to the staging buffer. */
 400                         rctx->dma_copy(ctx, &staging->b.b, 0,
 401                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 402                                        0, 0, resource, 0, box);
 403
 404                         data = r600_buffer_map_sync_with_rings(rctx, staging,
 405                                                                usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 406                         if (!data) {
 407                                 r600_resource_reference(&staging, NULL);
 408                                 return NULL;
 409                         }
 410                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 411
 412                         return r600_buffer_get_transfer(ctx, resource, usage, box,
 413                                                         ptransfer, data, staging, 0);
 414                 }
 415         }
 416
 417         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 418         if (!data) {
 419                 return NULL;
 420         }
 421         data += box->x;
 422
 423         return r600_buffer_get_transfer(ctx, resource, usage, box,
 424                                         ptransfer, data, NULL, 0);
 425 }
 426
 427 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 428                                         struct pipe_transfer *transfer,
 429                                         const struct pipe_box *box)
 430 {
 431         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 432         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 433
 434         if (rtransfer->staging) {
 435                 struct pipe_resource *dst, *src;
 436                 unsigned soffset;
 437                 struct pipe_box dma_box;
 438
 439                 dst = transfer->resource;
 440                 src = &rtransfer->staging->b.b;
 441                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 442
 443                 u_box_1d(soffset, box->width, &dma_box);
 444
 445                 /* Copy the staging buffer into the original one. */
 446                 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 447         }
 448
 449         util_range_add(&rbuffer->valid_buffer_range, box->x,
 450                        box->x + box->width);
 451 }
 452
 453 static void r600_buffer_flush_region(struct pipe_context *ctx,
 454                                      struct pipe_transfer *transfer,
 455                                      const struct pipe_box *rel_box)
 456 {
 457         if (transfer->usage & (PIPE_TRANSFER_WRITE |
 458                                PIPE_TRANSFER_FLUSH_EXPLICIT)) {
 459                 struct pipe_box box;
 460
 461                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 462                 r600_buffer_do_flush_region(ctx, transfer, &box);
 463         }
 464 }
 465
 466 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 467                                        struct pipe_transfer *transfer)
 468 {
 469         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 470         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 471
 472         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 473             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 474                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 475
 476         if (rtransfer->staging)
 477                 r600_resource_reference(&rtransfer->staging, NULL);
 478
 479         pipe_resource_reference(&transfer->resource, NULL);
 480         slab_free(&rctx->pool_transfers, transfer);
 481 }
 482
 483 void r600_buffer_subdata(struct pipe_context *ctx,
 484                          struct pipe_resource *buffer,
 485                          unsigned usage, unsigned offset,
 486                          unsigned size, const void *data)
 487 {
 488         struct pipe_transfer *transfer = NULL;
 489         struct pipe_box box;
 490         uint8_t *map = NULL;
 491
 492         u_box_1d(offset, size, &box);
 493         map = r600_buffer_transfer_map(ctx, buffer, 0,
 494                                        PIPE_TRANSFER_WRITE |
 495                                        PIPE_TRANSFER_DISCARD_RANGE |
 496                                        usage,
 497                                        &box, &transfer);
 498         if (!map)
 499                 return;
 500
 501         memcpy(map, data, size);
 502         r600_buffer_transfer_unmap(ctx, transfer);
 503 }
 504
 505 static const struct u_resource_vtbl r600_buffer_vtbl =
 506 {
 507         NULL,                           /* get_handle */
 508         r600_buffer_destroy,            /* resource_destroy */
 509         r600_buffer_transfer_map,       /* transfer_map */
 510         r600_buffer_flush_region,       /* transfer_flush_region */
 511         r600_buffer_transfer_unmap,     /* transfer_unmap */
 512 };
 513
 514 static struct r600_resource *
 515 r600_alloc_buffer_struct(struct pipe_screen *screen,
 516                          const struct pipe_resource *templ)
 517 {
 518         struct r600_resource *rbuffer;
 519
 520         rbuffer = MALLOC_STRUCT(r600_resource);
 521
 522         rbuffer->b.b = *templ;
 523         rbuffer->b.b.next = NULL;
 524         pipe_reference_init(&rbuffer->b.b.reference, 1);
 525         rbuffer->b.b.screen = screen;
 526         rbuffer->b.vtbl = &r600_buffer_vtbl;
 527         rbuffer->buf = NULL;
 528         rbuffer->bind_history = 0;
 529         rbuffer->TC_L2_dirty = false;
 530         rbuffer->is_shared = false;
 531         util_range_init(&rbuffer->valid_buffer_range);
 532         return rbuffer;
 533 }
 534
 535 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 536                                          const struct pipe_resource *templ,
 537                                          unsigned alignment)
 538 {
 539         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 540         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 541
 542         r600_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
 543
 544         if (templ->bind & PIPE_BIND_SHARED)
 545                 rbuffer->flags |= RADEON_FLAG_HANDLE;
 546         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 547                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 548
 549         if (!r600_alloc_resource(rscreen, rbuffer)) {
 550                 FREE(rbuffer);
 551                 return NULL;
 552         }
 553         return &rbuffer->b.b;
 554 }
 555
 556 struct pipe_resource *r600_aligned_buffer_create(struct pipe_screen *screen,
 557                                                  unsigned flags,
 558                                                  unsigned usage,
 559                                                  unsigned size,
 560                                                  unsigned alignment)
 561 {
 562         struct pipe_resource buffer;
 563
 564         memset(&buffer, 0, sizeof buffer);
 565         buffer.target = PIPE_BUFFER;
 566         buffer.format = PIPE_FORMAT_R8_UNORM;
 567         buffer.bind = 0;
 568         buffer.usage = usage;
 569         buffer.flags = flags;
 570         buffer.width0 = size;
 571         buffer.height0 = 1;
 572         buffer.depth0 = 1;
 573         buffer.array_size = 1;
 574         return r600_buffer_create(screen, &buffer, alignment);
 575 }
 576
 577 struct pipe_resource *
 578 r600_buffer_from_user_memory(struct pipe_screen *screen,
 579                              const struct pipe_resource *templ,
 580                              void *user_memory)
 581 {
 582         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 583         struct radeon_winsys *ws = rscreen->ws;
 584         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 585
 586         rbuffer->domains = RADEON_DOMAIN_GTT;
 587         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 588
 589         /* Convert a user pointer to a buffer. */
 590         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 591         if (!rbuffer->buf) {
 592                 FREE(rbuffer);
 593                 return NULL;
 594         }
 595
 596         if (rscreen->info.has_virtual_memory)
 597                 rbuffer->gpu_address =
 598                         ws->buffer_get_virtual_address(rbuffer->buf);
 599         else
 600                 rbuffer->gpu_address = 0;
 601
 602         return &rbuffer->b.b;
 603 }