src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                         struct radeon_winsys_cs_handle *buf,
  35                                         enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  38                 return TRUE;
  39         }
  40         if (ctx->dma.cs && ctx->dma.cs->cdw &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  42                 return TRUE;
  43         }
  44         return FALSE;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  55                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
  56         }
  57
  58         if (!(usage & PIPE_TRANSFER_WRITE)) {
  59                 /* have to wait for the last write */
  60                 rusage = RADEON_USAGE_WRITE;
  61         }
  62
  63         if (ctx->gfx.cs->cdw != ctx->initial_gfx_cs_size &&
  64             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  65                                              resource->cs_buf, rusage)) {
  66                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  67                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  68                         return NULL;
  69                 } else {
  70                         ctx->gfx.flush(ctx, 0, NULL);
  71                         busy = true;
  72                 }
  73         }
  74         if (ctx->dma.cs &&
  75             ctx->dma.cs->cdw &&
  76             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  77                                              resource->cs_buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  80                         return NULL;
  81                 } else {
  82                         ctx->dma.flush(ctx, 0, NULL);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  94                         if (ctx->dma.cs)
  95                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
 101 }
 102
 103 bool r600_init_resource(struct r600_common_screen *rscreen,
 104                         struct r600_resource *res,
 105                         unsigned size, unsigned alignment,
 106                         bool use_reusable_pool)
 107 {
 108         struct r600_texture *rtex = (struct r600_texture*)res;
 109         struct pb_buffer *old_buf, *new_buf;
 110         enum radeon_bo_flag flags = 0;
 111
 112         switch (res->b.b.usage) {
 113         case PIPE_USAGE_STREAM:
 114                 flags = RADEON_FLAG_GTT_WC;
 115                 /* fall through */
 116         case PIPE_USAGE_STAGING:
 117                 /* Transfers are likely to occur more often with these resources. */
 118                 res->domains = RADEON_DOMAIN_GTT;
 119                 break;
 120         case PIPE_USAGE_DYNAMIC:
 121                 /* Older kernels didn't always flush the HDP cache before
 122                  * CS execution
 123                  */
 124                 if (rscreen->info.drm_major == 2 &&
 125                     rscreen->info.drm_minor < 40) {
 126                         res->domains = RADEON_DOMAIN_GTT;
 127                         flags |= RADEON_FLAG_GTT_WC;
 128                         break;
 129                 }
 130                 flags |= RADEON_FLAG_CPU_ACCESS;
 131                 /* fall through */
 132         case PIPE_USAGE_DEFAULT:
 133         case PIPE_USAGE_IMMUTABLE:
 134         default:
 135                 /* Not listing GTT here improves performance in some apps. */
 136                 res->domains = RADEON_DOMAIN_VRAM;
 137                 flags |= RADEON_FLAG_GTT_WC;
 138                 break;
 139         }
 140
 141         if (res->b.b.target == PIPE_BUFFER &&
 142             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 143                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 144                 /* Use GTT for all persistent mappings with older kernels,
 145                  * because they didn't always flush the HDP cache before CS
 146                  * execution.
 147                  *
 148                  * Write-combined CPU mappings are fine, the kernel ensures all CPU
 149                  * writes finish before the GPU executes a command stream.
 150                  */
 151                 if (rscreen->info.drm_major == 2 &&
 152                     rscreen->info.drm_minor < 40)
 153                         res->domains = RADEON_DOMAIN_GTT;
 154                 else if (res->domains & RADEON_DOMAIN_VRAM)
 155                         flags |= RADEON_FLAG_CPU_ACCESS;
 156         }
 157
 158         /* Tiled textures are unmappable. Always put them in VRAM. */
 159         if (res->b.b.target != PIPE_BUFFER &&
 160             rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
 161                 res->domains = RADEON_DOMAIN_VRAM;
 162                 flags &= ~RADEON_FLAG_CPU_ACCESS;
 163                 flags |= RADEON_FLAG_NO_CPU_ACCESS;
 164         }
 165
 166         if (rscreen->debug_flags & DBG_NO_WC)
 167                 flags &= ~RADEON_FLAG_GTT_WC;
 168
 169         /* Allocate a new resource. */
 170         new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
 171                                              use_reusable_pool,
 172                                              res->domains, flags);
 173         if (!new_buf) {
 174                 return false;
 175         }
 176
 177         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 178          * NULL. This should prevent crashes with multiple contexts using
 179          * the same buffer where one of the contexts invalidates it while
 180          * the others are using it. */
 181         old_buf = res->buf;
 182         res->cs_buf = rscreen->ws->buffer_get_cs_handle(new_buf); /* should be atomic */
 183         res->buf = new_buf; /* should be atomic */
 184
 185         if (rscreen->info.r600_virtual_address)
 186                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->cs_buf);
 187         else
 188                 res->gpu_address = 0;
 189
 190         pb_reference(&old_buf, NULL);
 191
 192         util_range_set_empty(&res->valid_buffer_range);
 193         res->TC_L2_dirty = false;
 194
 195         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 196                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %u bytes\n",
 197                         res->gpu_address, res->gpu_address + res->buf->size,
 198                         res->buf->size);
 199         }
 200         return true;
 201 }
 202
 203 static void r600_buffer_destroy(struct pipe_screen *screen,
 204                                 struct pipe_resource *buf)
 205 {
 206         struct r600_resource *rbuffer = r600_resource(buf);
 207
 208         util_range_destroy(&rbuffer->valid_buffer_range);
 209         pb_reference(&rbuffer->buf, NULL);
 210         FREE(rbuffer);
 211 }
 212
 213 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 214                                       struct pipe_resource *resource,
 215                                       unsigned level,
 216                                       unsigned usage,
 217                                       const struct pipe_box *box,
 218                                       struct pipe_transfer **ptransfer,
 219                                       void *data, struct r600_resource *staging,
 220                                       unsigned offset)
 221 {
 222         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 223         struct r600_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
 224
 225         transfer->transfer.resource = resource;
 226         transfer->transfer.level = level;
 227         transfer->transfer.usage = usage;
 228         transfer->transfer.box = *box;
 229         transfer->transfer.stride = 0;
 230         transfer->transfer.layer_stride = 0;
 231         transfer->offset = offset;
 232         transfer->staging = staging;
 233         *ptransfer = &transfer->transfer;
 234         return data;
 235 }
 236
 237 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 238                                      unsigned dstx, unsigned srcx, unsigned size)
 239 {
 240         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 241
 242         return rctx->screen->has_cp_dma ||
 243                (dword_aligned && (rctx->dma.cs ||
 244                                   rctx->screen->has_streamout));
 245
 246 }
 247
 248 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 249                                       struct pipe_resource *resource,
 250                                       unsigned level,
 251                                       unsigned usage,
 252                                       const struct pipe_box *box,
 253                                       struct pipe_transfer **ptransfer)
 254 {
 255         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 256         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 257         struct r600_resource *rbuffer = r600_resource(resource);
 258         uint8_t *data;
 259
 260         assert(box->x + box->width <= resource->width0);
 261
 262         /* See if the buffer range being mapped has never been initialized,
 263          * in which case it can be mapped unsynchronized. */
 264         if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 265             usage & PIPE_TRANSFER_WRITE &&
 266             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 267                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 268         }
 269
 270         /* If discarding the entire range, discard the whole resource instead. */
 271         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 272             box->x == 0 && box->width == resource->width0) {
 273                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 274         }
 275
 276         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 277             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 278                 assert(usage & PIPE_TRANSFER_WRITE);
 279
 280                 /* Check if mapping this buffer would cause waiting for the GPU. */
 281                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 282                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 283                         rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 284                 }
 285                 /* At this point, the buffer is always idle. */
 286                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 287         }
 288         else if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 289                  !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 290                  !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 291                  r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) {
 292                 assert(usage & PIPE_TRANSFER_WRITE);
 293
 294                 /* Check if mapping this buffer would cause waiting for the GPU. */
 295                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 296                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 297                         /* Do a wait-free write-only transfer using a temporary buffer. */
 298                         unsigned offset;
 299                         struct r600_resource *staging = NULL;
 300
 301                         u_upload_alloc(rctx->uploader, 0, box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 302                                        &offset, (struct pipe_resource**)&staging, (void**)&data);
 303
 304                         if (staging) {
 305                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 306                                 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 307                                                                 ptransfer, data, staging, offset);
 308                         }
 309                 } else {
 310                         /* At this point, the buffer is always idle (we checked it above). */
 311                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 312                 }
 313         }
 314         /* Using a staging buffer in GTT for larger reads is much faster. */
 315         else if ((usage & PIPE_TRANSFER_READ) &&
 316                  !(usage & PIPE_TRANSFER_WRITE) &&
 317                  rbuffer->domains == RADEON_DOMAIN_VRAM &&
 318                  r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) {
 319                 struct r600_resource *staging;
 320
 321                 staging = (struct r600_resource*) pipe_buffer_create(
 322                                 ctx->screen, PIPE_BIND_TRANSFER_READ, PIPE_USAGE_STAGING,
 323                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 324                 if (staging) {
 325                         /* Copy the VRAM buffer to the staging buffer. */
 326                         rctx->dma_copy(ctx, &staging->b.b, 0,
 327                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 328                                        0, 0, resource, level, box);
 329
 330                         data = r600_buffer_map_sync_with_rings(rctx, staging, PIPE_TRANSFER_READ);
 331                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 332
 333                         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 334                                                         ptransfer, data, staging, 0);
 335                 }
 336         }
 337
 338         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 339         if (!data) {
 340                 return NULL;
 341         }
 342         data += box->x;
 343
 344         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 345                                         ptransfer, data, NULL, 0);
 346 }
 347
 348 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 349                                         struct pipe_transfer *transfer,
 350                                         const struct pipe_box *box)
 351 {
 352         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 353         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 354         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 355
 356         if (rtransfer->staging) {
 357                 struct pipe_resource *dst, *src;
 358                 unsigned soffset;
 359                 struct pipe_box dma_box;
 360
 361                 dst = transfer->resource;
 362                 src = &rtransfer->staging->b.b;
 363                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 364
 365                 u_box_1d(soffset, box->width, &dma_box);
 366
 367                 /* Copy the staging buffer into the original one. */
 368                 rctx->dma_copy(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 369         }
 370
 371         util_range_add(&rbuffer->valid_buffer_range, box->x,
 372                        box->x + box->width);
 373 }
 374
 375 static void r600_buffer_flush_region(struct pipe_context *ctx,
 376                                      struct pipe_transfer *transfer,
 377                                      const struct pipe_box *rel_box)
 378 {
 379         if (transfer->usage & (PIPE_TRANSFER_WRITE |
 380                                PIPE_TRANSFER_FLUSH_EXPLICIT)) {
 381                 struct pipe_box box;
 382
 383                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 384                 r600_buffer_do_flush_region(ctx, transfer, &box);
 385         }
 386 }
 387
 388 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 389                                        struct pipe_transfer *transfer)
 390 {
 391         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 392         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 393
 394         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 395             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 396                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 397
 398         if (rtransfer->staging)
 399                 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
 400
 401         util_slab_free(&rctx->pool_transfers, transfer);
 402 }
 403
 404 static const struct u_resource_vtbl r600_buffer_vtbl =
 405 {
 406         NULL,                           /* get_handle */
 407         r600_buffer_destroy,            /* resource_destroy */
 408         r600_buffer_transfer_map,       /* transfer_map */
 409         r600_buffer_flush_region,       /* transfer_flush_region */
 410         r600_buffer_transfer_unmap,     /* transfer_unmap */
 411         NULL                            /* transfer_inline_write */
 412 };
 413
 414 static struct r600_resource *
 415 r600_alloc_buffer_struct(struct pipe_screen *screen,
 416                          const struct pipe_resource *templ)
 417 {
 418         struct r600_resource *rbuffer;
 419
 420         rbuffer = MALLOC_STRUCT(r600_resource);
 421
 422         rbuffer->b.b = *templ;
 423         pipe_reference_init(&rbuffer->b.b.reference, 1);
 424         rbuffer->b.b.screen = screen;
 425         rbuffer->b.vtbl = &r600_buffer_vtbl;
 426         rbuffer->buf = NULL;
 427         rbuffer->TC_L2_dirty = false;
 428         util_range_init(&rbuffer->valid_buffer_range);
 429         return rbuffer;
 430 }
 431
 432 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 433                                          const struct pipe_resource *templ,
 434                                          unsigned alignment)
 435 {
 436         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 437         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 438
 439         if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE)) {
 440                 FREE(rbuffer);
 441                 return NULL;
 442         }
 443         return &rbuffer->b.b;
 444 }
 445
 446 struct pipe_resource *r600_aligned_buffer_create(struct pipe_screen *screen,
 447                                                  unsigned bind,
 448                                                  unsigned usage,
 449                                                  unsigned size,
 450                                                  unsigned alignment)
 451 {
 452         struct pipe_resource buffer;
 453
 454         memset(&buffer, 0, sizeof buffer);
 455         buffer.target = PIPE_BUFFER;
 456         buffer.format = PIPE_FORMAT_R8_UNORM;
 457         buffer.bind = bind;
 458         buffer.usage = usage;
 459         buffer.flags = 0;
 460         buffer.width0 = size;
 461         buffer.height0 = 1;
 462         buffer.depth0 = 1;
 463         buffer.array_size = 1;
 464         return r600_buffer_create(screen, &buffer, alignment);
 465 }
 466
 467 struct pipe_resource *
 468 r600_buffer_from_user_memory(struct pipe_screen *screen,
 469                              const struct pipe_resource *templ,
 470                              void *user_memory)
 471 {
 472         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 473         struct radeon_winsys *ws = rscreen->ws;
 474         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 475
 476         rbuffer->domains = RADEON_DOMAIN_GTT;
 477         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 478
 479         /* Convert a user pointer to a buffer. */
 480         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 481         if (!rbuffer->buf) {
 482                 FREE(rbuffer);
 483                 return NULL;
 484         }
 485
 486         rbuffer->cs_buf = ws->buffer_get_cs_handle(rbuffer->buf);
 487
 488         if (rscreen->info.r600_virtual_address)
 489                 rbuffer->gpu_address =
 490                         ws->buffer_get_virtual_address(rbuffer->cs_buf);
 491         else
 492                 rbuffer->gpu_address = 0;
 493
 494         return &rbuffer->b.b;
 495 }