src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                         struct pb_buffer *buf,
  35                                         enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  38                 return TRUE;
  39         }
  40         if (ctx->dma.cs && ctx->dma.cs->cdw &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  42                 return TRUE;
  43         }
  44         return FALSE;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  55                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  56         }
  57
  58         if (!(usage & PIPE_TRANSFER_WRITE)) {
  59                 /* have to wait for the last write */
  60                 rusage = RADEON_USAGE_WRITE;
  61         }
  62
  63         if (ctx->gfx.cs->cdw != ctx->initial_gfx_cs_size &&
  64             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  65                                              resource->buf, rusage)) {
  66                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  67                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  68                         return NULL;
  69                 } else {
  70                         ctx->gfx.flush(ctx, 0, NULL);
  71                         busy = true;
  72                 }
  73         }
  74         if (ctx->dma.cs &&
  75             ctx->dma.cs->cdw &&
  76             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  77                                              resource->buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  80                         return NULL;
  81                 } else {
  82                         ctx->dma.flush(ctx, 0, NULL);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  94                         if (ctx->dma.cs)
  95                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return ctx->ws->buffer_map(resource->buf, NULL, usage);
 101 }
 102
 103 bool r600_init_resource(struct r600_common_screen *rscreen,
 104                         struct r600_resource *res,
 105                         uint64_t size, unsigned alignment)
 106 {
 107         struct r600_texture *rtex = (struct r600_texture*)res;
 108         struct pb_buffer *old_buf, *new_buf;
 109         enum radeon_bo_flag flags = 0;
 110
 111         switch (res->b.b.usage) {
 112         case PIPE_USAGE_STREAM:
 113                 flags = RADEON_FLAG_GTT_WC;
 114                 /* fall through */
 115         case PIPE_USAGE_STAGING:
 116                 /* Transfers are likely to occur more often with these resources. */
 117                 res->domains = RADEON_DOMAIN_GTT;
 118                 break;
 119         case PIPE_USAGE_DYNAMIC:
 120                 /* Older kernels didn't always flush the HDP cache before
 121                  * CS execution
 122                  */
 123                 if (rscreen->info.drm_major == 2 &&
 124                     rscreen->info.drm_minor < 40) {
 125                         res->domains = RADEON_DOMAIN_GTT;
 126                         flags |= RADEON_FLAG_GTT_WC;
 127                         break;
 128                 }
 129                 flags |= RADEON_FLAG_CPU_ACCESS;
 130                 /* fall through */
 131         case PIPE_USAGE_DEFAULT:
 132         case PIPE_USAGE_IMMUTABLE:
 133         default:
 134                 /* Not listing GTT here improves performance in some apps. */
 135                 res->domains = RADEON_DOMAIN_VRAM;
 136                 flags |= RADEON_FLAG_GTT_WC;
 137                 break;
 138         }
 139
 140         if (res->b.b.target == PIPE_BUFFER &&
 141             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 142                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 143                 /* Use GTT for all persistent mappings with older kernels,
 144                  * because they didn't always flush the HDP cache before CS
 145                  * execution.
 146                  *
 147                  * Write-combined CPU mappings are fine, the kernel ensures all CPU
 148                  * writes finish before the GPU executes a command stream.
 149                  */
 150                 if (rscreen->info.drm_major == 2 &&
 151                     rscreen->info.drm_minor < 40)
 152                         res->domains = RADEON_DOMAIN_GTT;
 153                 else if (res->domains & RADEON_DOMAIN_VRAM)
 154                         flags |= RADEON_FLAG_CPU_ACCESS;
 155         }
 156
 157         /* Tiled textures are unmappable. Always put them in VRAM. */
 158         if (res->b.b.target != PIPE_BUFFER &&
 159             rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
 160                 res->domains = RADEON_DOMAIN_VRAM;
 161                 flags &= ~RADEON_FLAG_CPU_ACCESS;
 162                 flags |= RADEON_FLAG_NO_CPU_ACCESS |
 163                          RADEON_FLAG_GTT_WC;
 164         }
 165
 166         /* If VRAM is just stolen system memory, allow both VRAM and GTT,
 167          * whichever has free space. If a buffer is evicted from VRAM to GTT,
 168          * it will stay there.
 169          */
 170         if (!rscreen->info.has_dedicated_vram &&
 171             res->domains == RADEON_DOMAIN_VRAM)
 172                 res->domains = RADEON_DOMAIN_VRAM_GTT;
 173
 174         if (rscreen->debug_flags & DBG_NO_WC)
 175                 flags &= ~RADEON_FLAG_GTT_WC;
 176
 177         /* Allocate a new resource. */
 178         new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
 179                                              res->domains, flags);
 180         if (!new_buf) {
 181                 return false;
 182         }
 183
 184         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 185          * NULL. This should prevent crashes with multiple contexts using
 186          * the same buffer where one of the contexts invalidates it while
 187          * the others are using it. */
 188         old_buf = res->buf;
 189         res->buf = new_buf; /* should be atomic */
 190
 191         if (rscreen->info.has_virtual_memory)
 192                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 193         else
 194                 res->gpu_address = 0;
 195
 196         pb_reference(&old_buf, NULL);
 197
 198         util_range_set_empty(&res->valid_buffer_range);
 199         res->TC_L2_dirty = false;
 200
 201         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 202                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 203                         res->gpu_address, res->gpu_address + res->buf->size,
 204                         res->buf->size);
 205         }
 206         return true;
 207 }
 208
 209 static void r600_buffer_destroy(struct pipe_screen *screen,
 210                                 struct pipe_resource *buf)
 211 {
 212         struct r600_resource *rbuffer = r600_resource(buf);
 213
 214         util_range_destroy(&rbuffer->valid_buffer_range);
 215         pb_reference(&rbuffer->buf, NULL);
 216         FREE(rbuffer);
 217 }
 218
 219 static bool
 220 r600_invalidate_buffer(struct r600_common_context *rctx,
 221                        struct r600_resource *rbuffer)
 222 {
 223         /* Shared buffers can't be reallocated. */
 224         if (rbuffer->is_shared)
 225                 return false;
 226
 227         /* In AMD_pinned_memory, the user pointer association only gets
 228          * broken when the buffer is explicitly re-allocated.
 229          */
 230         if (rctx->ws->buffer_is_user_ptr(rbuffer->buf))
 231                 return false;
 232
 233         /* Check if mapping this buffer would cause waiting for the GPU. */
 234         if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 235             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 236                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 237         } else {
 238                 util_range_set_empty(&rbuffer->valid_buffer_range);
 239         }
 240
 241         return true;
 242 }
 243
 244 void r600_invalidate_resource(struct pipe_context *ctx,
 245                               struct pipe_resource *resource)
 246 {
 247         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 248         struct r600_resource *rbuffer = r600_resource(resource);
 249
 250         /* We currently only do anyting here for buffers */
 251         if (resource->target == PIPE_BUFFER)
 252                 (void)r600_invalidate_buffer(rctx, rbuffer);
 253 }
 254
 255 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 256                                       struct pipe_resource *resource,
 257                                       unsigned level,
 258                                       unsigned usage,
 259                                       const struct pipe_box *box,
 260                                       struct pipe_transfer **ptransfer,
 261                                       void *data, struct r600_resource *staging,
 262                                       unsigned offset)
 263 {
 264         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 265         struct r600_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
 266
 267         transfer->transfer.resource = resource;
 268         transfer->transfer.level = level;
 269         transfer->transfer.usage = usage;
 270         transfer->transfer.box = *box;
 271         transfer->transfer.stride = 0;
 272         transfer->transfer.layer_stride = 0;
 273         transfer->offset = offset;
 274         transfer->staging = staging;
 275         *ptransfer = &transfer->transfer;
 276         return data;
 277 }
 278
 279 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 280                                      unsigned dstx, unsigned srcx, unsigned size)
 281 {
 282         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 283
 284         return rctx->screen->has_cp_dma ||
 285                (dword_aligned && (rctx->dma.cs ||
 286                                   rctx->screen->has_streamout));
 287
 288 }
 289
 290 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 291                                       struct pipe_resource *resource,
 292                                       unsigned level,
 293                                       unsigned usage,
 294                                       const struct pipe_box *box,
 295                                       struct pipe_transfer **ptransfer)
 296 {
 297         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 298         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 299         struct r600_resource *rbuffer = r600_resource(resource);
 300         uint8_t *data;
 301
 302         assert(box->x + box->width <= resource->width0);
 303
 304         /* See if the buffer range being mapped has never been initialized,
 305          * in which case it can be mapped unsynchronized. */
 306         if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 307             usage & PIPE_TRANSFER_WRITE &&
 308             !rbuffer->is_shared &&
 309             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 310                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 311         }
 312
 313         /* If discarding the entire range, discard the whole resource instead. */
 314         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 315             box->x == 0 && box->width == resource->width0) {
 316                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 317         }
 318
 319         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 320             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 321                 assert(usage & PIPE_TRANSFER_WRITE);
 322
 323                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 324                         /* At this point, the buffer is always idle. */
 325                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 326                 } else {
 327                         /* Fall back to a temporary buffer. */
 328                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 329                 }
 330         }
 331
 332         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 333             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 334                        PIPE_TRANSFER_PERSISTENT)) &&
 335             !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 336             r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) {
 337                 assert(usage & PIPE_TRANSFER_WRITE);
 338
 339                 /* Check if mapping this buffer would cause waiting for the GPU. */
 340                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 341                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 342                         /* Do a wait-free write-only transfer using a temporary buffer. */
 343                         unsigned offset;
 344                         struct r600_resource *staging = NULL;
 345
 346                         u_upload_alloc(rctx->uploader, 0, box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 347                                        256, &offset, (struct pipe_resource**)&staging, (void**)&data);
 348
 349                         if (staging) {
 350                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 351                                 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 352                                                                 ptransfer, data, staging, offset);
 353                         }
 354                 } else {
 355                         /* At this point, the buffer is always idle (we checked it above). */
 356                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 357                 }
 358         }
 359         /* Using a staging buffer in GTT for larger reads is much faster. */
 360         else if ((usage & PIPE_TRANSFER_READ) &&
 361                  !(usage & (PIPE_TRANSFER_WRITE |
 362                             PIPE_TRANSFER_PERSISTENT)) &&
 363                  rbuffer->domains == RADEON_DOMAIN_VRAM &&
 364                  r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) {
 365                 struct r600_resource *staging;
 366
 367                 staging = (struct r600_resource*) pipe_buffer_create(
 368                                 ctx->screen, PIPE_BIND_TRANSFER_READ, PIPE_USAGE_STAGING,
 369                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 370                 if (staging) {
 371                         /* Copy the VRAM buffer to the staging buffer. */
 372                         rctx->dma_copy(ctx, &staging->b.b, 0,
 373                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 374                                        0, 0, resource, level, box);
 375
 376                         data = r600_buffer_map_sync_with_rings(rctx, staging, PIPE_TRANSFER_READ);
 377                         if (!data) {
 378                                 pipe_resource_reference((struct pipe_resource **)&staging, NULL);
 379                                 return NULL;
 380                         }
 381                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 382
 383                         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 384                                                         ptransfer, data, staging, 0);
 385                 }
 386         }
 387
 388         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 389         if (!data) {
 390                 return NULL;
 391         }
 392         data += box->x;
 393
 394         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 395                                         ptransfer, data, NULL, 0);
 396 }
 397
 398 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 399                                         struct pipe_transfer *transfer,
 400                                         const struct pipe_box *box)
 401 {
 402         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 403         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 404         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 405
 406         if (rtransfer->staging) {
 407                 struct pipe_resource *dst, *src;
 408                 unsigned soffset;
 409                 struct pipe_box dma_box;
 410
 411                 dst = transfer->resource;
 412                 src = &rtransfer->staging->b.b;
 413                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 414
 415                 u_box_1d(soffset, box->width, &dma_box);
 416
 417                 /* Copy the staging buffer into the original one. */
 418                 rctx->dma_copy(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 419         }
 420
 421         util_range_add(&rbuffer->valid_buffer_range, box->x,
 422                        box->x + box->width);
 423 }
 424
 425 static void r600_buffer_flush_region(struct pipe_context *ctx,
 426                                      struct pipe_transfer *transfer,
 427                                      const struct pipe_box *rel_box)
 428 {
 429         if (transfer->usage & (PIPE_TRANSFER_WRITE |
 430                                PIPE_TRANSFER_FLUSH_EXPLICIT)) {
 431                 struct pipe_box box;
 432
 433                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 434                 r600_buffer_do_flush_region(ctx, transfer, &box);
 435         }
 436 }
 437
 438 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 439                                        struct pipe_transfer *transfer)
 440 {
 441         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 442         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 443
 444         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 445             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 446                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 447
 448         if (rtransfer->staging)
 449                 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
 450
 451         util_slab_free(&rctx->pool_transfers, transfer);
 452 }
 453
 454 static const struct u_resource_vtbl r600_buffer_vtbl =
 455 {
 456         NULL,                           /* get_handle */
 457         r600_buffer_destroy,            /* resource_destroy */
 458         r600_buffer_transfer_map,       /* transfer_map */
 459         r600_buffer_flush_region,       /* transfer_flush_region */
 460         r600_buffer_transfer_unmap,     /* transfer_unmap */
 461         NULL                            /* transfer_inline_write */
 462 };
 463
 464 static struct r600_resource *
 465 r600_alloc_buffer_struct(struct pipe_screen *screen,
 466                          const struct pipe_resource *templ)
 467 {
 468         struct r600_resource *rbuffer;
 469
 470         rbuffer = MALLOC_STRUCT(r600_resource);
 471
 472         rbuffer->b.b = *templ;
 473         pipe_reference_init(&rbuffer->b.b.reference, 1);
 474         rbuffer->b.b.screen = screen;
 475         rbuffer->b.vtbl = &r600_buffer_vtbl;
 476         rbuffer->buf = NULL;
 477         rbuffer->TC_L2_dirty = false;
 478         rbuffer->is_shared = false;
 479         util_range_init(&rbuffer->valid_buffer_range);
 480         return rbuffer;
 481 }
 482
 483 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 484                                          const struct pipe_resource *templ,
 485                                          unsigned alignment)
 486 {
 487         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 488         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 489
 490         if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment)) {
 491                 FREE(rbuffer);
 492                 return NULL;
 493         }
 494         return &rbuffer->b.b;
 495 }
 496
 497 struct pipe_resource *r600_aligned_buffer_create(struct pipe_screen *screen,
 498                                                  unsigned bind,
 499                                                  unsigned usage,
 500                                                  unsigned size,
 501                                                  unsigned alignment)
 502 {
 503         struct pipe_resource buffer;
 504
 505         memset(&buffer, 0, sizeof buffer);
 506         buffer.target = PIPE_BUFFER;
 507         buffer.format = PIPE_FORMAT_R8_UNORM;
 508         buffer.bind = bind;
 509         buffer.usage = usage;
 510         buffer.flags = 0;
 511         buffer.width0 = size;
 512         buffer.height0 = 1;
 513         buffer.depth0 = 1;
 514         buffer.array_size = 1;
 515         return r600_buffer_create(screen, &buffer, alignment);
 516 }
 517
 518 struct pipe_resource *
 519 r600_buffer_from_user_memory(struct pipe_screen *screen,
 520                              const struct pipe_resource *templ,
 521                              void *user_memory)
 522 {
 523         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 524         struct radeon_winsys *ws = rscreen->ws;
 525         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 526
 527         rbuffer->domains = RADEON_DOMAIN_GTT;
 528         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 529
 530         /* Convert a user pointer to a buffer. */
 531         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 532         if (!rbuffer->buf) {
 533                 FREE(rbuffer);
 534                 return NULL;
 535         }
 536
 537         if (rscreen->info.has_virtual_memory)
 538                 rbuffer->gpu_address =
 539                         ws->buffer_get_virtual_address(rbuffer->buf);
 540         else
 541                 rbuffer->gpu_address = 0;
 542
 543         return &rbuffer->b.b;
 544 }