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[mesa.git] / src / gallium / drivers / radeon / r600_buffer_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák
25 */
26
27 #include "r600_cs.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30 #include <inttypes.h>
31 #include <stdio.h>
32
33 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
34 struct pb_buffer *buf,
35 enum radeon_bo_usage usage)
36 {
37 if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
38 return true;
39 }
40 if (radeon_emitted(ctx->dma.cs, 0) &&
41 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
42 return true;
43 }
44 return false;
45 }
46
47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
48 struct r600_resource *resource,
49 unsigned usage)
50 {
51 enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
52 bool busy = false;
53
54 assert(!(resource->flags & RADEON_FLAG_SPARSE));
55
56 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
57 return ctx->ws->buffer_map(resource->buf, NULL, usage);
58 }
59
60 if (!(usage & PIPE_TRANSFER_WRITE)) {
61 /* have to wait for the last write */
62 rusage = RADEON_USAGE_WRITE;
63 }
64
65 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
66 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
67 resource->buf, rusage)) {
68 if (usage & PIPE_TRANSFER_DONTBLOCK) {
69 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
70 return NULL;
71 } else {
72 ctx->gfx.flush(ctx, 0, NULL);
73 busy = true;
74 }
75 }
76 if (radeon_emitted(ctx->dma.cs, 0) &&
77 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
78 resource->buf, rusage)) {
79 if (usage & PIPE_TRANSFER_DONTBLOCK) {
80 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
81 return NULL;
82 } else {
83 ctx->dma.flush(ctx, 0, NULL);
84 busy = true;
85 }
86 }
87
88 if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
89 if (usage & PIPE_TRANSFER_DONTBLOCK) {
90 return NULL;
91 } else {
92 /* We will be wait for the GPU. Wait for any offloaded
93 * CS flush to complete to avoid busy-waiting in the winsys. */
94 ctx->ws->cs_sync_flush(ctx->gfx.cs);
95 if (ctx->dma.cs)
96 ctx->ws->cs_sync_flush(ctx->dma.cs);
97 }
98 }
99
100 /* Setting the CS to NULL will prevent doing checks we have done already. */
101 return ctx->ws->buffer_map(resource->buf, NULL, usage);
102 }
103
104 void r600_init_resource_fields(struct r600_common_screen *rscreen,
105 struct r600_resource *res,
106 uint64_t size, unsigned alignment)
107 {
108 struct r600_texture *rtex = (struct r600_texture*)res;
109
110 res->bo_size = size;
111 res->bo_alignment = alignment;
112 res->flags = 0;
113
114 switch (res->b.b.usage) {
115 case PIPE_USAGE_STREAM:
116 res->flags = RADEON_FLAG_GTT_WC;
117 /* fall through */
118 case PIPE_USAGE_STAGING:
119 /* Transfers are likely to occur more often with these
120 * resources. */
121 res->domains = RADEON_DOMAIN_GTT;
122 break;
123 case PIPE_USAGE_DYNAMIC:
124 /* Older kernels didn't always flush the HDP cache before
125 * CS execution
126 */
127 if (rscreen->info.drm_major == 2 &&
128 rscreen->info.drm_minor < 40) {
129 res->domains = RADEON_DOMAIN_GTT;
130 res->flags |= RADEON_FLAG_GTT_WC;
131 break;
132 }
133 res->flags |= RADEON_FLAG_CPU_ACCESS;
134 /* fall through */
135 case PIPE_USAGE_DEFAULT:
136 case PIPE_USAGE_IMMUTABLE:
137 default:
138 /* Not listing GTT here improves performance in some
139 * apps. */
140 res->domains = RADEON_DOMAIN_VRAM;
141 res->flags |= RADEON_FLAG_GTT_WC;
142 break;
143 }
144
145 if (res->b.b.target == PIPE_BUFFER &&
146 res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
147 PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
148 /* Use GTT for all persistent mappings with older
149 * kernels, because they didn't always flush the HDP
150 * cache before CS execution.
151 *
152 * Write-combined CPU mappings are fine, the kernel
153 * ensures all CPU writes finish before the GPU
154 * executes a command stream.
155 */
156 if (rscreen->info.drm_major == 2 &&
157 rscreen->info.drm_minor < 40)
158 res->domains = RADEON_DOMAIN_GTT;
159 else if (res->domains & RADEON_DOMAIN_VRAM)
160 res->flags |= RADEON_FLAG_CPU_ACCESS;
161 }
162
163 /* Tiled textures are unmappable. Always put them in VRAM. */
164 if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
165 res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
166 res->domains = RADEON_DOMAIN_VRAM;
167 res->flags &= ~RADEON_FLAG_CPU_ACCESS;
168 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
169 RADEON_FLAG_GTT_WC;
170 }
171
172 /* If VRAM is just stolen system memory, allow both VRAM and
173 * GTT, whichever has free space. If a buffer is evicted from
174 * VRAM to GTT, it will stay there.
175 *
176 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
177 * placements even with a low amount of stolen VRAM.
178 */
179 if (!rscreen->info.has_dedicated_vram &&
180 (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
181 res->domains == RADEON_DOMAIN_VRAM)
182 res->domains = RADEON_DOMAIN_VRAM_GTT;
183
184 if (rscreen->debug_flags & DBG_NO_WC)
185 res->flags &= ~RADEON_FLAG_GTT_WC;
186
187 /* Set expected VRAM and GART usage for the buffer. */
188 res->vram_usage = 0;
189 res->gart_usage = 0;
190
191 if (res->domains & RADEON_DOMAIN_VRAM)
192 res->vram_usage = size;
193 else if (res->domains & RADEON_DOMAIN_GTT)
194 res->gart_usage = size;
195 }
196
197 bool r600_alloc_resource(struct r600_common_screen *rscreen,
198 struct r600_resource *res)
199 {
200 struct pb_buffer *old_buf, *new_buf;
201
202 /* Allocate a new resource. */
203 new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
204 res->bo_alignment,
205 res->domains, res->flags);
206 if (!new_buf) {
207 return false;
208 }
209
210 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
211 * NULL. This should prevent crashes with multiple contexts using
212 * the same buffer where one of the contexts invalidates it while
213 * the others are using it. */
214 old_buf = res->buf;
215 res->buf = new_buf; /* should be atomic */
216
217 if (rscreen->info.has_virtual_memory)
218 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
219 else
220 res->gpu_address = 0;
221
222 pb_reference(&old_buf, NULL);
223
224 util_range_set_empty(&res->valid_buffer_range);
225 res->TC_L2_dirty = false;
226
227 /* Print debug information. */
228 if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
229 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
230 res->gpu_address, res->gpu_address + res->buf->size,
231 res->buf->size);
232 }
233 return true;
234 }
235
236 static void r600_buffer_destroy(struct pipe_screen *screen,
237 struct pipe_resource *buf)
238 {
239 struct r600_resource *rbuffer = r600_resource(buf);
240
241 threaded_resource_deinit(buf);
242 util_range_destroy(&rbuffer->valid_buffer_range);
243 pb_reference(&rbuffer->buf, NULL);
244 FREE(rbuffer);
245 }
246
247 static bool
248 r600_invalidate_buffer(struct r600_common_context *rctx,
249 struct r600_resource *rbuffer)
250 {
251 /* Shared buffers can't be reallocated. */
252 if (rbuffer->b.is_shared)
253 return false;
254
255 /* Sparse buffers can't be reallocated. */
256 if (rbuffer->flags & RADEON_FLAG_SPARSE)
257 return false;
258
259 /* In AMD_pinned_memory, the user pointer association only gets
260 * broken when the buffer is explicitly re-allocated.
261 */
262 if (rbuffer->b.is_user_ptr)
263 return false;
264
265 /* Check if mapping this buffer would cause waiting for the GPU. */
266 if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
267 !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
268 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
269 } else {
270 util_range_set_empty(&rbuffer->valid_buffer_range);
271 }
272
273 return true;
274 }
275
276 /* Replace the storage of dst with src. */
277 void r600_replace_buffer_storage(struct pipe_context *ctx,
278 struct pipe_resource *dst,
279 struct pipe_resource *src)
280 {
281 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
282 struct r600_resource *rdst = r600_resource(dst);
283 struct r600_resource *rsrc = r600_resource(src);
284 uint64_t old_gpu_address = rdst->gpu_address;
285
286 pb_reference(&rdst->buf, rsrc->buf);
287 rdst->gpu_address = rsrc->gpu_address;
288
289 assert(rdst->vram_usage == rsrc->vram_usage);
290 assert(rdst->gart_usage == rsrc->gart_usage);
291 assert(rdst->bo_size == rsrc->bo_size);
292 assert(rdst->bo_alignment == rsrc->bo_alignment);
293 assert(rdst->domains == rsrc->domains);
294 assert(rdst->flags == rsrc->flags);
295
296 rctx->rebind_buffer(ctx, dst, old_gpu_address);
297 }
298
299 void r600_invalidate_resource(struct pipe_context *ctx,
300 struct pipe_resource *resource)
301 {
302 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
303 struct r600_resource *rbuffer = r600_resource(resource);
304
305 /* We currently only do anyting here for buffers */
306 if (resource->target == PIPE_BUFFER)
307 (void)r600_invalidate_buffer(rctx, rbuffer);
308 }
309
310 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
311 struct pipe_resource *resource,
312 unsigned usage,
313 const struct pipe_box *box,
314 struct pipe_transfer **ptransfer,
315 void *data, struct r600_resource *staging,
316 unsigned offset)
317 {
318 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
319 struct r600_transfer *transfer;
320
321 if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
322 transfer = slab_alloc(&rctx->pool_transfers_unsync);
323 else
324 transfer = slab_alloc(&rctx->pool_transfers);
325
326 transfer->b.b.resource = NULL;
327 pipe_resource_reference(&transfer->b.b.resource, resource);
328 transfer->b.b.level = 0;
329 transfer->b.b.usage = usage;
330 transfer->b.b.box = *box;
331 transfer->b.b.stride = 0;
332 transfer->b.b.layer_stride = 0;
333 transfer->b.staging = NULL;
334 transfer->offset = offset;
335 transfer->staging = staging;
336 *ptransfer = &transfer->b.b;
337 return data;
338 }
339
340 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
341 unsigned dstx, unsigned srcx, unsigned size)
342 {
343 bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
344
345 return rctx->screen->has_cp_dma ||
346 (dword_aligned && (rctx->dma.cs ||
347 rctx->screen->has_streamout));
348
349 }
350
351 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
352 struct pipe_resource *resource,
353 unsigned level,
354 unsigned usage,
355 const struct pipe_box *box,
356 struct pipe_transfer **ptransfer)
357 {
358 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
359 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
360 struct r600_resource *rbuffer = r600_resource(resource);
361 uint8_t *data;
362
363 assert(box->x + box->width <= resource->width0);
364
365 /* From GL_AMD_pinned_memory issues:
366 *
367 * 4) Is glMapBuffer on a shared buffer guaranteed to return the
368 * same system address which was specified at creation time?
369 *
370 * RESOLVED: NO. The GL implementation might return a different
371 * virtual mapping of that memory, although the same physical
372 * page will be used.
373 *
374 * So don't ever use staging buffers.
375 */
376 if (rbuffer->b.is_user_ptr)
377 usage |= PIPE_TRANSFER_PERSISTENT;
378
379 /* See if the buffer range being mapped has never been initialized,
380 * in which case it can be mapped unsynchronized. */
381 if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
382 TC_TRANSFER_MAP_IGNORE_VALID_RANGE)) &&
383 usage & PIPE_TRANSFER_WRITE &&
384 !rbuffer->b.is_shared &&
385 !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
386 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
387 }
388
389 /* If discarding the entire range, discard the whole resource instead. */
390 if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
391 box->x == 0 && box->width == resource->width0) {
392 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
393 }
394
395 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
396 !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
397 TC_TRANSFER_MAP_NO_INVALIDATE))) {
398 assert(usage & PIPE_TRANSFER_WRITE);
399
400 if (r600_invalidate_buffer(rctx, rbuffer)) {
401 /* At this point, the buffer is always idle. */
402 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
403 } else {
404 /* Fall back to a temporary buffer. */
405 usage |= PIPE_TRANSFER_DISCARD_RANGE;
406 }
407 }
408
409 if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
410 !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
411 ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
412 PIPE_TRANSFER_PERSISTENT)) &&
413 r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
414 (rbuffer->flags & RADEON_FLAG_SPARSE))) {
415 assert(usage & PIPE_TRANSFER_WRITE);
416
417 /* Check if mapping this buffer would cause waiting for the GPU.
418 */
419 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
420 r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
421 !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
422 /* Do a wait-free write-only transfer using a temporary buffer. */
423 unsigned offset;
424 struct r600_resource *staging = NULL;
425
426 u_upload_alloc(ctx->stream_uploader, 0,
427 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
428 rctx->screen->info.tcc_cache_line_size,
429 &offset, (struct pipe_resource**)&staging,
430 (void**)&data);
431
432 if (staging) {
433 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
434 return r600_buffer_get_transfer(ctx, resource, usage, box,
435 ptransfer, data, staging, offset);
436 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
437 return NULL;
438 }
439 } else {
440 /* At this point, the buffer is always idle (we checked it above). */
441 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
442 }
443 }
444 /* Use a staging buffer in cached GTT for reads. */
445 else if (((usage & PIPE_TRANSFER_READ) &&
446 !(usage & PIPE_TRANSFER_PERSISTENT) &&
447 (rbuffer->domains & RADEON_DOMAIN_VRAM ||
448 rbuffer->flags & RADEON_FLAG_GTT_WC) &&
449 r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
450 (rbuffer->flags & RADEON_FLAG_SPARSE)) {
451 struct r600_resource *staging;
452
453 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
454 staging = (struct r600_resource*) pipe_buffer_create(
455 ctx->screen, 0, PIPE_USAGE_STAGING,
456 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
457 if (staging) {
458 /* Copy the VRAM buffer to the staging buffer. */
459 rctx->dma_copy(ctx, &staging->b.b, 0,
460 box->x % R600_MAP_BUFFER_ALIGNMENT,
461 0, 0, resource, 0, box);
462
463 data = r600_buffer_map_sync_with_rings(rctx, staging,
464 usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
465 if (!data) {
466 r600_resource_reference(&staging, NULL);
467 return NULL;
468 }
469 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
470
471 return r600_buffer_get_transfer(ctx, resource, usage, box,
472 ptransfer, data, staging, 0);
473 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
474 return NULL;
475 }
476 }
477
478 data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
479 if (!data) {
480 return NULL;
481 }
482 data += box->x;
483
484 return r600_buffer_get_transfer(ctx, resource, usage, box,
485 ptransfer, data, NULL, 0);
486 }
487
488 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
489 struct pipe_transfer *transfer,
490 const struct pipe_box *box)
491 {
492 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
493 struct r600_resource *rbuffer = r600_resource(transfer->resource);
494
495 if (rtransfer->staging) {
496 struct pipe_resource *dst, *src;
497 unsigned soffset;
498 struct pipe_box dma_box;
499
500 dst = transfer->resource;
501 src = &rtransfer->staging->b.b;
502 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
503
504 u_box_1d(soffset, box->width, &dma_box);
505
506 /* Copy the staging buffer into the original one. */
507 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
508 }
509
510 util_range_add(&rbuffer->valid_buffer_range, box->x,
511 box->x + box->width);
512 }
513
514 static void r600_buffer_flush_region(struct pipe_context *ctx,
515 struct pipe_transfer *transfer,
516 const struct pipe_box *rel_box)
517 {
518 unsigned required_usage = PIPE_TRANSFER_WRITE |
519 PIPE_TRANSFER_FLUSH_EXPLICIT;
520
521 if ((transfer->usage & required_usage) == required_usage) {
522 struct pipe_box box;
523
524 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
525 r600_buffer_do_flush_region(ctx, transfer, &box);
526 }
527 }
528
529 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
530 struct pipe_transfer *transfer)
531 {
532 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
533 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
534
535 if (transfer->usage & PIPE_TRANSFER_WRITE &&
536 !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
537 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
538
539 r600_resource_reference(&rtransfer->staging, NULL);
540 assert(rtransfer->b.staging == NULL); /* for threaded context only */
541 pipe_resource_reference(&transfer->resource, NULL);
542
543 /* Don't use pool_transfers_unsync. We are always in the driver
544 * thread. */
545 slab_free(&rctx->pool_transfers, transfer);
546 }
547
548 void r600_buffer_subdata(struct pipe_context *ctx,
549 struct pipe_resource *buffer,
550 unsigned usage, unsigned offset,
551 unsigned size, const void *data)
552 {
553 struct pipe_transfer *transfer = NULL;
554 struct pipe_box box;
555 uint8_t *map = NULL;
556
557 u_box_1d(offset, size, &box);
558 map = r600_buffer_transfer_map(ctx, buffer, 0,
559 PIPE_TRANSFER_WRITE |
560 PIPE_TRANSFER_DISCARD_RANGE |
561 usage,
562 &box, &transfer);
563 if (!map)
564 return;
565
566 memcpy(map, data, size);
567 r600_buffer_transfer_unmap(ctx, transfer);
568 }
569
570 static const struct u_resource_vtbl r600_buffer_vtbl =
571 {
572 NULL, /* get_handle */
573 r600_buffer_destroy, /* resource_destroy */
574 r600_buffer_transfer_map, /* transfer_map */
575 r600_buffer_flush_region, /* transfer_flush_region */
576 r600_buffer_transfer_unmap, /* transfer_unmap */
577 };
578
579 static struct r600_resource *
580 r600_alloc_buffer_struct(struct pipe_screen *screen,
581 const struct pipe_resource *templ)
582 {
583 struct r600_resource *rbuffer;
584
585 rbuffer = MALLOC_STRUCT(r600_resource);
586
587 rbuffer->b.b = *templ;
588 rbuffer->b.b.next = NULL;
589 pipe_reference_init(&rbuffer->b.b.reference, 1);
590 rbuffer->b.b.screen = screen;
591
592 rbuffer->b.vtbl = &r600_buffer_vtbl;
593 threaded_resource_init(&rbuffer->b.b);
594
595 rbuffer->buf = NULL;
596 rbuffer->bind_history = 0;
597 rbuffer->TC_L2_dirty = false;
598 util_range_init(&rbuffer->valid_buffer_range);
599 return rbuffer;
600 }
601
602 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
603 const struct pipe_resource *templ,
604 unsigned alignment)
605 {
606 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
607 struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
608
609 r600_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
610
611 if (templ->bind & PIPE_BIND_SHARED)
612 rbuffer->flags |= RADEON_FLAG_HANDLE;
613 if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
614 rbuffer->flags |= RADEON_FLAG_SPARSE;
615
616 if (!r600_alloc_resource(rscreen, rbuffer)) {
617 FREE(rbuffer);
618 return NULL;
619 }
620 return &rbuffer->b.b;
621 }
622
623 struct pipe_resource *r600_aligned_buffer_create(struct pipe_screen *screen,
624 unsigned flags,
625 unsigned usage,
626 unsigned size,
627 unsigned alignment)
628 {
629 struct pipe_resource buffer;
630
631 memset(&buffer, 0, sizeof buffer);
632 buffer.target = PIPE_BUFFER;
633 buffer.format = PIPE_FORMAT_R8_UNORM;
634 buffer.bind = 0;
635 buffer.usage = usage;
636 buffer.flags = flags;
637 buffer.width0 = size;
638 buffer.height0 = 1;
639 buffer.depth0 = 1;
640 buffer.array_size = 1;
641 return r600_buffer_create(screen, &buffer, alignment);
642 }
643
644 struct pipe_resource *
645 r600_buffer_from_user_memory(struct pipe_screen *screen,
646 const struct pipe_resource *templ,
647 void *user_memory)
648 {
649 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
650 struct radeon_winsys *ws = rscreen->ws;
651 struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
652
653 rbuffer->domains = RADEON_DOMAIN_GTT;
654 rbuffer->flags = 0;
655 rbuffer->b.is_user_ptr = true;
656 util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
657 util_range_add(&rbuffer->b.valid_buffer_range, 0, templ->width0);
658
659 /* Convert a user pointer to a buffer. */
660 rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
661 if (!rbuffer->buf) {
662 FREE(rbuffer);
663 return NULL;
664 }
665
666 if (rscreen->info.has_virtual_memory)
667 rbuffer->gpu_address =
668 ws->buffer_get_virtual_address(rbuffer->buf);
669 else
670 rbuffer->gpu_address = 0;
671
672 rbuffer->vram_usage = 0;
673 rbuffer->gart_usage = templ->width0;
674
675 return &rbuffer->b.b;
676 }