src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include <inttypes.h>
  29
  30 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  31                                         struct radeon_winsys_cs_handle *buf,
  32                                         enum radeon_bo_usage usage)
  33 {
  34         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
  35                 return TRUE;
  36         }
  37         if (ctx->rings.dma.cs &&
  38             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
  39                 return TRUE;
  40         }
  41         return FALSE;
  42 }
  43
  44 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  45                                       struct r600_resource *resource,
  46                                       unsigned usage)
  47 {
  48         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  49
  50         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  51                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
  52         }
  53
  54         if (!(usage & PIPE_TRANSFER_WRITE)) {
  55                 /* have to wait for the last write */
  56                 rusage = RADEON_USAGE_WRITE;
  57         }
  58
  59         if (ctx->rings.gfx.cs->cdw &&
  60             ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs,
  61                                              resource->cs_buf, rusage)) {
  62                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  63                         ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
  64                         return NULL;
  65                 } else {
  66                         ctx->rings.gfx.flush(ctx, 0);
  67                 }
  68         }
  69         if (ctx->rings.dma.cs &&
  70             ctx->rings.dma.cs->cdw &&
  71             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs,
  72                                              resource->cs_buf, rusage)) {
  73                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  74                         ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
  75                         return NULL;
  76                 } else {
  77                         ctx->rings.dma.flush(ctx, 0);
  78                 }
  79         }
  80
  81         if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
  82                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  83                         return NULL;
  84                 } else {
  85                         /* We will be wait for the GPU. Wait for any offloaded
  86                          * CS flush to complete to avoid busy-waiting in the winsys. */
  87                         ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
  88                         if (ctx->rings.dma.cs)
  89                                 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
  90                 }
  91         }
  92
  93         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
  94 }
  95
  96 bool r600_init_resource(struct r600_common_screen *rscreen,
  97                         struct r600_resource *res,
  98                         unsigned size, unsigned alignment,
  99                         bool use_reusable_pool, unsigned usage)
 100 {
 101         uint32_t initial_domain, domains;
 102
 103         switch(usage) {
 104         case PIPE_USAGE_STAGING:
 105                 /* Staging resources participate in transfers, i.e. are used
 106                  * for uploads and downloads from regular resources.
 107                  * We generate them internally for some transfers.
 108                  */
 109                 initial_domain = RADEON_DOMAIN_GTT;
 110                 domains = RADEON_DOMAIN_GTT;
 111                 break;
 112         case PIPE_USAGE_DYNAMIC:
 113         case PIPE_USAGE_STREAM:
 114                 /* Default to GTT, but allow the memory manager to move it to VRAM. */
 115                 initial_domain = RADEON_DOMAIN_GTT;
 116                 domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
 117                 break;
 118         case PIPE_USAGE_DEFAULT:
 119         case PIPE_USAGE_STATIC:
 120         case PIPE_USAGE_IMMUTABLE:
 121         default:
 122                 /* Don't list GTT here, because the memory manager would put some
 123                  * resources to GTT no matter what the initial domain is.
 124                  * Not listing GTT in the domains improves performance a lot. */
 125                 initial_domain = RADEON_DOMAIN_VRAM;
 126                 domains = RADEON_DOMAIN_VRAM;
 127                 break;
 128         }
 129
 130         res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
 131                                               use_reusable_pool,
 132                                               initial_domain);
 133         if (!res->buf) {
 134                 return false;
 135         }
 136
 137         res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf);
 138         res->domains = domains;
 139         util_range_set_empty(&res->valid_buffer_range);
 140
 141         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 142                 fprintf(stderr, "VM start=0x%"PRIu64"  end=0x%"PRIu64" | Buffer %u bytes\n",
 143                         r600_resource_va(&rscreen->b, &res->b.b),
 144                         r600_resource_va(&rscreen->b, &res->b.b) + res->buf->size,
 145                         res->buf->size);
 146         }
 147         return true;
 148 }