src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                         struct radeon_winsys_cs_handle *buf,
  35                                         enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
  38                 return TRUE;
  39         }
  40         if (ctx->rings.dma.cs && ctx->rings.dma.cs->cdw &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
  42                 return TRUE;
  43         }
  44         return FALSE;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  55                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
  56         }
  57
  58         if (!(usage & PIPE_TRANSFER_WRITE)) {
  59                 /* have to wait for the last write */
  60                 rusage = RADEON_USAGE_WRITE;
  61         }
  62
  63         if (ctx->rings.gfx.cs->cdw != ctx->initial_gfx_cs_size &&
  64             ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs,
  65                                              resource->cs_buf, rusage)) {
  66                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  67                         ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  68                         return NULL;
  69                 } else {
  70                         ctx->rings.gfx.flush(ctx, 0, NULL);
  71                         busy = true;
  72                 }
  73         }
  74         if (ctx->rings.dma.cs &&
  75             ctx->rings.dma.cs->cdw &&
  76             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs,
  77                                              resource->cs_buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  80                         return NULL;
  81                 } else {
  82                         ctx->rings.dma.flush(ctx, 0, NULL);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || ctx->ws->buffer_is_busy(resource->buf, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
  94                         if (ctx->rings.dma.cs)
  95                                 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
 101 }
 102
 103 bool r600_init_resource(struct r600_common_screen *rscreen,
 104                         struct r600_resource *res,
 105                         unsigned size, unsigned alignment,
 106                         bool use_reusable_pool)
 107 {
 108         struct r600_texture *rtex = (struct r600_texture*)res;
 109         struct pb_buffer *old_buf, *new_buf;
 110         enum radeon_bo_flag flags = 0;
 111
 112         switch (res->b.b.usage) {
 113         case PIPE_USAGE_STAGING:
 114                 /* Transfers are likely to occur more often with these resources. */
 115                 res->domains = RADEON_DOMAIN_GTT;
 116                 break;
 117         case PIPE_USAGE_STREAM:
 118         case PIPE_USAGE_DYNAMIC:
 119                 /* Older kernels didn't always flush the HDP cache before
 120                  * CS execution
 121                  */
 122                 if (rscreen->info.drm_minor < 40) {
 123                         res->domains = RADEON_DOMAIN_GTT;
 124                         flags = RADEON_FLAG_GTT_WC;
 125                         break;
 126                 }
 127                 /* fall through */
 128         case PIPE_USAGE_DEFAULT:
 129         case PIPE_USAGE_IMMUTABLE:
 130         default:
 131                 /* Not listing GTT here improves performance in some apps. */
 132                 res->domains = RADEON_DOMAIN_VRAM;
 133                 flags = RADEON_FLAG_GTT_WC;
 134                 break;
 135         }
 136
 137         /* Use GTT for all persistent mappings with older kernels, because they
 138          * didn't always flush the HDP cache before CS execution.
 139          *
 140          * Write-combined CPU mappings are fine, the kernel ensures all CPU
 141          * writes finish before the GPU executes a command stream.
 142          */
 143         if (rscreen->info.drm_minor < 40 &&
 144             res->b.b.target == PIPE_BUFFER &&
 145             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 146                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 147                 res->domains = RADEON_DOMAIN_GTT;
 148         }
 149
 150         /* Tiled textures are unmappable. Always put them in VRAM. */
 151         if (res->b.b.target != PIPE_BUFFER &&
 152             rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
 153                 res->domains = RADEON_DOMAIN_VRAM;
 154         }
 155
 156         /* Allocate a new resource. */
 157         new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
 158                                              use_reusable_pool,
 159                                              res->domains, flags);
 160         if (!new_buf) {
 161                 return false;
 162         }
 163
 164         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 165          * NULL. This should prevent crashes with multiple contexts using
 166          * the same buffer where one of the contexts invalidates it while
 167          * the others are using it. */
 168         old_buf = res->buf;
 169         res->cs_buf = rscreen->ws->buffer_get_cs_handle(new_buf); /* should be atomic */
 170         res->buf = new_buf; /* should be atomic */
 171
 172         if (rscreen->info.r600_virtual_address)
 173                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->cs_buf);
 174         else
 175                 res->gpu_address = 0;
 176
 177         pb_reference(&old_buf, NULL);
 178
 179         util_range_set_empty(&res->valid_buffer_range);
 180
 181         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 182                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %u bytes\n",
 183                         res->gpu_address, res->gpu_address + res->buf->size,
 184                         res->buf->size);
 185         }
 186         return true;
 187 }
 188
 189 static void r600_buffer_destroy(struct pipe_screen *screen,
 190                                 struct pipe_resource *buf)
 191 {
 192         struct r600_resource *rbuffer = r600_resource(buf);
 193
 194         util_range_destroy(&rbuffer->valid_buffer_range);
 195         pb_reference(&rbuffer->buf, NULL);
 196         FREE(rbuffer);
 197 }
 198
 199 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 200                                       struct pipe_resource *resource,
 201                                       unsigned level,
 202                                       unsigned usage,
 203                                       const struct pipe_box *box,
 204                                       struct pipe_transfer **ptransfer,
 205                                       void *data, struct r600_resource *staging,
 206                                       unsigned offset)
 207 {
 208         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 209         struct r600_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
 210
 211         transfer->transfer.resource = resource;
 212         transfer->transfer.level = level;
 213         transfer->transfer.usage = usage;
 214         transfer->transfer.box = *box;
 215         transfer->transfer.stride = 0;
 216         transfer->transfer.layer_stride = 0;
 217         transfer->offset = offset;
 218         transfer->staging = staging;
 219         *ptransfer = &transfer->transfer;
 220         return data;
 221 }
 222
 223 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 224                                      unsigned dstx, unsigned srcx, unsigned size)
 225 {
 226         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 227
 228         return rctx->screen->has_cp_dma ||
 229                (dword_aligned && (rctx->rings.dma.cs ||
 230                                   rctx->screen->has_streamout));
 231
 232 }
 233
 234 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 235                                       struct pipe_resource *resource,
 236                                       unsigned level,
 237                                       unsigned usage,
 238                                       const struct pipe_box *box,
 239                                       struct pipe_transfer **ptransfer)
 240 {
 241         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 242         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 243         struct r600_resource *rbuffer = r600_resource(resource);
 244         uint8_t *data;
 245
 246         assert(box->x + box->width <= resource->width0);
 247
 248         /* See if the buffer range being mapped has never been initialized,
 249          * in which case it can be mapped unsynchronized. */
 250         if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 251             usage & PIPE_TRANSFER_WRITE &&
 252             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 253                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 254         }
 255
 256         /* If discarding the entire range, discard the whole resource instead. */
 257         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 258             box->x == 0 && box->width == resource->width0) {
 259                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 260         }
 261
 262         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 263             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 264                 assert(usage & PIPE_TRANSFER_WRITE);
 265
 266                 /* Check if mapping this buffer would cause waiting for the GPU. */
 267                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 268                     rctx->ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
 269                         rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 270                 }
 271                 /* At this point, the buffer is always idle. */
 272                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 273         }
 274         else if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 275                  !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 276                  !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 277                  r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) {
 278                 assert(usage & PIPE_TRANSFER_WRITE);
 279
 280                 /* Check if mapping this buffer would cause waiting for the GPU. */
 281                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 282                     rctx->ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
 283                         /* Do a wait-free write-only transfer using a temporary buffer. */
 284                         unsigned offset;
 285                         struct r600_resource *staging = NULL;
 286
 287                         u_upload_alloc(rctx->uploader, 0, box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 288                                        &offset, (struct pipe_resource**)&staging, (void**)&data);
 289
 290                         if (staging) {
 291                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 292                                 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 293                                                                 ptransfer, data, staging, offset);
 294                         } else {
 295                                 return NULL; /* error, shouldn't occur though */
 296                         }
 297                 }
 298                 /* At this point, the buffer is always idle (we checked it above). */
 299                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 300         }
 301         /* Using a staging buffer in GTT for larger reads is much faster. */
 302         else if ((usage & PIPE_TRANSFER_READ) &&
 303                  !(usage & PIPE_TRANSFER_WRITE) &&
 304                  rbuffer->domains == RADEON_DOMAIN_VRAM &&
 305                  r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) {
 306                 unsigned offset;
 307                 struct r600_resource *staging = NULL;
 308
 309                 u_upload_alloc(rctx->uploader, 0,
 310                                box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 311                                &offset, (struct pipe_resource**)&staging, (void**)&data);
 312
 313                 if (staging) {
 314                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 315
 316                         /* Copy the VRAM buffer to the staging buffer. */
 317                         rctx->dma_copy(ctx, &staging->b.b, 0,
 318                                        offset + box->x % R600_MAP_BUFFER_ALIGNMENT,
 319                                        0, 0, resource, level, box);
 320
 321                         /* Just do the synchronization. The buffer is mapped already. */
 322                         r600_buffer_map_sync_with_rings(rctx, staging, PIPE_TRANSFER_READ);
 323
 324                         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 325                                                         ptransfer, data, staging, offset);
 326                 }
 327         }
 328
 329         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 330         if (!data) {
 331                 return NULL;
 332         }
 333         data += box->x;
 334
 335         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 336                                         ptransfer, data, NULL, 0);
 337 }
 338
 339 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 340                                        struct pipe_transfer *transfer)
 341 {
 342         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 343         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 344         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 345
 346         if (rtransfer->staging) {
 347                 if (rtransfer->transfer.usage & PIPE_TRANSFER_WRITE) {
 348                         struct pipe_resource *dst, *src;
 349                         unsigned soffset, doffset, size;
 350                         struct pipe_box box;
 351
 352                         dst = transfer->resource;
 353                         src = &rtransfer->staging->b.b;
 354                         size = transfer->box.width;
 355                         doffset = transfer->box.x;
 356                         soffset = rtransfer->offset + transfer->box.x % R600_MAP_BUFFER_ALIGNMENT;
 357
 358                         u_box_1d(soffset, size, &box);
 359
 360                         /* Copy the staging buffer into the original one. */
 361                         rctx->dma_copy(ctx, dst, 0, doffset, 0, 0, src, 0, &box);
 362                 }
 363                 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
 364         }
 365
 366         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 367                 util_range_add(&rbuffer->valid_buffer_range, transfer->box.x,
 368                                transfer->box.x + transfer->box.width);
 369         }
 370         util_slab_free(&rctx->pool_transfers, transfer);
 371 }
 372
 373 static const struct u_resource_vtbl r600_buffer_vtbl =
 374 {
 375         NULL,                           /* get_handle */
 376         r600_buffer_destroy,            /* resource_destroy */
 377         r600_buffer_transfer_map,       /* transfer_map */
 378         NULL,                           /* transfer_flush_region */
 379         r600_buffer_transfer_unmap,     /* transfer_unmap */
 380         NULL                            /* transfer_inline_write */
 381 };
 382
 383 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 384                                          const struct pipe_resource *templ,
 385                                          unsigned alignment)
 386 {
 387         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 388         struct r600_resource *rbuffer;
 389
 390         rbuffer = MALLOC_STRUCT(r600_resource);
 391
 392         rbuffer->b.b = *templ;
 393         pipe_reference_init(&rbuffer->b.b.reference, 1);
 394         rbuffer->b.b.screen = screen;
 395         rbuffer->b.vtbl = &r600_buffer_vtbl;
 396         rbuffer->buf = NULL;
 397         util_range_init(&rbuffer->valid_buffer_range);
 398
 399         if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE)) {
 400                 FREE(rbuffer);
 401                 return NULL;
 402         }
 403         return &rbuffer->b.b;
 404 }