src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                         struct radeon_winsys_cs_handle *buf,
  35                                         enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
  38                 return TRUE;
  39         }
  40         if (ctx->rings.dma.cs &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
  42                 return TRUE;
  43         }
  44         return FALSE;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52         bool busy = false;
  53
  54         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  55                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
  56         }
  57
  58         if (!(usage & PIPE_TRANSFER_WRITE)) {
  59                 /* have to wait for the last write */
  60                 rusage = RADEON_USAGE_WRITE;
  61         }
  62
  63         if (ctx->rings.gfx.cs->cdw != ctx->initial_gfx_cs_size &&
  64             ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs,
  65                                              resource->cs_buf, rusage)) {
  66                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  67                         ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
  68                         return NULL;
  69                 } else {
  70                         ctx->rings.gfx.flush(ctx, 0);
  71                         busy = true;
  72                 }
  73         }
  74         if (ctx->rings.dma.cs &&
  75             ctx->rings.dma.cs->cdw &&
  76             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs,
  77                                              resource->cs_buf, rusage)) {
  78                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  79                         ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
  80                         return NULL;
  81                 } else {
  82                         ctx->rings.dma.flush(ctx, 0);
  83                         busy = true;
  84                 }
  85         }
  86
  87         if (busy || ctx->ws->buffer_is_busy(resource->buf, rusage)) {
  88                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  89                         return NULL;
  90                 } else {
  91                         /* We will be wait for the GPU. Wait for any offloaded
  92                          * CS flush to complete to avoid busy-waiting in the winsys. */
  93                         ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
  94                         if (ctx->rings.dma.cs)
  95                                 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
  96                 }
  97         }
  98
  99         /* Setting the CS to NULL will prevent doing checks we have done already. */
 100         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
 101 }
 102
 103 bool r600_init_resource(struct r600_common_screen *rscreen,
 104                         struct r600_resource *res,
 105                         unsigned size, unsigned alignment,
 106                         bool use_reusable_pool)
 107 {
 108         struct r600_texture *rtex = (struct r600_texture*)res;
 109
 110         switch (res->b.b.usage) {
 111         case PIPE_USAGE_STAGING:
 112         case PIPE_USAGE_DYNAMIC:
 113         case PIPE_USAGE_STREAM:
 114                 /* Transfers are likely to occur more often with these resources. */
 115                 res->domains = RADEON_DOMAIN_GTT;
 116                 break;
 117         case PIPE_USAGE_DEFAULT:
 118         case PIPE_USAGE_IMMUTABLE:
 119         default:
 120                 /* Not listing GTT here improves performance in some apps. */
 121                 res->domains = RADEON_DOMAIN_VRAM;
 122                 break;
 123         }
 124
 125         /* Use GTT for all persistent mappings, because they are
 126          * always cached and coherent. */
 127         if (res->b.b.target == PIPE_BUFFER &&
 128             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 129                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 130                 res->domains = RADEON_DOMAIN_GTT;
 131         }
 132
 133         /* Tiled textures are unmappable. Always put them in VRAM. */
 134         if (res->b.b.target != PIPE_BUFFER &&
 135             rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
 136                 res->domains = RADEON_DOMAIN_VRAM;
 137         }
 138
 139         /* Allocate the resource. */
 140         res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
 141                                               use_reusable_pool,
 142                                               res->domains);
 143         if (!res->buf) {
 144                 return false;
 145         }
 146
 147         res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf);
 148         util_range_set_empty(&res->valid_buffer_range);
 149
 150         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 151                 fprintf(stderr, "VM start=0x%"PRIu64"  end=0x%"PRIu64" | Buffer %u bytes\n",
 152                         r600_resource_va(&rscreen->b, &res->b.b),
 153                         r600_resource_va(&rscreen->b, &res->b.b) + res->buf->size,
 154                         res->buf->size);
 155         }
 156         return true;
 157 }
 158
 159 static void r600_buffer_destroy(struct pipe_screen *screen,
 160                                 struct pipe_resource *buf)
 161 {
 162         struct r600_resource *rbuffer = r600_resource(buf);
 163
 164         util_range_destroy(&rbuffer->valid_buffer_range);
 165         pb_reference(&rbuffer->buf, NULL);
 166         FREE(rbuffer);
 167 }
 168
 169 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 170                                       struct pipe_resource *resource,
 171                                       unsigned level,
 172                                       unsigned usage,
 173                                       const struct pipe_box *box,
 174                                       struct pipe_transfer **ptransfer,
 175                                       void *data, struct r600_resource *staging,
 176                                       unsigned offset)
 177 {
 178         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 179         struct r600_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
 180
 181         transfer->transfer.resource = resource;
 182         transfer->transfer.level = level;
 183         transfer->transfer.usage = usage;
 184         transfer->transfer.box = *box;
 185         transfer->transfer.stride = 0;
 186         transfer->transfer.layer_stride = 0;
 187         transfer->offset = offset;
 188         transfer->staging = staging;
 189         *ptransfer = &transfer->transfer;
 190         return data;
 191 }
 192
 193 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 194                                       struct pipe_resource *resource,
 195                                       unsigned level,
 196                                       unsigned usage,
 197                                       const struct pipe_box *box,
 198                                       struct pipe_transfer **ptransfer)
 199 {
 200         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 201         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 202         struct r600_resource *rbuffer = r600_resource(resource);
 203         uint8_t *data;
 204
 205         assert(box->x + box->width <= resource->width0);
 206
 207         /* See if the buffer range being mapped has never been initialized,
 208          * in which case it can be mapped unsynchronized. */
 209         if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 210             usage & PIPE_TRANSFER_WRITE &&
 211             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 212                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 213         }
 214
 215         /* If discarding the entire range, discard the whole resource instead. */
 216         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 217             box->x == 0 && box->width == resource->width0) {
 218                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 219         }
 220
 221         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 222             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 223                 assert(usage & PIPE_TRANSFER_WRITE);
 224
 225                 /* Check if mapping this buffer would cause waiting for the GPU. */
 226                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 227                     rctx->ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
 228                         rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 229                 }
 230                 /* At this point, the buffer is always idle. */
 231                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 232         }
 233         else if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 234                  !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 235                  !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 236                  (rscreen->has_cp_dma ||
 237                   (rscreen->has_streamout &&
 238                    /* The buffer range must be aligned to 4 with streamout. */
 239                    box->x % 4 == 0 && box->width % 4 == 0))) {
 240                 assert(usage & PIPE_TRANSFER_WRITE);
 241
 242                 /* Check if mapping this buffer would cause waiting for the GPU. */
 243                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 244                     rctx->ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
 245                         /* Do a wait-free write-only transfer using a temporary buffer. */
 246                         unsigned offset;
 247                         struct r600_resource *staging = NULL;
 248
 249                         u_upload_alloc(rctx->uploader, 0, box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 250                                        &offset, (struct pipe_resource**)&staging, (void**)&data);
 251
 252                         if (staging) {
 253                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 254                                 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 255                                                                 ptransfer, data, staging, offset);
 256                         } else {
 257                                 return NULL; /* error, shouldn't occur though */
 258                         }
 259                 }
 260                 /* At this point, the buffer is always idle (we checked it above). */
 261                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 262         }
 263
 264         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 265         if (!data) {
 266                 return NULL;
 267         }
 268         data += box->x;
 269
 270         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 271                                         ptransfer, data, NULL, 0);
 272 }
 273
 274 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 275                                        struct pipe_transfer *transfer)
 276 {
 277         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 278         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 279         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 280
 281         if (rtransfer->staging) {
 282                 struct pipe_resource *dst, *src;
 283                 unsigned soffset, doffset, size;
 284                 struct pipe_box box;
 285
 286                 dst = transfer->resource;
 287                 src = &rtransfer->staging->b.b;
 288                 size = transfer->box.width;
 289                 doffset = transfer->box.x;
 290                 soffset = rtransfer->offset + transfer->box.x % R600_MAP_BUFFER_ALIGNMENT;
 291
 292                 u_box_1d(soffset, size, &box);
 293
 294                 /* Copy the staging buffer into the original one. */
 295                 if (!(size % 4) && !(doffset % 4) && !(soffset % 4) &&
 296                     rctx->dma_copy(ctx, dst, 0, doffset, 0, 0, src, 0, &box)) {
 297                         /* DONE. */
 298                 } else {
 299                         ctx->resource_copy_region(ctx, dst, 0, doffset, 0, 0, src, 0, &box);
 300                 }
 301                 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
 302         }
 303
 304         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 305                 util_range_add(&rbuffer->valid_buffer_range, transfer->box.x,
 306                                transfer->box.x + transfer->box.width);
 307         }
 308         util_slab_free(&rctx->pool_transfers, transfer);
 309 }
 310
 311 static const struct u_resource_vtbl r600_buffer_vtbl =
 312 {
 313         NULL,                           /* get_handle */
 314         r600_buffer_destroy,            /* resource_destroy */
 315         r600_buffer_transfer_map,       /* transfer_map */
 316         NULL,                           /* transfer_flush_region */
 317         r600_buffer_transfer_unmap,     /* transfer_unmap */
 318         NULL                            /* transfer_inline_write */
 319 };
 320
 321 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 322                                          const struct pipe_resource *templ,
 323                                          unsigned alignment)
 324 {
 325         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 326         struct r600_resource *rbuffer;
 327
 328         rbuffer = MALLOC_STRUCT(r600_resource);
 329
 330         rbuffer->b.b = *templ;
 331         pipe_reference_init(&rbuffer->b.b.reference, 1);
 332         rbuffer->b.b.screen = screen;
 333         rbuffer->b.vtbl = &r600_buffer_vtbl;
 334         util_range_init(&rbuffer->valid_buffer_range);
 335
 336         if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE)) {
 337                 FREE(rbuffer);
 338                 return NULL;
 339         }
 340         return &rbuffer->b.b;
 341 }