src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include <inttypes.h>
  31 #include <stdio.h>
  32
  33 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  34                                         struct radeon_winsys_cs_handle *buf,
  35                                         enum radeon_bo_usage usage)
  36 {
  37         if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
  38                 return TRUE;
  39         }
  40         if (ctx->rings.dma.cs &&
  41             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
  42                 return TRUE;
  43         }
  44         return FALSE;
  45 }
  46
  47 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  48                                       struct r600_resource *resource,
  49                                       unsigned usage)
  50 {
  51         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  52
  53         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  54                 return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
  55         }
  56
  57         if (!(usage & PIPE_TRANSFER_WRITE)) {
  58                 /* have to wait for the last write */
  59                 rusage = RADEON_USAGE_WRITE;
  60         }
  61
  62         if (ctx->rings.gfx.cs->cdw &&
  63             ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs,
  64                                              resource->cs_buf, rusage)) {
  65                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  66                         ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
  67                         return NULL;
  68                 } else {
  69                         ctx->rings.gfx.flush(ctx, 0);
  70                 }
  71         }
  72         if (ctx->rings.dma.cs &&
  73             ctx->rings.dma.cs->cdw &&
  74             ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs,
  75                                              resource->cs_buf, rusage)) {
  76                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  77                         ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
  78                         return NULL;
  79                 } else {
  80                         ctx->rings.dma.flush(ctx, 0);
  81                 }
  82         }
  83
  84         if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
  85                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  86                         return NULL;
  87                 } else {
  88                         /* We will be wait for the GPU. Wait for any offloaded
  89                          * CS flush to complete to avoid busy-waiting in the winsys. */
  90                         ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
  91                         if (ctx->rings.dma.cs)
  92                                 ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
  93                 }
  94         }
  95
  96         return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
  97 }
  98
  99 bool r600_init_resource(struct r600_common_screen *rscreen,
 100                         struct r600_resource *res,
 101                         unsigned size, unsigned alignment,
 102                         bool use_reusable_pool, unsigned usage)
 103 {
 104         uint32_t initial_domain, domains;
 105
 106         switch(usage) {
 107         case PIPE_USAGE_STAGING:
 108                 /* Staging resources participate in transfers, i.e. are used
 109                  * for uploads and downloads from regular resources.
 110                  * We generate them internally for some transfers.
 111                  */
 112                 initial_domain = RADEON_DOMAIN_GTT;
 113                 domains = RADEON_DOMAIN_GTT;
 114                 break;
 115         case PIPE_USAGE_DYNAMIC:
 116         case PIPE_USAGE_STREAM:
 117                 /* Default to GTT, but allow the memory manager to move it to VRAM. */
 118                 initial_domain = RADEON_DOMAIN_GTT;
 119                 domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
 120                 break;
 121         case PIPE_USAGE_DEFAULT:
 122         case PIPE_USAGE_STATIC:
 123         case PIPE_USAGE_IMMUTABLE:
 124         default:
 125                 /* Don't list GTT here, because the memory manager would put some
 126                  * resources to GTT no matter what the initial domain is.
 127                  * Not listing GTT in the domains improves performance a lot. */
 128                 initial_domain = RADEON_DOMAIN_VRAM;
 129                 domains = RADEON_DOMAIN_VRAM;
 130                 break;
 131         }
 132
 133         res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
 134                                               use_reusable_pool,
 135                                               initial_domain);
 136         if (!res->buf) {
 137                 return false;
 138         }
 139
 140         res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf);
 141         res->domains = domains;
 142         util_range_set_empty(&res->valid_buffer_range);
 143
 144         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 145                 fprintf(stderr, "VM start=0x%"PRIu64"  end=0x%"PRIu64" | Buffer %u bytes\n",
 146                         r600_resource_va(&rscreen->b, &res->b.b),
 147                         r600_resource_va(&rscreen->b, &res->b.b) + res->buf->size,
 148                         res->buf->size);
 149         }
 150         return true;
 151 }
 152
 153 static void r600_buffer_destroy(struct pipe_screen *screen,
 154                                 struct pipe_resource *buf)
 155 {
 156         struct r600_resource *rbuffer = r600_resource(buf);
 157
 158         util_range_destroy(&rbuffer->valid_buffer_range);
 159         pb_reference(&rbuffer->buf, NULL);
 160         FREE(rbuffer);
 161 }
 162
 163 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 164                                       struct pipe_resource *resource,
 165                                       unsigned level,
 166                                       unsigned usage,
 167                                       const struct pipe_box *box,
 168                                       struct pipe_transfer **ptransfer,
 169                                       void *data, struct r600_resource *staging,
 170                                       unsigned offset)
 171 {
 172         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 173         struct r600_transfer *transfer = util_slab_alloc(&rctx->pool_transfers);
 174
 175         transfer->transfer.resource = resource;
 176         transfer->transfer.level = level;
 177         transfer->transfer.usage = usage;
 178         transfer->transfer.box = *box;
 179         transfer->transfer.stride = 0;
 180         transfer->transfer.layer_stride = 0;
 181         transfer->offset = offset;
 182         transfer->staging = staging;
 183         *ptransfer = &transfer->transfer;
 184         return data;
 185 }
 186
 187 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 188                                       struct pipe_resource *resource,
 189                                       unsigned level,
 190                                       unsigned usage,
 191                                       const struct pipe_box *box,
 192                                       struct pipe_transfer **ptransfer)
 193 {
 194         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 195         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 196         struct r600_resource *rbuffer = r600_resource(resource);
 197         uint8_t *data;
 198
 199         assert(box->x + box->width <= resource->width0);
 200
 201         /* See if the buffer range being mapped has never been initialized,
 202          * in which case it can be mapped unsynchronized. */
 203         if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 204             usage & PIPE_TRANSFER_WRITE &&
 205             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 206                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 207         }
 208
 209         /* If discarding the entire range, discard the whole resource instead. */
 210         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 211             box->x == 0 && box->width == resource->width0) {
 212                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 213         }
 214
 215         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 216             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 217                 assert(usage & PIPE_TRANSFER_WRITE);
 218
 219                 /* Check if mapping this buffer would cause waiting for the GPU. */
 220                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 221                     rctx->ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
 222                         rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 223                 }
 224                 /* At this point, the buffer is always idle. */
 225                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 226         }
 227         else if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 228                  !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 229                  !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 230                  (rscreen->has_cp_dma ||
 231                   (rscreen->has_streamout &&
 232                    /* The buffer range must be aligned to 4 with streamout. */
 233                    box->x % 4 == 0 && box->width % 4 == 0))) {
 234                 assert(usage & PIPE_TRANSFER_WRITE);
 235
 236                 /* Check if mapping this buffer would cause waiting for the GPU. */
 237                 if (r600_rings_is_buffer_referenced(rctx, rbuffer->cs_buf, RADEON_USAGE_READWRITE) ||
 238                     rctx->ws->buffer_is_busy(rbuffer->buf, RADEON_USAGE_READWRITE)) {
 239                         /* Do a wait-free write-only transfer using a temporary buffer. */
 240                         unsigned offset;
 241                         struct r600_resource *staging = NULL;
 242
 243                         u_upload_alloc(rctx->uploader, 0, box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 244                                        &offset, (struct pipe_resource**)&staging, (void**)&data);
 245
 246                         if (staging) {
 247                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 248                                 return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 249                                                                 ptransfer, data, staging, offset);
 250                         }
 251                 }
 252         }
 253
 254         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 255         if (!data) {
 256                 return NULL;
 257         }
 258         data += box->x;
 259
 260         return r600_buffer_get_transfer(ctx, resource, level, usage, box,
 261                                         ptransfer, data, NULL, 0);
 262 }
 263
 264 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 265                                        struct pipe_transfer *transfer)
 266 {
 267         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 268         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 269         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 270
 271         if (rtransfer->staging) {
 272                 struct pipe_resource *dst, *src;
 273                 unsigned soffset, doffset, size;
 274                 struct pipe_box box;
 275
 276                 dst = transfer->resource;
 277                 src = &rtransfer->staging->b.b;
 278                 size = transfer->box.width;
 279                 doffset = transfer->box.x;
 280                 soffset = rtransfer->offset + transfer->box.x % R600_MAP_BUFFER_ALIGNMENT;
 281
 282                 u_box_1d(soffset, size, &box);
 283
 284                 /* Copy the staging buffer into the original one. */
 285                 if (!(size % 4) && !(doffset % 4) && !(soffset % 4) &&
 286                     rctx->dma_copy(ctx, dst, 0, doffset, 0, 0, src, 0, &box)) {
 287                         /* DONE. */
 288                 } else {
 289                         ctx->resource_copy_region(ctx, dst, 0, doffset, 0, 0, src, 0, &box);
 290                 }
 291                 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
 292         }
 293
 294         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 295                 util_range_add(&rbuffer->valid_buffer_range, transfer->box.x,
 296                                transfer->box.x + transfer->box.width);
 297         }
 298         util_slab_free(&rctx->pool_transfers, transfer);
 299 }
 300
 301 static const struct u_resource_vtbl r600_buffer_vtbl =
 302 {
 303         NULL,                           /* get_handle */
 304         r600_buffer_destroy,            /* resource_destroy */
 305         r600_buffer_transfer_map,       /* transfer_map */
 306         NULL,                           /* transfer_flush_region */
 307         r600_buffer_transfer_unmap,     /* transfer_unmap */
 308         NULL                            /* transfer_inline_write */
 309 };
 310
 311 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 312                                          const struct pipe_resource *templ,
 313                                          unsigned alignment)
 314 {
 315         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 316         struct r600_resource *rbuffer;
 317
 318         rbuffer = MALLOC_STRUCT(r600_resource);
 319
 320         rbuffer->b.b = *templ;
 321         pipe_reference_init(&rbuffer->b.b.reference, 1);
 322         rbuffer->b.b.screen = screen;
 323         rbuffer->b.vtbl = &r600_buffer_vtbl;
 324         util_range_init(&rbuffer->valid_buffer_range);
 325
 326         if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE, templ->usage)) {
 327                 FREE(rbuffer);
 328                 return NULL;
 329         }
 330         return &rbuffer->b.b;
 331 }