src/gallium/drivers/radeon/r600_buffer_common.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák
  25  */
  26
  27 #include "r600_cs.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_upload_mgr.h"
  30 #include "util/u_threaded_context.h"
  31 #include <inttypes.h>
  32 #include <stdio.h>
  33
  34 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
  35                                      struct pb_buffer *buf,
  36                                      enum radeon_bo_usage usage)
  37 {
  38         if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
  39                 return true;
  40         }
  41         if (radeon_emitted(ctx->dma.cs, 0) &&
  42             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
  43                 return true;
  44         }
  45         return false;
  46 }
  47
  48 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
  49                                       struct r600_resource *resource,
  50                                       unsigned usage)
  51 {
  52         enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
  53         bool busy = false;
  54
  55         assert(!(resource->flags & RADEON_FLAG_SPARSE));
  56
  57         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
  58                 return ctx->ws->buffer_map(resource->buf, NULL, usage);
  59         }
  60
  61         if (!(usage & PIPE_TRANSFER_WRITE)) {
  62                 /* have to wait for the last write */
  63                 rusage = RADEON_USAGE_WRITE;
  64         }
  65
  66         if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
  67             ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
  68                                              resource->buf, rusage)) {
  69                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  70                         ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  71                         return NULL;
  72                 } else {
  73                         ctx->gfx.flush(ctx, 0, NULL);
  74                         busy = true;
  75                 }
  76         }
  77         if (radeon_emitted(ctx->dma.cs, 0) &&
  78             ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
  79                                              resource->buf, rusage)) {
  80                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  81                         ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
  82                         return NULL;
  83                 } else {
  84                         ctx->dma.flush(ctx, 0, NULL);
  85                         busy = true;
  86                 }
  87         }
  88
  89         if (busy || !ctx->ws->buffer_wait(resource->buf, 0, rusage)) {
  90                 if (usage & PIPE_TRANSFER_DONTBLOCK) {
  91                         return NULL;
  92                 } else {
  93                         /* We will be wait for the GPU. Wait for any offloaded
  94                          * CS flush to complete to avoid busy-waiting in the winsys. */
  95                         ctx->ws->cs_sync_flush(ctx->gfx.cs);
  96                         if (ctx->dma.cs)
  97                                 ctx->ws->cs_sync_flush(ctx->dma.cs);
  98                 }
  99         }
 100
 101         /* Setting the CS to NULL will prevent doing checks we have done already. */
 102         return ctx->ws->buffer_map(resource->buf, NULL, usage);
 103 }
 104
 105 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 106                                struct r600_resource *res,
 107                                uint64_t size, unsigned alignment)
 108 {
 109         struct r600_texture *rtex = (struct r600_texture*)res;
 110
 111         res->bo_size = size;
 112         res->bo_alignment = alignment;
 113         res->flags = 0;
 114
 115         switch (res->b.b.usage) {
 116         case PIPE_USAGE_STREAM:
 117                 res->flags = RADEON_FLAG_GTT_WC;
 118                 /* fall through */
 119         case PIPE_USAGE_STAGING:
 120                 /* Transfers are likely to occur more often with these
 121                  * resources. */
 122                 res->domains = RADEON_DOMAIN_GTT;
 123                 break;
 124         case PIPE_USAGE_DYNAMIC:
 125                 /* Older kernels didn't always flush the HDP cache before
 126                  * CS execution
 127                  */
 128                 if (rscreen->info.drm_major == 2 &&
 129                     rscreen->info.drm_minor < 40) {
 130                         res->domains = RADEON_DOMAIN_GTT;
 131                         res->flags |= RADEON_FLAG_GTT_WC;
 132                         break;
 133                 }
 134                 res->flags |= RADEON_FLAG_CPU_ACCESS;
 135                 /* fall through */
 136         case PIPE_USAGE_DEFAULT:
 137         case PIPE_USAGE_IMMUTABLE:
 138         default:
 139                 /* Not listing GTT here improves performance in some
 140                  * apps. */
 141                 res->domains = RADEON_DOMAIN_VRAM;
 142                 res->flags |= RADEON_FLAG_GTT_WC;
 143                 break;
 144         }
 145
 146         if (res->b.b.target == PIPE_BUFFER &&
 147             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 148                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 149                 /* Use GTT for all persistent mappings with older
 150                  * kernels, because they didn't always flush the HDP
 151                  * cache before CS execution.
 152                  *
 153                  * Write-combined CPU mappings are fine, the kernel
 154                  * ensures all CPU writes finish before the GPU
 155                  * executes a command stream.
 156                  */
 157                 if (rscreen->info.drm_major == 2 &&
 158                     rscreen->info.drm_minor < 40)
 159                         res->domains = RADEON_DOMAIN_GTT;
 160                 else if (res->domains & RADEON_DOMAIN_VRAM)
 161                         res->flags |= RADEON_FLAG_CPU_ACCESS;
 162         }
 163
 164         /* Tiled textures are unmappable. Always put them in VRAM. */
 165         if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
 166             res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
 167                 res->domains = RADEON_DOMAIN_VRAM;
 168                 res->flags &= ~RADEON_FLAG_CPU_ACCESS;
 169                 res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 170                          RADEON_FLAG_GTT_WC;
 171         }
 172
 173         /* If VRAM is just stolen system memory, allow both VRAM and
 174          * GTT, whichever has free space. If a buffer is evicted from
 175          * VRAM to GTT, it will stay there.
 176          *
 177          * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
 178          * placements even with a low amount of stolen VRAM.
 179          */
 180         if (!rscreen->info.has_dedicated_vram &&
 181             (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
 182             res->domains == RADEON_DOMAIN_VRAM)
 183                 res->domains = RADEON_DOMAIN_VRAM_GTT;
 184
 185         if (rscreen->debug_flags & DBG_NO_WC)
 186                 res->flags &= ~RADEON_FLAG_GTT_WC;
 187
 188         /* Set expected VRAM and GART usage for the buffer. */
 189         res->vram_usage = 0;
 190         res->gart_usage = 0;
 191
 192         if (res->domains & RADEON_DOMAIN_VRAM)
 193                 res->vram_usage = size;
 194         else if (res->domains & RADEON_DOMAIN_GTT)
 195                 res->gart_usage = size;
 196 }
 197
 198 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 199                          struct r600_resource *res)
 200 {
 201         struct pb_buffer *old_buf, *new_buf;
 202
 203         /* Allocate a new resource. */
 204         new_buf = rscreen->ws->buffer_create(rscreen->ws, res->bo_size,
 205                                              res->bo_alignment,
 206                                              res->domains, res->flags);
 207         if (!new_buf) {
 208                 return false;
 209         }
 210
 211         /* Replace the pointer such that if res->buf wasn't NULL, it won't be
 212          * NULL. This should prevent crashes with multiple contexts using
 213          * the same buffer where one of the contexts invalidates it while
 214          * the others are using it. */
 215         old_buf = res->buf;
 216         res->buf = new_buf; /* should be atomic */
 217
 218         if (rscreen->info.has_virtual_memory)
 219                 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
 220         else
 221                 res->gpu_address = 0;
 222
 223         pb_reference(&old_buf, NULL);
 224
 225         util_range_set_empty(&res->valid_buffer_range);
 226         res->TC_L2_dirty = false;
 227
 228         /* Print debug information. */
 229         if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 230                 fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 231                         res->gpu_address, res->gpu_address + res->buf->size,
 232                         res->buf->size);
 233         }
 234         return true;
 235 }
 236
 237 static void r600_buffer_destroy(struct pipe_screen *screen,
 238                                 struct pipe_resource *buf)
 239 {
 240         struct r600_resource *rbuffer = r600_resource(buf);
 241
 242         util_range_destroy(&rbuffer->valid_buffer_range);
 243         pb_reference(&rbuffer->buf, NULL);
 244         FREE(rbuffer);
 245 }
 246
 247 static bool
 248 r600_invalidate_buffer(struct r600_common_context *rctx,
 249                        struct r600_resource *rbuffer)
 250 {
 251         /* Shared buffers can't be reallocated. */
 252         if (rbuffer->is_shared)
 253                 return false;
 254
 255         /* Sparse buffers can't be reallocated. */
 256         if (rbuffer->flags & RADEON_FLAG_SPARSE)
 257                 return false;
 258
 259         /* In AMD_pinned_memory, the user pointer association only gets
 260          * broken when the buffer is explicitly re-allocated.
 261          */
 262         if (rctx->ws->buffer_is_user_ptr(rbuffer->buf))
 263                 return false;
 264
 265         /* Check if mapping this buffer would cause waiting for the GPU. */
 266         if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 267             !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 268                 rctx->invalidate_buffer(&rctx->b, &rbuffer->b.b);
 269         } else {
 270                 util_range_set_empty(&rbuffer->valid_buffer_range);
 271         }
 272
 273         return true;
 274 }
 275
 276 void r600_invalidate_resource(struct pipe_context *ctx,
 277                               struct pipe_resource *resource)
 278 {
 279         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 280         struct r600_resource *rbuffer = r600_resource(resource);
 281
 282         /* We currently only do anyting here for buffers */
 283         if (resource->target == PIPE_BUFFER)
 284                 (void)r600_invalidate_buffer(rctx, rbuffer);
 285 }
 286
 287 static void *r600_buffer_get_transfer(struct pipe_context *ctx,
 288                                       struct pipe_resource *resource,
 289                                       unsigned usage,
 290                                       const struct pipe_box *box,
 291                                       struct pipe_transfer **ptransfer,
 292                                       void *data, struct r600_resource *staging,
 293                                       unsigned offset)
 294 {
 295         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 296         struct r600_transfer *transfer;
 297
 298         if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
 299                 transfer = slab_alloc(&rctx->pool_transfers_unsync);
 300         else
 301                 transfer = slab_alloc(&rctx->pool_transfers);
 302
 303         transfer->transfer.resource = NULL;
 304         pipe_resource_reference(&transfer->transfer.resource, resource);
 305         transfer->transfer.level = 0;
 306         transfer->transfer.usage = usage;
 307         transfer->transfer.box = *box;
 308         transfer->transfer.stride = 0;
 309         transfer->transfer.layer_stride = 0;
 310         transfer->offset = offset;
 311         transfer->staging = staging;
 312         *ptransfer = &transfer->transfer;
 313         return data;
 314 }
 315
 316 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 317                                      unsigned dstx, unsigned srcx, unsigned size)
 318 {
 319         bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);
 320
 321         return rctx->screen->has_cp_dma ||
 322                (dword_aligned && (rctx->dma.cs ||
 323                                   rctx->screen->has_streamout));
 324
 325 }
 326
 327 static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 328                                       struct pipe_resource *resource,
 329                                       unsigned level,
 330                                       unsigned usage,
 331                                       const struct pipe_box *box,
 332                                       struct pipe_transfer **ptransfer)
 333 {
 334         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 335         struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
 336         struct r600_resource *rbuffer = r600_resource(resource);
 337         uint8_t *data;
 338
 339         assert(box->x + box->width <= resource->width0);
 340
 341         /* From GL_AMD_pinned_memory issues:
 342          *
 343          *     4) Is glMapBuffer on a shared buffer guaranteed to return the
 344          *        same system address which was specified at creation time?
 345          *
 346          *        RESOLVED: NO. The GL implementation might return a different
 347          *        virtual mapping of that memory, although the same physical
 348          *        page will be used.
 349          *
 350          * So don't ever use staging buffers.
 351          */
 352         if (rscreen->ws->buffer_is_user_ptr(rbuffer->buf))
 353                 usage |= PIPE_TRANSFER_PERSISTENT;
 354
 355         /* See if the buffer range being mapped has never been initialized,
 356          * in which case it can be mapped unsynchronized. */
 357         if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 358                        TC_TRANSFER_MAP_IGNORE_VALID_RANGE)) &&
 359             usage & PIPE_TRANSFER_WRITE &&
 360             !rbuffer->is_shared &&
 361             !util_ranges_intersect(&rbuffer->valid_buffer_range, box->x, box->x + box->width)) {
 362                 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 363         }
 364
 365         /* If discarding the entire range, discard the whole resource instead. */
 366         if (usage & PIPE_TRANSFER_DISCARD_RANGE &&
 367             box->x == 0 && box->width == resource->width0) {
 368                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 369         }
 370
 371         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE &&
 372             !(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 373                        TC_TRANSFER_MAP_NO_INVALIDATE))) {
 374                 assert(usage & PIPE_TRANSFER_WRITE);
 375
 376                 if (r600_invalidate_buffer(rctx, rbuffer)) {
 377                         /* At this point, the buffer is always idle. */
 378                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 379                 } else {
 380                         /* Fall back to a temporary buffer. */
 381                         usage |= PIPE_TRANSFER_DISCARD_RANGE;
 382                 }
 383         }
 384
 385         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 386             !(rscreen->debug_flags & DBG_NO_DISCARD_RANGE) &&
 387             ((!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
 388                          PIPE_TRANSFER_PERSISTENT)) &&
 389               r600_can_dma_copy_buffer(rctx, box->x, 0, box->width)) ||
 390              (rbuffer->flags & RADEON_FLAG_SPARSE))) {
 391                 assert(usage & PIPE_TRANSFER_WRITE);
 392
 393                 /* Check if mapping this buffer would cause waiting for the GPU.
 394                  */
 395                 if (rbuffer->flags & RADEON_FLAG_SPARSE ||
 396                     r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 397                     !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 398                         /* Do a wait-free write-only transfer using a temporary buffer. */
 399                         unsigned offset;
 400                         struct r600_resource *staging = NULL;
 401
 402                         u_upload_alloc(ctx->stream_uploader, 0,
 403                                        box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
 404                                        rctx->screen->info.tcc_cache_line_size,
 405                                        &offset, (struct pipe_resource**)&staging,
 406                                        (void**)&data);
 407
 408                         if (staging) {
 409                                 data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 410                                 return r600_buffer_get_transfer(ctx, resource, usage, box,
 411                                                                 ptransfer, data, staging, offset);
 412                         } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 413                                 return NULL;
 414                         }
 415                 } else {
 416                         /* At this point, the buffer is always idle (we checked it above). */
 417                         usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
 418                 }
 419         }
 420         /* Use a staging buffer in cached GTT for reads. */
 421         else if (((usage & PIPE_TRANSFER_READ) &&
 422                   !(usage & PIPE_TRANSFER_PERSISTENT) &&
 423                   (rbuffer->domains & RADEON_DOMAIN_VRAM ||
 424                    rbuffer->flags & RADEON_FLAG_GTT_WC) &&
 425                   r600_can_dma_copy_buffer(rctx, 0, box->x, box->width)) ||
 426                  (rbuffer->flags & RADEON_FLAG_SPARSE)) {
 427                 struct r600_resource *staging;
 428
 429                 assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
 430                 staging = (struct r600_resource*) pipe_buffer_create(
 431                                 ctx->screen, 0, PIPE_USAGE_STAGING,
 432                                 box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
 433                 if (staging) {
 434                         /* Copy the VRAM buffer to the staging buffer. */
 435                         rctx->dma_copy(ctx, &staging->b.b, 0,
 436                                        box->x % R600_MAP_BUFFER_ALIGNMENT,
 437                                        0, 0, resource, 0, box);
 438
 439                         data = r600_buffer_map_sync_with_rings(rctx, staging,
 440                                                                usage & ~PIPE_TRANSFER_UNSYNCHRONIZED);
 441                         if (!data) {
 442                                 r600_resource_reference(&staging, NULL);
 443                                 return NULL;
 444                         }
 445                         data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 446
 447                         return r600_buffer_get_transfer(ctx, resource, usage, box,
 448                                                         ptransfer, data, staging, 0);
 449                 } else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
 450                         return NULL;
 451                 }
 452         }
 453
 454         data = r600_buffer_map_sync_with_rings(rctx, rbuffer, usage);
 455         if (!data) {
 456                 return NULL;
 457         }
 458         data += box->x;
 459
 460         return r600_buffer_get_transfer(ctx, resource, usage, box,
 461                                         ptransfer, data, NULL, 0);
 462 }
 463
 464 static void r600_buffer_do_flush_region(struct pipe_context *ctx,
 465                                         struct pipe_transfer *transfer,
 466                                         const struct pipe_box *box)
 467 {
 468         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 469         struct r600_resource *rbuffer = r600_resource(transfer->resource);
 470
 471         if (rtransfer->staging) {
 472                 struct pipe_resource *dst, *src;
 473                 unsigned soffset;
 474                 struct pipe_box dma_box;
 475
 476                 dst = transfer->resource;
 477                 src = &rtransfer->staging->b.b;
 478                 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
 479
 480                 u_box_1d(soffset, box->width, &dma_box);
 481
 482                 /* Copy the staging buffer into the original one. */
 483                 ctx->resource_copy_region(ctx, dst, 0, box->x, 0, 0, src, 0, &dma_box);
 484         }
 485
 486         util_range_add(&rbuffer->valid_buffer_range, box->x,
 487                        box->x + box->width);
 488 }
 489
 490 static void r600_buffer_flush_region(struct pipe_context *ctx,
 491                                      struct pipe_transfer *transfer,
 492                                      const struct pipe_box *rel_box)
 493 {
 494         unsigned required_usage = PIPE_TRANSFER_WRITE |
 495                                   PIPE_TRANSFER_FLUSH_EXPLICIT;
 496
 497         if ((transfer->usage & required_usage) == required_usage) {
 498                 struct pipe_box box;
 499
 500                 u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
 501                 r600_buffer_do_flush_region(ctx, transfer, &box);
 502         }
 503 }
 504
 505 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
 506                                        struct pipe_transfer *transfer)
 507 {
 508         struct r600_common_context *rctx = (struct r600_common_context*)ctx;
 509         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 510
 511         if (transfer->usage & PIPE_TRANSFER_WRITE &&
 512             !(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
 513                 r600_buffer_do_flush_region(ctx, transfer, &transfer->box);
 514
 515         if (rtransfer->staging)
 516                 r600_resource_reference(&rtransfer->staging, NULL);
 517
 518         pipe_resource_reference(&transfer->resource, NULL);
 519
 520         /* Don't use pool_transfers_unsync. We are always in the driver
 521          * thread. */
 522         slab_free(&rctx->pool_transfers, transfer);
 523 }
 524
 525 void r600_buffer_subdata(struct pipe_context *ctx,
 526                          struct pipe_resource *buffer,
 527                          unsigned usage, unsigned offset,
 528                          unsigned size, const void *data)
 529 {
 530         struct pipe_transfer *transfer = NULL;
 531         struct pipe_box box;
 532         uint8_t *map = NULL;
 533
 534         u_box_1d(offset, size, &box);
 535         map = r600_buffer_transfer_map(ctx, buffer, 0,
 536                                        PIPE_TRANSFER_WRITE |
 537                                        PIPE_TRANSFER_DISCARD_RANGE |
 538                                        usage,
 539                                        &box, &transfer);
 540         if (!map)
 541                 return;
 542
 543         memcpy(map, data, size);
 544         r600_buffer_transfer_unmap(ctx, transfer);
 545 }
 546
 547 static const struct u_resource_vtbl r600_buffer_vtbl =
 548 {
 549         NULL,                           /* get_handle */
 550         r600_buffer_destroy,            /* resource_destroy */
 551         r600_buffer_transfer_map,       /* transfer_map */
 552         r600_buffer_flush_region,       /* transfer_flush_region */
 553         r600_buffer_transfer_unmap,     /* transfer_unmap */
 554 };
 555
 556 static struct r600_resource *
 557 r600_alloc_buffer_struct(struct pipe_screen *screen,
 558                          const struct pipe_resource *templ)
 559 {
 560         struct r600_resource *rbuffer;
 561
 562         rbuffer = MALLOC_STRUCT(r600_resource);
 563
 564         rbuffer->b.b = *templ;
 565         rbuffer->b.b.next = NULL;
 566         pipe_reference_init(&rbuffer->b.b.reference, 1);
 567         rbuffer->b.b.screen = screen;
 568         rbuffer->b.vtbl = &r600_buffer_vtbl;
 569         rbuffer->buf = NULL;
 570         rbuffer->bind_history = 0;
 571         rbuffer->TC_L2_dirty = false;
 572         rbuffer->is_shared = false;
 573         util_range_init(&rbuffer->valid_buffer_range);
 574         return rbuffer;
 575 }
 576
 577 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 578                                          const struct pipe_resource *templ,
 579                                          unsigned alignment)
 580 {
 581         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 582         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 583
 584         r600_init_resource_fields(rscreen, rbuffer, templ->width0, alignment);
 585
 586         if (templ->bind & PIPE_BIND_SHARED)
 587                 rbuffer->flags |= RADEON_FLAG_HANDLE;
 588         if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
 589                 rbuffer->flags |= RADEON_FLAG_SPARSE;
 590
 591         if (!r600_alloc_resource(rscreen, rbuffer)) {
 592                 FREE(rbuffer);
 593                 return NULL;
 594         }
 595         return &rbuffer->b.b;
 596 }
 597
 598 struct pipe_resource *r600_aligned_buffer_create(struct pipe_screen *screen,
 599                                                  unsigned flags,
 600                                                  unsigned usage,
 601                                                  unsigned size,
 602                                                  unsigned alignment)
 603 {
 604         struct pipe_resource buffer;
 605
 606         memset(&buffer, 0, sizeof buffer);
 607         buffer.target = PIPE_BUFFER;
 608         buffer.format = PIPE_FORMAT_R8_UNORM;
 609         buffer.bind = 0;
 610         buffer.usage = usage;
 611         buffer.flags = flags;
 612         buffer.width0 = size;
 613         buffer.height0 = 1;
 614         buffer.depth0 = 1;
 615         buffer.array_size = 1;
 616         return r600_buffer_create(screen, &buffer, alignment);
 617 }
 618
 619 struct pipe_resource *
 620 r600_buffer_from_user_memory(struct pipe_screen *screen,
 621                              const struct pipe_resource *templ,
 622                              void *user_memory)
 623 {
 624         struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
 625         struct radeon_winsys *ws = rscreen->ws;
 626         struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 627
 628         rbuffer->domains = RADEON_DOMAIN_GTT;
 629         rbuffer->flags = 0;
 630         util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0);
 631
 632         /* Convert a user pointer to a buffer. */
 633         rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
 634         if (!rbuffer->buf) {
 635                 FREE(rbuffer);
 636                 return NULL;
 637         }
 638
 639         if (rscreen->info.has_virtual_memory)
 640                 rbuffer->gpu_address =
 641                         ws->buffer_get_virtual_address(rbuffer->buf);
 642         else
 643                 rbuffer->gpu_address = 0;
 644
 645         rbuffer->vram_usage = 0;
 646         rbuffer->gart_usage = templ->width0;
 647
 648         return &rbuffer->b.b;
 649 }